From patchwork Thu Nov 7 17:28:54 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kwok Cheung Yeung X-Patchwork-Id: 1191332 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-512739-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=codesourcery.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="y1re33iL"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4789PV6Mmtz9sNx for ; Fri, 8 Nov 2019 04:29:17 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :subject:to:message-id:date:mime-version:content-type :content-transfer-encoding; q=dns; s=default; b=FZRbLgeo2z10lQgw i/HATF0ZL1/c4FSkGpvwMDSx5QRguFLLWtGqB5PsouNzACu9K69Z8QvhBWjvpWac KlqqiFPtu3ZLyjhUq+oN/Boq8ppkur40VDOGmlbts0WFlqrrOrVNwTpo+CiHJXbn k3j1uPkRR08rYyKwJdDgWf/cTtY= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :subject:to:message-id:date:mime-version:content-type :content-transfer-encoding; s=default; bh=Lbzj9AHIQaLcJfz9sE1ySa Rma4o=; b=y1re33iLXyPoLxMnXxLTqu+ssJ31Zwhg9hfgq4sR7XUjZQW+cCLIcm gBGAizcFYqj8zEkaUWx6Pcv1KMLYU8sIGV2YrJnRTgWRrG3PT9vnnMUmc0c2aIFh OTYrWU/IrYaTYaJFm1GlOFKA4KuZ4N5t9rFXySKlAcOYE8CMHTEPQ= Received: (qmail 97861 invoked by alias); 7 Nov 2019 17:29:09 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 97853 invoked by uid 89); 7 Nov 2019 17:29:09 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-19.3 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3 autolearn=ham version=3.3.1 spammy=reloads, Assigning X-HELO: esa2.mentor.iphmx.com Received: from esa2.mentor.iphmx.com (HELO esa2.mentor.iphmx.com) (68.232.141.98) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 07 Nov 2019 17:29:08 +0000 IronPort-SDR: YIUas+O2vv/LjLxeY95ojhgbJ/YAZ6XmFGat756nDRGMkRePdfQGCdF/UY4TgBxmRjHY1k9Pl7 Yqn4l6q0jUKcNp8tq+5ArGsoWUjy6VUSPTGT8xMrxBVKO84LnVD+7QacRaHvVDiEqIZ0qLltFj d0glVZu8gCfzeYDDTW+epo7XFEkxv4Exeq6cRd6rdsH8n3Uzlr/1CUn4Key+/vFP+2RLstuHmu E8//uppOS3yAQxtCQewZwpZv5yEQLM5nKT51XDiq38mJmkb3ISKSZ0CaEftWk0e4Y3v06k9jsD ECs= Received: from orw-gwy-02-in.mentorg.com ([192.94.38.167]) by esa2.mentor.iphmx.com with ESMTP; 07 Nov 2019 09:29:06 -0800 IronPort-SDR: LRsvM5e5apD2lQI8mj1Z7WORoHzZ+9qkH/gWE5+UaPIvgRvvR7wJz+KDLZxWLit6DpFXgIfMUR qB1AtDptOg5iMrb+Mx5fvWrXwtFQYuKdaZqj3QOqdDmkZsaEmctRaDuTHasDQ02PUrlc1ffwGh zMVnwc0DMFvlfQG6M25vSbAoPNpMlXjMZJlX97pgQ5Ep6YF3P1c5co0+/nkFIxvlGodzd6+KkB B+V3bZT6ri6ViXc1DevzsnqkroEworXsxZPW8xaqotw3iENFialnYJunm0qqVnU/ngSS8C7AP/ 1oI= From: Kwok Cheung Yeung Subject: [PATCH] [LRA] Do not use eliminable registers for spilling To: , Vladimir Makarov Message-ID: <2ef934ad-ee64-51f6-138b-bb052327304a@codesourcery.com> Date: Thu, 7 Nov 2019 17:28:54 +0000 User-Agent: Mozilla/5.0 (Windows NT 10.0; Win64; x64; rv:68.0) Gecko/20100101 Thunderbird/68.2.1 MIME-Version: 1.0 Hello On AMD GCN, I encountered the following situation in the following testcases using the compilation flags '-O2 -ftracer -fsplit-paths': libgomp.oacc-fortran/reduction-1.f90 libgomp.oacc-fortran/reduction-2.f90 libgomp.oacc-fortran/reduction-3.f90 gcc.c-torture/execute/ieee/pr50310.c - LRA decides to spill a register to s14 (which is used for the hard frame pointer, but is not in use due to the -fomit-frame-pointer implied by -O2). The reload dump has: Spill r612 into hr14 ... (insn 597 711 712 2 (set (reg:BI 129 scc [612]) (ne:BI (reg:SI 2 s2 [684]) (const_int 0 [0]))) "reduction-1.f90":22:0 23 {cstoresi4} (nil)) ... (insn 710 713 598 2 (set (reg:BI 14 s14) (reg:BI 160 v0 [685])) "reduction-1.f90":22:0 3 {*movbi} (nil)) - Later on, LRA decides to allocate s14 to a pseudo: Assigning to 758 (cl=ALL_REGS, orig=758, freq=388, tfirst=758, tfreq=388)... Assign 14 to subreg reload r758 (freq=388) ... (insn 801 786 787 34 (set (reg:BI 14 s14 [758]) (reg:BI 163 v3 [758])) 3 {*movbi} (nil)) - But then the next BB reloads the value previously spilled into s14, which has been clobbered by previous instruction: (insn 733 144 732 9 (set (reg:BI 163 v3 [706]) (reg:BI 14 s14)) 3 {*movbi} (nil)) A similar issue has been dealt with in the past in PR83327, which was fixed in r258093. However, it does not work here - s14 is not marked as conflicting with pseudo 758. This is because s14 is in eliminable_regset - if HARD_FRAME_POINTER_IS_FRAME_POINTER is false, ira_setup_eliminable_regset puts HARD_FRAME_POINTER_REGNUM into eliminable_regset even if the frame pointer is not needed (Why is this? It seems to have been that way since IRA was introduced). At the beginning of process_bb_lives (in lra-lives.c), eliminable_regset is ~ANDed out of hard_regs_live, so even if s14 is in the live-outs of the BB, it will be removed from consideration when registering conflicts with pseudos in the BB. (As an aside, the liveness of eliminable spill registers would previously have been updated by make_hard_regno_live and make_hard_regno_dead, but as of r276440 '[LRA] Don't make eliminable registers live (PR91957)' this is no longer the case.) Given that conflicts with registers in eliminable_regset is not tracked, I believe the easiest fix is simply to prevent eliminable registers from being used as spill registers. Built and tested on AMD GCN with no regressions. I've bootstrapped it on x86_64, but there is no point testing on it ATM as TARGET_SPILL_CLASS was disabled in r237792. Okay for trunk? Kwok Yeung [LRA] Do not use eliminable registers for spilling 2019-11-07 Kwok Cheung Yeung gcc/ * lra-spills.c (assign_spill_hard_regs): Do not spill into registers in eliminable_regset. diff --git a/gcc/lra-spills.c b/gcc/lra-spills.c index 0068e52..54f76cc 100644 --- a/gcc/lra-spills.c +++ b/gcc/lra-spills.c @@ -283,6 +283,8 @@ assign_spill_hard_regs (int *pseudo_regnos, int n) for (k = 0; k < spill_class_size; k++) { hard_regno = ira_class_hard_regs[spill_class][k]; + if (TEST_HARD_REG_BIT (eliminable_regset, hard_regno)) + continue; if (! overlaps_hard_reg_set_p (conflict_hard_regs, mode, hard_regno)) break; }