From patchwork Sun Nov 3 20:33:28 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= X-Patchwork-Id: 1188611 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="ZlH456ju"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 475nhK733Zz9sNx for ; Mon, 4 Nov 2019 07:33:53 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728227AbfKCUdw (ORCPT ); Sun, 3 Nov 2019 15:33:52 -0500 Received: from mail-wr1-f44.google.com ([209.85.221.44]:33252 "EHLO mail-wr1-f44.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1728107AbfKCUdu (ORCPT ); Sun, 3 Nov 2019 15:33:50 -0500 Received: by mail-wr1-f44.google.com with SMTP id s1so14828017wro.0; Sun, 03 Nov 2019 12:33:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=9PTjPnnXrhQTEA6oIUuGKycZpquqSu0RexmpAAxMkKM=; b=ZlH456jue5FYNyvKFDvJTC8b7gFTI06byf1mM8aw5WgyBo4ojCRCowUP2DT2ubuHf9 y1WSgeXVZ8i0ev5i0RHeS65Bs4NzxP7FsUMfFLWxxiRAmBRK8wD//UekcAhltgA3BDeY Zkj6Wu0wDplSVusktSj3bdjNPJtjfI8nyLQ8+bpApciJrbyR6w5uAnsmkX2axlFiDKoE uBoGUpsF7RhyR2hlLKHUtdarf8yBJB1zB7IwxpJelg19g7yn/8M7aZvWj73O7D2Wcd44 3e8xSXzp0SQ+b1kt3DHGiOcoOaKUBwAlZ6Gt6hki/cMb8zeV9MFU46N5T3hVPtVFiy8G uE3Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9PTjPnnXrhQTEA6oIUuGKycZpquqSu0RexmpAAxMkKM=; b=d+fpfdI011vE/2OIw3ji7y8LpUk3h3Et62xCHLVmpE31Va4GNl56nPpLCWeodhuw9N GZDzEzL/A6+3qH3OFTZYhYGTNjARS6bOKEUDo2HnS7LIpta8zYqBf5xoCYFhTK37gr1k tj1CIihfLF+Pkqs7nWR2iWvWrtrv7vv1cuT/8NexD/okibkt7eldQhK316Q/kfzwzK4V zEnM/nu5IXbNNNtLDsMrvWpeuetknYCXysDibSGIsscdtkRwD1ZPEsMOwFxIskS4Oy3J 6qYpFCwHbw5rgZl0hiUDc79rEZV9WHJnrBR3ywVIMDyetLl5is1b2lbM89wovCj9BAV8 bRww== X-Gm-Message-State: APjAAAWFP7uvsEy2ezfhHEGtHStEfhlH6xXjNpquh0bbR/VBm/Q/rB5O Ot4Mw0bkN9FTtETJrm631NI= X-Google-Smtp-Source: APXvYqzrRKRa1dghpnaaDA+/4SyPPw2ng/Eh6/Ef282232gLUIpPYC5TN1vN6QY3Fqw+LbKZqVFLfQ== X-Received: by 2002:adf:ea11:: with SMTP id q17mr19979964wrm.83.1572813226641; Sun, 03 Nov 2019 12:33:46 -0800 (PST) Received: from localhost.localdomain ([2a01:e0a:1f1:d0f0::4e2b:d7ca]) by smtp.gmail.com with ESMTPSA id x16sm13644026wrp.91.2019.11.03.12.33.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Nov 2019 12:33:45 -0800 (PST) From: =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= To: Thierry Reding , =?utf-8?q?=27Uwe_Kleine-K?= =?utf-8?b?w7ZuaWcn?= , Rob Herring , Mark Rutland , Maxime Ripard , Chen-Yu Tsai Cc: linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Jernej Skrabec , =?utf-8?b?Q2zDqW1lbnQgUMOp?= =?utf-8?q?ron?= Subject: [PATCH v2 1/7] dt-bindings: pwm: allwinner: Add H6 PWM description Date: Sun, 3 Nov 2019 21:33:28 +0100 Message-Id: <20191103203334.10539-2-peron.clem@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191103203334.10539-1-peron.clem@gmail.com> References: <20191103203334.10539-1-peron.clem@gmail.com> MIME-Version: 1.0 Sender: linux-pwm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org From: Jernej Skrabec H6 PWM block is basically the same as A20 PWM, except that it also has bus clock and reset line which needs to be handled accordingly. Expand Allwinner PWM binding with H6 PWM specifics. Signed-off-by: Jernej Skrabec Signed-off-by: Clément Péron --- .../bindings/pwm/allwinner,sun4i-a10-pwm.yaml | 45 ++++++++++++++++++- 1 file changed, 44 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.yaml b/Documentation/devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.yaml index 0ac52f83a58c..bf36ea509f31 100644 --- a/Documentation/devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.yaml +++ b/Documentation/devicetree/bindings/pwm/allwinner,sun4i-a10-pwm.yaml @@ -30,13 +30,46 @@ properties: - items: - const: allwinner,sun50i-h5-pwm - const: allwinner,sun5i-a13-pwm + - const: allwinner,sun50i-h6-pwm reg: maxItems: 1 - clocks: + # Even though it only applies to subschemas under the conditionals, + # not listing them here will trigger a warning because of the + # additionalsProperties set to false. + clocks: true + clock-names: true + resets: maxItems: 1 + if: + properties: + compatible: + contains: + const: allwinner,sun50i-h6-pwm + + then: + properties: + clocks: + items: + - description: Module Clock + - description: Bus Clock + + clock-names: + items: + - const: mod + - const: bus + + required: + - clock-names + - resets + + else: + properties: + clocks: + maxItems: 1 + required: - "#pwm-cells" - compatible @@ -54,4 +87,14 @@ examples: #pwm-cells = <3>; }; + - | + pwm@300a000 { + compatible = "allwinner,sun50i-h6-pwm"; + reg = <0x0300a000 0x400>; + clocks = <&osc24M>, <&ccu CLK_BUS_PWM>; + clock-names = "mod", "bus"; + resets = <&ccu RST_BUS_PWM>; + #pwm-cells = <3>; + }; + ... From patchwork Sun Nov 3 20:33:29 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= X-Patchwork-Id: 1188609 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="ZQUt1nmR"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 475nhJ4Z9yz9sPL for ; Mon, 4 Nov 2019 07:33:52 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728201AbfKCUdu (ORCPT ); Sun, 3 Nov 2019 15:33:50 -0500 Received: from mail-wm1-f67.google.com ([209.85.128.67]:37393 "EHLO mail-wm1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727941AbfKCUdt (ORCPT ); Sun, 3 Nov 2019 15:33:49 -0500 Received: by mail-wm1-f67.google.com with SMTP id q130so13971227wme.2; Sun, 03 Nov 2019 12:33:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=dFi/U1rLrNtYEF4KWCZeapP9LyQz1KrI3hNiOLuNA64=; b=ZQUt1nmRM2FUbzYRthgFhs63Yvguqcf4AMFDBlwueb4W6j6t/ov+SAwCrRETGaIJQE t7Fj0TE4wHI7gocR1i1BJNL7a6SwNfgkKR0cDFXrjf1/uhjbGDCusfI4cvftb9xaYGJb robrcVE2VFFshdyIr2+0902/9v7nl3r6Scx+q/dyZ34o5XhdT+a8GKrGkfdFLxJgOrQs BzHAjQVpbkqQxpoyrKCY0QiTW9Odv8Rng1REsj4TmtILsOlr2Lf1HX6TYEtJ1EMrYS4k CnLlgDEGHSyG80fmMk4Xzn5ytEbV8EOmE/abaBCZrjWpTsrx/uk0Q230j39/7fFA3h9O rqFQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=dFi/U1rLrNtYEF4KWCZeapP9LyQz1KrI3hNiOLuNA64=; b=SKZgwWgAn0ikvOMVv1NcY4YZlcay5xE6C0O85yc+8TnkLElyW4+UiY6q15a8PfD8LS tgbu6KYGnMLh3xPXh3dVkMEDveuK32X9BOMJ96MUcaDbbF4GyAkrbHh0pR4CcJAI9cw8 JUrBH3ORnuaA+YjVja45OtwHaTd2hu85FOR3aD09G1XB+g+JAV70MwMqTWN/klAysFtq tBqUNhIqLhCDsqzZwCIdQp2iI5J9M3n8niGy8jAV4obPoDbsBsomqHiyYGY9bht4Q2JX lbrDhRrIQ9ED99YQtxcWV1LbnxI+q8hECdyAQYtIKfhCvxBSsXXpXkly8hPEZ9FsDune O7ew== X-Gm-Message-State: APjAAAVFrWjSDssvTkIsmW8rLxzFUarczBEKOLunYeBAjgW3h9qaHSrF AZBnSS1fYLAOgm2IdkkIqRs= X-Google-Smtp-Source: APXvYqyHGuQGzFLqWSs1hRl/bS7UtXf/0vTeNiNDZ0Jn7ft1yhN53cmPZImc/ucvSmsNoFapr7/39w== X-Received: by 2002:a05:600c:21d3:: with SMTP id x19mr19936742wmj.121.1572813227311; Sun, 03 Nov 2019 12:33:47 -0800 (PST) Received: from localhost.localdomain ([2a01:e0a:1f1:d0f0::4e2b:d7ca]) by smtp.gmail.com with ESMTPSA id x16sm13644026wrp.91.2019.11.03.12.33.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Nov 2019 12:33:46 -0800 (PST) From: =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= To: Thierry Reding , =?utf-8?q?=27Uwe_Kleine-K?= =?utf-8?b?w7ZuaWcn?= , Rob Herring , Mark Rutland , Maxime Ripard , Chen-Yu Tsai Cc: linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Jernej Skrabec , =?utf-8?b?Q2zDqW1lbnQgUMOp?= =?utf-8?q?ron?= Subject: [PATCH v2 2/7] pwm: sun4i: Add an optional probe for reset line Date: Sun, 3 Nov 2019 21:33:29 +0100 Message-Id: <20191103203334.10539-3-peron.clem@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191103203334.10539-1-peron.clem@gmail.com> References: <20191103203334.10539-1-peron.clem@gmail.com> MIME-Version: 1.0 Sender: linux-pwm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org From: Jernej Skrabec H6 PWM core needs deasserted reset line in order to work. Add an optional probe for it. Signed-off-by: Jernej Skrabec Signed-off-by: Clément Péron --- drivers/pwm/pwm-sun4i.c | 32 ++++++++++++++++++++++++++++++-- 1 file changed, 30 insertions(+), 2 deletions(-) diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c index 6f5840a1a82d..d194b8ebdb00 100644 --- a/drivers/pwm/pwm-sun4i.c +++ b/drivers/pwm/pwm-sun4i.c @@ -16,6 +16,7 @@ #include #include #include +#include #include #include #include @@ -78,6 +79,7 @@ struct sun4i_pwm_data { struct sun4i_pwm_chip { struct pwm_chip chip; struct clk *clk; + struct reset_control *rst; void __iomem *base; spinlock_t ctrl_lock; const struct sun4i_pwm_data *data; @@ -365,6 +367,20 @@ static int sun4i_pwm_probe(struct platform_device *pdev) if (IS_ERR(pwm->clk)) return PTR_ERR(pwm->clk); + pwm->rst = devm_reset_control_get_optional(&pdev->dev, NULL); + if (IS_ERR(pwm->rst)) { + if (PTR_ERR(pwm->rst) == -EPROBE_DEFER) + return PTR_ERR(pwm->rst); + dev_info(&pdev->dev, "no reset control found\n"); + } + + /* Deassert reset */ + ret = reset_control_deassert(pwm->rst); + if (ret) { + dev_err(&pdev->dev, "Cannot deassert reset control\n"); + return ret; + } + pwm->chip.dev = &pdev->dev; pwm->chip.ops = &sun4i_pwm_ops; pwm->chip.base = -1; @@ -377,19 +393,31 @@ static int sun4i_pwm_probe(struct platform_device *pdev) ret = pwmchip_add(&pwm->chip); if (ret < 0) { dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret); - return ret; + goto err_pwm_add; } platform_set_drvdata(pdev, pwm); return 0; + +err_pwm_add: + reset_control_assert(pwm->rst); + + return ret; } static int sun4i_pwm_remove(struct platform_device *pdev) { struct sun4i_pwm_chip *pwm = platform_get_drvdata(pdev); + int ret; + + ret = pwmchip_remove(&pwm->chip); + if (ret) + return ret; + + reset_control_assert(pwm->rst); - return pwmchip_remove(&pwm->chip); + return 0; } static struct platform_driver sun4i_pwm_driver = { From patchwork Sun Nov 3 20:33:30 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= X-Patchwork-Id: 1188617 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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Sun, 03 Nov 2019 12:33:48 -0800 (PST) Received: from localhost.localdomain ([2a01:e0a:1f1:d0f0::4e2b:d7ca]) by smtp.gmail.com with ESMTPSA id x16sm13644026wrp.91.2019.11.03.12.33.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Nov 2019 12:33:47 -0800 (PST) From: =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= To: Thierry Reding , =?utf-8?q?=27Uwe_Kleine-K?= =?utf-8?b?w7ZuaWcn?= , Rob Herring , Mark Rutland , Maxime Ripard , Chen-Yu Tsai Cc: linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Jernej Skrabec , =?utf-8?b?Q2zDqW1lbnQgUMOp?= =?utf-8?q?ron?= Subject: [PATCH v2 3/7] pwm: sun4i: Add an optional probe for bus clock Date: Sun, 3 Nov 2019 21:33:30 +0100 Message-Id: <20191103203334.10539-4-peron.clem@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191103203334.10539-1-peron.clem@gmail.com> References: <20191103203334.10539-1-peron.clem@gmail.com> MIME-Version: 1.0 Sender: linux-pwm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org From: Jernej Skrabec H6 PWM core needs bus clock to be enabled in order to work. Add an optional probe for it and a fallback for previous bindings without name on module clock. Signed-off-by: Jernej Skrabec Signed-off-by: Clément Péron --- drivers/pwm/pwm-sun4i.c | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+) diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c index d194b8ebdb00..b5e7ac364f59 100644 --- a/drivers/pwm/pwm-sun4i.c +++ b/drivers/pwm/pwm-sun4i.c @@ -78,6 +78,7 @@ struct sun4i_pwm_data { struct sun4i_pwm_chip { struct pwm_chip chip; + struct clk *bus_clk; struct clk *clk; struct reset_control *rst; void __iomem *base; @@ -367,6 +368,31 @@ static int sun4i_pwm_probe(struct platform_device *pdev) if (IS_ERR(pwm->clk)) return PTR_ERR(pwm->clk); + /* Get all clocks and reset line */ + pwm->clk = devm_clk_get_optional(&pdev->dev, "mod"); + if (IS_ERR(pwm->clk)) { + dev_err(&pdev->dev, "get clock failed %ld\n", + PTR_ERR(pwm->clk)); + return PTR_ERR(pwm->clk); + } + + /* Fallback for old dtbs with a single clock and no name */ + if (!pwm->clk) { + pwm->clk = devm_clk_get(&pdev->dev, NULL); + if (IS_ERR(pwm->clk)) { + dev_err(&pdev->dev, "get clock failed %ld\n", + PTR_ERR(pwm->clk)); + return PTR_ERR(pwm->clk); + } + } + + pwm->bus_clk = devm_clk_get_optional(&pdev->dev, "bus"); + if (IS_ERR(pwm->bus_clk)) { + dev_err(&pdev->dev, "get bus_clock failed %ld\n", + PTR_ERR(pwm->bus_clk)); + return PTR_ERR(pwm->bus_clk); + } + pwm->rst = devm_reset_control_get_optional(&pdev->dev, NULL); if (IS_ERR(pwm->rst)) { if (PTR_ERR(pwm->rst) == -EPROBE_DEFER) @@ -381,6 +407,13 @@ static int sun4i_pwm_probe(struct platform_device *pdev) return ret; } + /* Enable bus clock */ + ret = clk_prepare_enable(pwm->bus_clk); + if (ret) { + dev_err(&pdev->dev, "Cannot prepare_enable bus_clk\n"); + goto err_bus; + } + pwm->chip.dev = &pdev->dev; pwm->chip.ops = &sun4i_pwm_ops; pwm->chip.base = -1; @@ -401,6 +434,8 @@ static int sun4i_pwm_probe(struct platform_device *pdev) return 0; err_pwm_add: + clk_disable_unprepare(pwm->bus_clk); +err_bus: reset_control_assert(pwm->rst); return ret; @@ -415,6 +450,7 @@ static int sun4i_pwm_remove(struct platform_device *pdev) if (ret) return ret; + clk_disable_unprepare(pwm->bus_clk); reset_control_assert(pwm->rst); return 0; From patchwork Sun Nov 3 20:33:31 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= X-Patchwork-Id: 1188613 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="K7kfdeNH"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 475nhN4j3Rz9sPT for ; Mon, 4 Nov 2019 07:33:56 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728255AbfKCUdy (ORCPT ); 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Sun, 03 Nov 2019 12:33:48 -0800 (PST) From: =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= To: Thierry Reding , =?utf-8?q?=27Uwe_Kleine-K?= =?utf-8?b?w7ZuaWcn?= , Rob Herring , Mark Rutland , Maxime Ripard , Chen-Yu Tsai Cc: linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Jernej Skrabec , =?utf-8?b?Q2zDqW1lbnQgUMOp?= =?utf-8?q?ron?= Subject: [PATCH v2 4/7] pwm: sun4i: Add support to output source clock directly Date: Sun, 3 Nov 2019 21:33:31 +0100 Message-Id: <20191103203334.10539-5-peron.clem@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191103203334.10539-1-peron.clem@gmail.com> References: <20191103203334.10539-1-peron.clem@gmail.com> MIME-Version: 1.0 Sender: linux-pwm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org From: Jernej Skrabec PWM core has an option to bypass whole logic and output unchanged source clock as PWM output. This is achieved by enabling bypass bit. Note that when bypass is enabled, no other setting has any meaning, not even enable bit. This mode of operation is needed to achieve high enough frequency to serve as clock source for AC200 chip, which is integrated into same package as H6 SoC. Signed-off-by: Jernej Skrabec Signed-off-by: Clément Péron --- drivers/pwm/pwm-sun4i.c | 39 ++++++++++++++++++++++++++++++++++++++- 1 file changed, 38 insertions(+), 1 deletion(-) diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c index b5e7ac364f59..2441574674d9 100644 --- a/drivers/pwm/pwm-sun4i.c +++ b/drivers/pwm/pwm-sun4i.c @@ -3,6 +3,10 @@ * Driver for Allwinner sun4i Pulse Width Modulation Controller * * Copyright (C) 2014 Alexandre Belloni + * + * Limitations: + * - When outputing the source clock directly, the PWM logic will be bypassed + * and the currently running period is not guaranted to be completed */ #include @@ -73,6 +77,7 @@ static const u32 prescaler_table[] = { struct sun4i_pwm_data { bool has_prescaler_bypass; + bool has_direct_mod_clk_output; unsigned int npwm; }; @@ -118,6 +123,20 @@ static void sun4i_pwm_get_state(struct pwm_chip *chip, val = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG); + /* + * PWM chapter in H6 manual has a diagram which explains that if bypass + * bit is set, no other setting has any meaning. Even more, experiment + * proved that also enable bit is ignored in this case. + */ + if ((val & BIT_CH(PWM_BYPASS, pwm->hwpwm)) && + data->has_direct_mod_clk_output) { + state->period = DIV_ROUND_CLOSEST_ULL(NSEC_PER_SEC, clk_rate); + state->duty_cycle = state->period / 2; + state->polarity = PWM_POLARITY_NORMAL; + state->enabled = true; + return; + } + if ((PWM_REG_PRESCAL(val, pwm->hwpwm) == PWM_PRESCAL_MASK) && sun4i_pwm->data->has_prescaler_bypass) prescaler = 1; @@ -203,7 +222,8 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, { struct sun4i_pwm_chip *sun4i_pwm = to_sun4i_pwm_chip(chip); struct pwm_state cstate; - u32 ctrl; + u32 ctrl, clk_rate; + bool bypass; int ret; unsigned int delay_us; unsigned long now; @@ -218,6 +238,16 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, } } + /* + * Although it would make much more sense to check for bypass in + * sun4i_pwm_calculate(), value of bypass bit also depends on "enabled". + * Period is allowed to be rounded up or down. + */ + clk_rate = clk_get_rate(sun4i_pwm->clk); + bypass = ((state->period * clk_rate >= NSEC_PER_SEC && + state->period * clk_rate < NSEC_PER_SEC + clk_rate) && + state->enabled); + spin_lock(&sun4i_pwm->ctrl_lock); ctrl = sun4i_pwm_readl(sun4i_pwm, PWM_CTRL_REG); @@ -265,6 +295,13 @@ static int sun4i_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, ctrl &= ~BIT_CH(PWM_CLK_GATING, pwm->hwpwm); } + if (sun4i_pwm->data->has_direct_mod_clk_output) { + if (bypass) + ctrl |= BIT_CH(PWM_BYPASS, pwm->hwpwm); + else + ctrl &= ~BIT_CH(PWM_BYPASS, pwm->hwpwm); + } + sun4i_pwm_writel(sun4i_pwm, ctrl, PWM_CTRL_REG); spin_unlock(&sun4i_pwm->ctrl_lock); From patchwork Sun Nov 3 20:33:32 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= X-Patchwork-Id: 1188612 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; 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Sun, 03 Nov 2019 12:33:50 -0800 (PST) Received: from localhost.localdomain ([2a01:e0a:1f1:d0f0::4e2b:d7ca]) by smtp.gmail.com with ESMTPSA id x16sm13644026wrp.91.2019.11.03.12.33.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Nov 2019 12:33:49 -0800 (PST) From: =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= To: Thierry Reding , =?utf-8?q?=27Uwe_Kleine-K?= =?utf-8?b?w7ZuaWcn?= , Rob Herring , Mark Rutland , Maxime Ripard , Chen-Yu Tsai Cc: linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Jernej Skrabec , =?utf-8?b?Q2zDqW1lbnQgUMOp?= =?utf-8?q?ron?= Subject: [PATCH v2 5/7] pwm: sun4i: Add support for H6 PWM Date: Sun, 3 Nov 2019 21:33:32 +0100 Message-Id: <20191103203334.10539-6-peron.clem@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191103203334.10539-1-peron.clem@gmail.com> References: <20191103203334.10539-1-peron.clem@gmail.com> MIME-Version: 1.0 Sender: linux-pwm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org From: Jernej Skrabec Now that sun4i PWM driver supports deasserting reset line and enabling bus clock, support for H6 PWM can be added. Note that while H6 PWM has two channels, only first one is wired to output pin. Second channel is used as a clock source to companion AC200 chip which is bundled into same package. Signed-off-by: Jernej Skrabec Signed-off-by: Clément Péron --- drivers/pwm/pwm-sun4i.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/pwm/pwm-sun4i.c b/drivers/pwm/pwm-sun4i.c index 2441574674d9..0ccc93ce33f4 100644 --- a/drivers/pwm/pwm-sun4i.c +++ b/drivers/pwm/pwm-sun4i.c @@ -360,6 +360,12 @@ static const struct sun4i_pwm_data sun4i_pwm_single_bypass = { .npwm = 1, }; +static const struct sun4i_pwm_data sun50i_h6_pwm_data = { + .has_prescaler_bypass = true, + .has_direct_mod_clk_output = true, + .npwm = 2, +}; + static const struct of_device_id sun4i_pwm_dt_ids[] = { { .compatible = "allwinner,sun4i-a10-pwm", @@ -376,6 +382,9 @@ static const struct of_device_id sun4i_pwm_dt_ids[] = { }, { .compatible = "allwinner,sun8i-h3-pwm", .data = &sun4i_pwm_single_bypass, + }, { + .compatible = "allwinner,sun50i-h6-pwm", + .data = &sun50i_h6_pwm_data, }, { /* sentinel */ }, From patchwork Sun Nov 3 20:33:33 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= X-Patchwork-Id: 1188615 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="i/sky6bs"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 475nhh5d9Xz9sPj for ; Mon, 4 Nov 2019 07:34:12 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728244AbfKCUdy (ORCPT ); Sun, 3 Nov 2019 15:33:54 -0500 Received: from mail-wr1-f67.google.com ([209.85.221.67]:37666 "EHLO mail-wr1-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727941AbfKCUdx (ORCPT ); Sun, 3 Nov 2019 15:33:53 -0500 Received: by mail-wr1-f67.google.com with SMTP id t1so8862977wrv.4; Sun, 03 Nov 2019 12:33:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=n0fXA0HzdVYuMz+Yhj3TQjNmtcRgY2Ng0Cfj0PwkXk0=; b=i/sky6bsfSoF+v66SZuJapjuBGutQRDLdacALuPS5Wpd4itve6qDo356E0DWwjjenP XNxa4Ro0IGjjt/oLMELFfbsRrkIezE2nvUKkzc4eWUGT4vT4nFTFjjSnuPMihnkyMSST PmDy0XvN87/xfufSylj0f0yY6cfgPOP0Bze4I2s8Hj689EizoFVDxnirvSFGlJBjTuIu PR1A36HffOGv2pCZShvSGatli0jdBTlSAFkXgqDnRo+WuhUx0BazPwBRBhsvJrE2Jbey Og6OjYGsW6to5SDCttzC91MeD324z3tW42tiiQ6IPQiylpDDy0SnOl+OQM7Mvkdcqh4A HY0Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=n0fXA0HzdVYuMz+Yhj3TQjNmtcRgY2Ng0Cfj0PwkXk0=; b=hg5uLNTG2tPwMuyp//+rjZBEoKLXkfF3anG86IrlpvLGj89mXR+anST46D6SS4D3bC ewkEZc5kxp3qK1Ww65UskSA4vNtgRQ/JaJO8ei3pvF+ANnlMoYHH/999FlbgN3tANoVH +s/Z3k4YHxYv+b0bJ8Gsyo5Ut8GtZ3ZmO+yCkjCpJRTEDd00Nq0DuhdA492eKVCG2o2e uEIvtTHg9WIKeM9LG1SpT9OR+U9XRE1/KcU0rwqjAz/LkWMw+SrCeLrdtkSpkvPnfgRe +qZzpGo7YBHjtz+mPySVNYNPp+DV0Hz5n5kFHLicnPtMBjnAtsk+oqIfPPmBuiYe216W DerA== X-Gm-Message-State: APjAAAW9JOEq97bBCCUvSQYnLtc0RbAlgWdQV0f+Rc17W+BaXSpUqk3B OTLd646GVwmJywGN5+HPqzQ= X-Google-Smtp-Source: APXvYqzVgddkWTmA7e/xSuVULVWuMR+fGR0jEkIJUyfWJe0RutYNHUuUB24XHZrQsrHhHYeIj6B/fQ== X-Received: by 2002:a5d:404d:: with SMTP id w13mr21117897wrp.185.1572813230950; Sun, 03 Nov 2019 12:33:50 -0800 (PST) Received: from localhost.localdomain ([2a01:e0a:1f1:d0f0::4e2b:d7ca]) by smtp.gmail.com with ESMTPSA id x16sm13644026wrp.91.2019.11.03.12.33.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Nov 2019 12:33:50 -0800 (PST) From: =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= To: Thierry Reding , =?utf-8?q?=27Uwe_Kleine-K?= =?utf-8?b?w7ZuaWcn?= , Rob Herring , Mark Rutland , Maxime Ripard , Chen-Yu Tsai Cc: linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Jernej Skrabec , =?utf-8?b?Q2zDqW1lbnQgUMOp?= =?utf-8?q?ron?= Subject: [PATCH v2 6/7] arm64: dts: allwinner: h6: Add PWM node Date: Sun, 3 Nov 2019 21:33:33 +0100 Message-Id: <20191103203334.10539-7-peron.clem@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191103203334.10539-1-peron.clem@gmail.com> References: <20191103203334.10539-1-peron.clem@gmail.com> MIME-Version: 1.0 Sender: linux-pwm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org From: Jernej Skrabec Allwinner H6 PWM is similar to that in A20 except that it has additional bus clock and reset line. Note that first PWM channel is connected to output pin and second channel is used internally, as a clock source to AC200 co-packaged chip. This means that any combination of these two channels can be used and thus it doesn't make sense to add pinctrl nodes at this point. Signed-off-by: Jernej Skrabec Signed-off-by: Clément Péron --- arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi index 0d5ea19336a1..b0d9ee1ead13 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi @@ -222,6 +222,16 @@ status = "disabled"; }; + pwm: pwm@300a000 { + compatible = "allwinner,sun50i-h6-pwm"; + reg = <0x0300a000 0x400>; + clocks = <&osc24M>, <&ccu CLK_BUS_PWM>; + clock-names = "mod", "bus"; + resets = <&ccu RST_BUS_PWM>; + #pwm-cells = <3>; + status = "disabled"; + }; + pio: pinctrl@300b000 { compatible = "allwinner,sun50i-h6-pinctrl"; reg = <0x0300b000 0x400>; From patchwork Sun Nov 3 20:33:34 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= X-Patchwork-Id: 1188614 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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Sun, 03 Nov 2019 12:33:51 -0800 (PST) Received: from localhost.localdomain ([2a01:e0a:1f1:d0f0::4e2b:d7ca]) by smtp.gmail.com with ESMTPSA id x16sm13644026wrp.91.2019.11.03.12.33.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 03 Nov 2019 12:33:51 -0800 (PST) From: =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= To: Thierry Reding , =?utf-8?q?=27Uwe_Kleine-K?= =?utf-8?b?w7ZuaWcn?= , Rob Herring , Mark Rutland , Maxime Ripard , Chen-Yu Tsai Cc: linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, =?utf-8?b?Q2zDqW1lbnQgUMOpcm9u?= Subject: [PATCH v2 7/7] [DO NOT MERGE] arm64: allwinner: h6: enable Beelink GS1 PWM Date: Sun, 3 Nov 2019 21:33:34 +0100 Message-Id: <20191103203334.10539-8-peron.clem@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191103203334.10539-1-peron.clem@gmail.com> References: <20191103203334.10539-1-peron.clem@gmail.com> MIME-Version: 1.0 Sender: linux-pwm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org Signed-off-by: Clément Péron --- arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts index 1d05d570142f..38aba7e5bbd9 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts +++ b/arch/arm64/boot/dts/allwinner/sun50i-h6-beelink-gs1.dts @@ -131,6 +131,10 @@ vcc-pg-supply = <®_aldo1>; }; +&pwm { + status = "okay"; +}; + &r_i2c { status = "okay";