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Thu, 31 Oct 2019 23:06:05 -0700 Received: from xsj-pvapsmtp01 (xsj-smtp1.xilinx.com [149.199.38.66]) by xsj-smtp-dlp1.xlnx.xilinx.com (8.13.8/8.13.1) with ESMTP id xA165w0t010449; Thu, 31 Oct 2019 23:05:58 -0700 Received: from [172.23.64.106] (helo=xhdvnc125.xilinx.com) by xsj-pvapsmtp01 with esmtp (Exim 4.63) (envelope-from ) id 1iQQ4L-0007Zx-Nr; Thu, 31 Oct 2019 23:05:58 -0700 Received: by xhdvnc125.xilinx.com (Postfix, from userid 16987) id F1175121385; Fri, 1 Nov 2019 11:35:56 +0530 (IST) From: Manish Narani To: ulf.hansson@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com, adrian.hunter@intel.com, michal.simek@xilinx.com, jolly.shah@xilinx.com, nava.manne@xilinx.com, rajan.vaja@xilinx.com, manish.narani@xilinx.com Cc: linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, git@xilinx.com Subject: [PATCH v5 4/8] dt-bindings: mmc: Add optional generic properties for mmc Date: Fri, 1 Nov 2019 11:35:49 +0530 Message-Id: <1572588353-110682-5-git-send-email-manish.narani@xilinx.com> X-Mailer: git-send-email 2.1.1 In-Reply-To: <1572588353-110682-1-git-send-email-manish.narani@xilinx.com> References: <1572588353-110682-1-git-send-email-manish.narani@xilinx.com> X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.2.0.1013-23620.005 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:149.199.60.83; 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X-Microsoft-Antispam-Message-Info: Xrv/KS/zB81+SQjgET0Epr1lkvKD8nX6b5nl+k+lx0JIw+vndDF3WLlfXczqWycNCeaabbK6es6lHER+nmbY85whTzdAkUkcQar8BvamL8yVnJXuhJpPs2nBUJeNIbMKCp8MlsqJqUv4yHflXh6mlO/E0ixgwpRUgYLN/gj9HG9nDFs/Ng17DVYqtDYFUlWtX3Z3DmPPUr7oTlOSyNdbJWg+yAmV23FgaT/JvrnLcjRt7VN0G8KoI+PAsnZppREqSg4OjrRkiPCkseW3VxoGHlj3tYPtExL8ru4S7Tp+xrBRLyvEGV744YP0h+WWz5oZNWbHx6Cg2V95TpoVgcHGU7Ua6klQDDRjPzUL4wcdZQLgLrGvysTlmZWO4yqIS5UO4Mkpg1k3zn4BzyUOl9KX/1cdXkXnwrGF7dyZX1uy5zgdmz73TrpiT5wQJQ3+rMO9 X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Nov 2019 06:06:10.8597 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: dff954f7-f8e9-49d0-cd79-08d75e91980c X-MS-Exchange-CrossTenant-Id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=657af505-d5df-48d0-8300-c31994686c5c; Ip=[149.199.60.83]; Helo=[xsj-pvapsmtpgw01] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SN1PR02MB3807 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add optional properties for mmc hosts which are used to set clk delays for different speed modes in the controller. Signed-off-by: Manish Narani --- .../bindings/mmc/mmc-controller.yaml | 92 +++++++++++++++++++ 1 file changed, 92 insertions(+) diff --git a/Documentation/devicetree/bindings/mmc/mmc-controller.yaml b/Documentation/devicetree/bindings/mmc/mmc-controller.yaml index 080754e0ef35..87a83d966851 100644 --- a/Documentation/devicetree/bindings/mmc/mmc-controller.yaml +++ b/Documentation/devicetree/bindings/mmc/mmc-controller.yaml @@ -212,6 +212,98 @@ properties: description: eMMC HS400 enhanced strobe mode is supported + # Below mentioned are the clock (phase) delays which are to be configured + # in the controller while switching to particular speed mode. The range + # of values are 0 to 359 degrees. + + clk-phase-legacy: + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - minimum: 0 + - maximum: 359 + description: + Input/Output Clock Delay pair in degrees for Legacy Mode. + + clk-phase-mmc-hs: + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - minimum: 0 + - maximum: 359 + description: + Input/Output Clock Delay pair degrees for MMC HS. + + clk-phase-sd-hs: + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - minimum: 0 + - maximum: 359 + description: + Input/Output Clock Delay pair in degrees for SD HS. + + clk-phase-uhs-sdr12: + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - minimum: 0 + - maximum: 359 + description: + Input/Output Clock Delay pair in degrees for SDR12. + + clk-phase-uhs-sdr25: + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - minimum: 0 + - maximum: 359 + description: + Input/Output Clock Delay pair in degrees for SDR25. + + clk-phase-uhs-sdr50: + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - minimum: 0 + - maximum: 359 + description: + Input/Output Clock Delay pair in degrees for SDR50. + + clk-phase-uhs-sdr104: + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - minimum: 0 + - maximum: 359 + description: + Input/Output Clock Delay pair in degrees for SDR104. + + clk-phase-uhs-ddr50: + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - minimum: 0 + - maximum: 359 + description: + Input/Output Clock Delay pair in degrees for SD DDR50. + + clk-phase-mmc-ddr52: + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - minimum: 0 + - maximum: 359 + description: + Input/Output Clock Delay pair in degrees for MMC DDR52. + + clk-phase-mmc-hs200: + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - minimum: 0 + - maximum: 359 + description: + Input/Output Clock Delay pair in degrees for MMC HS200. + + clk-phase-mmc-hs400: + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - minimum: 0 + - maximum: 359 + description: + Input/Output Clock Delay pair in degrees for MMC HS400. + dsr: allOf: - $ref: /schemas/types.yaml#/definitions/uint32 From patchwork Fri Nov 1 06:05:52 2019 Content-Type: text/plain; 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Thu, 31 Oct 2019 23:06:03 -0700 Received: from xsj-pvapsmtp01 (smtp3.xilinx.com [149.199.38.66]) by xsj-smtp-dlp1.xlnx.xilinx.com (8.13.8/8.13.1) with ESMTP id xA165xts010455; Thu, 31 Oct 2019 23:05:59 -0700 Received: from [172.23.64.106] (helo=xhdvnc125.xilinx.com) by xsj-pvapsmtp01 with esmtp (Exim 4.63) (envelope-from ) id 1iQQ4M-0007aN-Pn; Thu, 31 Oct 2019 23:05:59 -0700 Received: by xhdvnc125.xilinx.com (Postfix, from userid 16987) id 0DC00121388; Fri, 1 Nov 2019 11:35:57 +0530 (IST) From: Manish Narani To: ulf.hansson@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com, adrian.hunter@intel.com, michal.simek@xilinx.com, jolly.shah@xilinx.com, nava.manne@xilinx.com, rajan.vaja@xilinx.com, manish.narani@xilinx.com Cc: linux-mmc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, git@xilinx.com Subject: [PATCH v5 7/8] dt-bindings: mmc: arasan: Document 'xlnx, zynqmp-8.9a' controller Date: Fri, 1 Nov 2019 11:35:52 +0530 Message-Id: <1572588353-110682-8-git-send-email-manish.narani@xilinx.com> X-Mailer: git-send-email 2.1.1 In-Reply-To: <1572588353-110682-1-git-send-email-manish.narani@xilinx.com> References: <1572588353-110682-1-git-send-email-manish.narani@xilinx.com> X-RCIS-Action: ALLOW X-TM-AS-Product-Ver: IMSS-7.1.0.1224-8.2.0.1013-23620.005 X-TM-AS-User-Approved-Sender: Yes;Yes X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:149.199.60.83; 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Signed-off-by: Manish Narani Reviewed-by: Rob Herring --- .../devicetree/bindings/mmc/arasan,sdhci.txt | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt index b51e40b2e0c5..6f28e9d612d9 100644 --- a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt +++ b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt @@ -15,6 +15,9 @@ Required Properties: - "arasan,sdhci-5.1": generic Arasan SDHCI 5.1 PHY - "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1": rk3399 eMMC PHY For this device it is strongly suggested to include arasan,soc-ctl-syscon. + - "xlnx,zynqmp-8.9a": ZynqMP SDHCI 8.9a PHY + For this device it is strongly suggested to include clock-output-names and + #clock-cells. - "ti,am654-sdhci-5.1", "arasan,sdhci-5.1": TI AM654 MMC PHY Note: This binding has been deprecated and moved to [5]. - "intel,lgm-sdhci-5.1-emmc", "arasan,sdhci-5.1": Intel LGM eMMC PHY @@ -47,6 +50,10 @@ Optional Properties: - xlnx,int-clock-stable-broken: when present, the controller always reports that the internal clock is stable even when it is not. + - xlnx,mio-bank: When specified, this will indicate the MIO bank number in + which the command and data lines are configured. If not specified, driver + will assume this as 0. + Example: sdhci@e0100000 { compatible = "arasan,sdhci-8.9a"; @@ -83,6 +90,18 @@ Example: #clock-cells = <0>; }; + sdhci: mmc@ff160000 { + compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a"; + interrupt-parent = <&gic>; + interrupts = <0 48 4>; + reg = <0x0 0xff160000 0x0 0x1000>; + clocks = <&clk200>, <&clk200>; + clock-names = "clk_xin", "clk_ahb"; + clock-output-names = "clk_out_sd0", "clk_in_sd0"; + #clock-cells = <1>; + arasan-clk-phase-sd-hs = <63>, <72>; + }; + emmc: sdhci@ec700000 { compatible = "intel,lgm-sdhci-5.1-emmc", "arasan,sdhci-5.1"; reg = <0xec700000 0x300>;