From patchwork Wed Oct 30 10:25:41 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lokesh Vutla X-Patchwork-Id: 1186637 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=quarantine dis=none) header.from=ti.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=ti.com header.i=@ti.com header.b="gx/Fioa6"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 4734Pv3HYjz9sPJ for ; Wed, 30 Oct 2019 21:26:57 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 8F130C21DFB; Wed, 30 Oct 2019 10:26:52 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 511E4C21C51; Wed, 30 Oct 2019 10:26:51 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 85D2DC21C51; Wed, 30 Oct 2019 10:26:50 +0000 (UTC) Received: from lelv0143.ext.ti.com (lelv0143.ext.ti.com [198.47.23.248]) by lists.denx.de (Postfix) with ESMTPS id 151F5C21BE5 for ; Wed, 30 Oct 2019 10:26:49 +0000 (UTC) Received: from lelv0266.itg.ti.com ([10.180.67.225]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id x9UAQlOC046168; Wed, 30 Oct 2019 05:26:47 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1572431207; bh=u5dX6pDDpFuCKPJIRc5rVLY0BvDHdYD9mV9g/PhbDj8=; h=From:To:CC:Subject:Date; b=gx/Fioa6nb4n0hnGZy0pRaJOiXtTPEigaMSZ3EvSAe+maTxjWtPCy/Hya8DNtlI6B bIBopylgutG6RCrdlPVWWk0jzqVi4HzfXLPC/UcB8gvZ9pKyBF+cfi6rZhi9BBtSRa O2cqH8btKlT1vJvYeRwjDBNCwghfU5iBCJZ1EWrM= Received: from DLEE109.ent.ti.com (dlee109.ent.ti.com [157.170.170.41]) by lelv0266.itg.ti.com (8.15.2/8.15.2) with ESMTPS id x9UAQlF3112184 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 30 Oct 2019 05:26:47 -0500 Received: from DLEE110.ent.ti.com (157.170.170.21) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5; Wed, 30 Oct 2019 05:26:34 -0500 Received: from fllv0039.itg.ti.com (10.64.41.19) by DLEE110.ent.ti.com (157.170.170.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1713.5 via Frontend Transport; Wed, 30 Oct 2019 05:26:47 -0500 Received: from uda0131933.india.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by fllv0039.itg.ti.com (8.15.2/8.15.2) with ESMTP id x9UAQjg4111240; Wed, 30 Oct 2019 05:26:45 -0500 From: Lokesh Vutla To: Tom Rini , Date: Wed, 30 Oct 2019 15:55:41 +0530 Message-ID: <20191030102541.16222-1-lokeshvutla@ti.com> X-Mailer: git-send-email 2.23.0 MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Cc: Tero Kristo Subject: [U-Boot] [PATCH] arm: caches: Disable mmu only if mmu is available X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" As part of disabling caches MMU as well gets disabled. But MMU is not available on all armv7 cores like R5F. So disable MMU only if it is available. Signed-off-by: Lokesh Vutla --- arch/arm/lib/cache-cp15.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c index b2913e8165..47c223917a 100644 --- a/arch/arm/lib/cache-cp15.c +++ b/arch/arm/lib/cache-cp15.c @@ -235,12 +235,18 @@ static void cache_disable(uint32_t cache_bit) /* if cache isn;t enabled no need to disable */ if ((reg & CR_C) != CR_C) return; +#ifdef CONFIG_SYS_ARM_MMU /* if disabling data cache, disable mmu too */ cache_bit |= CR_M; +#endif } reg = get_cr(); +#ifdef CONFIG_SYS_ARM_MMU if (cache_bit == (CR_C | CR_M)) +#elif defined(CONFIG_SYS_ARM_MPU) + if (cache_bit == CR_C) +#endif flush_dcache_all(); set_cr(reg & ~cache_bit); }