From patchwork Wed Oct 30 06:32:19 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joel Stanley X-Patchwork-Id: 1186515 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 472zDN1RqLz9sPj for ; Wed, 30 Oct 2019 17:33:24 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=jms.id.au Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="bdQ2ZHu6"; dkim-atps=neutral Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 472zDM5439zF3ky for ; Wed, 30 Oct 2019 17:33:23 +1100 (AEDT) X-Original-To: openbmc@lists.ozlabs.org Delivered-To: openbmc@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gmail.com (client-ip=2607:f8b0:4864:20::434; helo=mail-pf1-x434.google.com; envelope-from=joel.stan@gmail.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=jms.id.au Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="bdQ2ZHu6"; dkim-atps=neutral Received: from mail-pf1-x434.google.com (mail-pf1-x434.google.com [IPv6:2607:f8b0:4864:20::434]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 472zCW4l3LzF3V9 for ; Wed, 30 Oct 2019 17:32:38 +1100 (AEDT) Received: by mail-pf1-x434.google.com with SMTP id b25so829794pfi.13 for ; Tue, 29 Oct 2019 23:32:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=dLRxYrd8OZQn6msCJJYhGXbEGnyruPOi30WNbEHoPp0=; b=bdQ2ZHu6mwC7dxbr+u3WsTCInhk9y3iZ/5+1rwrC1gtcfXD9zHZHey+kRCIdDtCzar mX/q7NXWGKpm/O51hYFSmnugCVOL/tIeyrwiXzKwwUeOXKxAYZO6zDGNTuvB7qPN2UKE 2pBw+uQJdMh9KWnzAbgByO+AJpxSVO8IqeNP/g1EHMObBjBRTGUhygfg8Oxk/m5RQbdY QLlkhFw1bZVMaOj6Mg3dBHvlDEL79Ys9VeHmko41TSfEf9+kpJkZlDbVu3elF87GsH7L e9Wu9tUJGNyWlBgxik4E3Yb5ID4MH6vOaq2jgICpSEwE2kwZA9gH4Uu4E7u3G3w6TYEa UhUA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=dLRxYrd8OZQn6msCJJYhGXbEGnyruPOi30WNbEHoPp0=; b=Q6JNPDxHR7iF8TNmiOAsYx7iNUTjKfGsDNkVdcNqeWSbz5YSKFXGIP37Cu11EoX1zF 6cZsNPOTo0M/eG8w/PRlwLrBMp8NtRSGoutqvDVY6gYk7BUaTX0iAz7wF51fi0LqDY6v nsAJidlzmB1c7gBjoqHbU0XYILPECNMFckDgCJDDRHvuz91kFZ3j4wVI4pus2tnet/Ef Rsbl7ZgfG2uD24BCyXYrC1UqBgfwqS1bizQS2nvMgQyMZtvYdMe0zCDwXS7LYhc7HbrZ McC3VSoRmZ+vbsEhxCGns4TvRNGUYd3e8h2k0qxHD4sYxipaYfI0oFdJ5wMi1dXu6N5k 4YYA== X-Gm-Message-State: APjAAAWnUlMTcUZ9jFZUj8s2LzeC9lmOZPMyvHEdhz8lvyDBBmf1qhuX n6NW1uOgChRWrhA+kuz0sds= X-Google-Smtp-Source: APXvYqwT4iAwzvca94AOtDdmK8hOfekAi3D8tieLXmDMlfRsDTaZWTC754ihCy8vAj6Hj1ZAAu6xYA== X-Received: by 2002:a17:90a:7f06:: with SMTP id k6mr11761099pjl.10.1572417156179; Tue, 29 Oct 2019 23:32:36 -0700 (PDT) Received: from voyager.ibm.com ([36.255.48.244]) by smtp.gmail.com with ESMTPSA id i102sm1028018pje.17.2019.10.29.23.32.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Oct 2019 23:32:35 -0700 (PDT) From: Joel Stanley To: Ryan Chen , Jeremy Kerr , Andrew Jeffery Subject: [PATCH u-boot aspeed-dev-v2019.04 1/7] dt-bindings: Add FSI clock Date: Wed, 30 Oct 2019 17:02:19 +1030 Message-Id: <20191030063225.11319-2-joel@jms.id.au> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191030063225.11319-1-joel@jms.id.au> References: <20191030063225.11319-1-joel@jms.id.au> MIME-Version: 1.0 X-BeenThere: openbmc@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development list for OpenBMC List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: openbmc@lists.ozlabs.org Errors-To: openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "openbmc" Signed-off-by: Joel Stanley --- include/dt-bindings/clock/ast2600-clock.h | 39 ++++++++++++----------- 1 file changed, 20 insertions(+), 19 deletions(-) diff --git a/include/dt-bindings/clock/ast2600-clock.h b/include/dt-bindings/clock/ast2600-clock.h index 4956fa196d39..7e07cbda37c4 100644 --- a/include/dt-bindings/clock/ast2600-clock.h +++ b/include/dt-bindings/clock/ast2600-clock.h @@ -41,23 +41,24 @@ #define ASPEED_CLK_GATE_USBUHCICLK 33 #define ASPEED_CLK_GATE_USBPORT1CLK 34 #define ASPEED_CLK_GATE_USBPORT2CLK 35 +#define ASPEED_CLK_GATE_FSICLK 36 -#define ASPEED_CLK_APLL 36 -#define ASPEED_CLK_EPLL 37 -#define ASPEED_CLK_DPLL 38 -#define ASPEED_CLK_HPLL 39 -#define ASPEED_CLK_AHB 40 -#define ASPEED_CLK_APB1 41 -#define ASPEED_CLK_APB2 42 -#define ASPEED_CLK_UART 43 -#define ASPEED_CLK_SDIO 44 -#define ASPEED_CLK_ECLK 45 -#define ASPEED_CLK_ECLK_MUX 46 -#define ASPEED_CLK_LHCLK 47 -#define ASPEED_CLK_MAC 48 -#define ASPEED_CLK_BCLK 49 -#define ASPEED_CLK_MPLL 50 -#define ASPEED_CLK_24M 51 -#define ASPEED_CLK_EMMC 52 -#define ASPEED_CLK_UARTX 53 -#define ASPEED_CLK_UARTUX 54 +#define ASPEED_CLK_APLL 37 +#define ASPEED_CLK_EPLL 38 +#define ASPEED_CLK_DPLL 39 +#define ASPEED_CLK_HPLL 40 +#define ASPEED_CLK_AHB 41 +#define ASPEED_CLK_APB1 42 +#define ASPEED_CLK_APB2 43 +#define ASPEED_CLK_UART 44 +#define ASPEED_CLK_SDIO 45 +#define ASPEED_CLK_ECLK 46 +#define ASPEED_CLK_ECLK_MUX 47 +#define ASPEED_CLK_LHCLK 48 +#define ASPEED_CLK_MAC 49 +#define ASPEED_CLK_BCLK 50 +#define ASPEED_CLK_MPLL 51 +#define ASPEED_CLK_24M 52 +#define ASPEED_CLK_EMMC 53 +#define ASPEED_CLK_UARTX 54 +#define ASPEED_CLK_UARTUX 55 From patchwork Wed Oct 30 06:32:20 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joel Stanley X-Patchwork-Id: 1186517 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 472zGj4vzlz9sPK for ; Wed, 30 Oct 2019 17:35:25 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=jms.id.au Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="BWJzLIAE"; dkim-atps=neutral Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 472zGj3lbRzF3WX for ; Wed, 30 Oct 2019 17:35:25 +1100 (AEDT) X-Original-To: openbmc@lists.ozlabs.org Delivered-To: openbmc@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gmail.com (client-ip=2607:f8b0:4864:20::42a; helo=mail-pf1-x42a.google.com; envelope-from=joel.stan@gmail.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=jms.id.au Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="BWJzLIAE"; dkim-atps=neutral Received: from mail-pf1-x42a.google.com (mail-pf1-x42a.google.com [IPv6:2607:f8b0:4864:20::42a]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 472zCY4Xp0zF3V3 for ; Wed, 30 Oct 2019 17:32:41 +1100 (AEDT) Received: by mail-pf1-x42a.google.com with SMTP id v19so864859pfm.3 for ; Tue, 29 Oct 2019 23:32:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=oM9LovEotlbaLpWTQ4s+j1JIcDwISrWXIit1SinGRm4=; b=BWJzLIAEVHBHI1uHgXcnMcaqhZmHoA1KKPX9PnWWsxzcsgwq1u+awG0DxkxxdSq28r uLQhXQVvcVPvYUiPIesrRS4h4yzjKn9RjIOfffQPmpH/IvnGleaOHZbV/PhK3vSxPW0E 4U1XK7L6MdJbiu3cPn/jrUBlSGRTP//vXODzKY41jtK9/57qNGQc8n0JgBYcPq5rj1fj 0dgS14VcwhIdkmE40wrfedHeB6E5vfKqVxeGnD8jnh5fdRgrpDPQoBQSrgNBHg9mHRlH dX29Q7ZLbeKvtxGs7PJSXEp94DZcwh4siz3vhUhRPuxhMdaKzokDYtUcfOnc/uTDeOzx uJAw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=oM9LovEotlbaLpWTQ4s+j1JIcDwISrWXIit1SinGRm4=; b=Fn2rCoG6/X7j9U12Y/duqdwEK2FA9rj7MRWcrRKIgnwxB/V2pkG4yyxmucxzric447 lz9tPd3zwZidb8cPCvStUR15uIaWB8yyldvMW72auhjU6xh3APxuVduXQzKFsWwLfpF+ AM243E4ZxoEhsGbT3PwjNFmm31sjfbStIt3wscaITnhz+EY+KDC3KM+Ma52XAuuBpcXY AwzJdFa3KXBtSHNd/RlW2Ucpl/9uX8vJ+wMKb/FfwGXXDS3mO8pO2PAkRkVSMgC76jtr AlHATMt82HOBtMTiZhbeOYcNfza2deD8qaSXZeiXrXZukq+bMLE0xlyT1X80TgHO1rGH VDGw== X-Gm-Message-State: APjAAAVzEXddRecEw2Y6hRsB4Z/8t6vK8fKgv0mEFOZ33PkKRDHSRwPo Y1Z5jNVd8nOJEp2ImUAwBz0= X-Google-Smtp-Source: APXvYqw7CttFm/11TVSYdUggGyTf8S6lcwJtF5jdw3nZBfh52vnxypv8/9aSdfhgSp+sAW9vNX+pSQ== X-Received: by 2002:a17:90a:f991:: with SMTP id cq17mr11993163pjb.30.1572417158848; Tue, 29 Oct 2019 23:32:38 -0700 (PDT) Received: from voyager.ibm.com ([36.255.48.244]) by smtp.gmail.com with ESMTPSA id i102sm1028018pje.17.2019.10.29.23.32.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Oct 2019 23:32:38 -0700 (PDT) From: Joel Stanley To: Ryan Chen , Jeremy Kerr , Andrew Jeffery Subject: [PATCH u-boot aspeed-dev-v2019.04 2/7] dts: ast2600: Add FSI description Date: Wed, 30 Oct 2019 17:02:20 +1030 Message-Id: <20191030063225.11319-3-joel@jms.id.au> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191030063225.11319-1-joel@jms.id.au> References: <20191030063225.11319-1-joel@jms.id.au> MIME-Version: 1.0 X-BeenThere: openbmc@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development list for OpenBMC List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: openbmc@lists.ozlabs.org Errors-To: openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "openbmc" Signed-off-by: Joel Stanley --- arch/arm/dts/ast2600.dtsi | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/arch/arm/dts/ast2600.dtsi b/arch/arm/dts/ast2600.dtsi index 070ff87ce619..ab71fcd2d543 100644 --- a/arch/arm/dts/ast2600.dtsi +++ b/arch/arm/dts/ast2600.dtsi @@ -600,6 +600,27 @@ ranges = <0 0x1e78a000 0x1000>; }; + fsim0: fsi@1e79b000 { + compatible = "aspeed,ast2600-fsi-master", "fsi-master"; + reg = <0x1e79b000 0x94>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fsi1_default>; + clocks = <&scu ASPEED_CLK_GATE_FSICLK>; + status = "disabled"; + }; + + fsim1: fsi@1e79b100 { + compatible = "aspeed,ast2600-fsi-master", "fsi-master"; + reg = <0x1e79b100 0x94>; + interrupts = ; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fsi2_default>; + clocks = <&scu ASPEED_CLK_GATE_FSICLK>; + status = "disabled"; + }; + + uart6: serial@1e790000 { compatible = "ns16550a"; reg = <0x1e790000 0x20>; @@ -1065,6 +1086,16 @@ groups = "ESPI"; }; + pinctrl_fsi1_default: fsi1_default { + function = "FSI1"; + groups = "FSI1"; + }; + + pinctrl_fsi2_default: fsi2_default { + function = "FSI2"; + groups = "FSI2"; + }; + pinctrl_fwspics1_default: fwspics1_default { function = "FWSPICS1"; groups = "FWSPICS1"; From patchwork Wed Oct 30 06:32:21 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joel Stanley X-Patchwork-Id: 1186519 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 472zJ428WVz9sPK for ; Wed, 30 Oct 2019 17:36:36 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=jms.id.au Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="ARsAdfvG"; dkim-atps=neutral Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 472zJ367tCzF1Xx for ; Wed, 30 Oct 2019 17:36:35 +1100 (AEDT) X-Original-To: openbmc@lists.ozlabs.org Delivered-To: openbmc@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gmail.com (client-ip=2607:f8b0:4864:20::543; helo=mail-pg1-x543.google.com; envelope-from=joel.stan@gmail.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=jms.id.au Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="ARsAdfvG"; dkim-atps=neutral Received: from mail-pg1-x543.google.com (mail-pg1-x543.google.com [IPv6:2607:f8b0:4864:20::543]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 472zCc1dbLzF3V3 for ; Wed, 30 Oct 2019 17:32:44 +1100 (AEDT) Received: by mail-pg1-x543.google.com with SMTP id w3so779667pgt.5 for ; Tue, 29 Oct 2019 23:32:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=sTzQSV/7sRPq35TdzhWjtH6nxsSmk5rc/lmVue61QIA=; b=ARsAdfvGwNBFfF/2LyHY8sP4YvLXrxqf+LCufHJopeZevUT9XnDwujtLg2ZHuBqdWy PETt3s1+1qVXJMtcv0cQgJ5e99Wor9Fa7+mE+G5Qtu2QVl4R3vxKTQXEqtXpunGCprwR NldRxTV4btMPDpBNIfjtTn0fzRz5S/MTvUGKhKnCJlChtSEzDn0KsXt8yarLWeIOYSCd yT1psK02SwDvA1Nt5bYTzn4D1eOJWhXY5107dbdMjmzwKACPuI169xVvpDrA1ppGR65W 0ocVHNRiHEixw0uJDOMYbDII4LmEFrnq92xjyGtwIF0+xlpjAy0pe83Hu7oLWj7UIYJ1 Eplw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=sTzQSV/7sRPq35TdzhWjtH6nxsSmk5rc/lmVue61QIA=; b=GUiTTfiKXA6dWqy7OFSp8z0b/qwSS5WpCQLsWrHG23hxaFxLYu8gz4HMegYydSIBvI b94NCUls7Gv6NbzYe2lfMkiKF3zBUI+td+IMyDyCw50stbtCMwF0AWWOWAfFkhMe/XNA nCX8ZmUvCn4osa0SvM9UFRGtCj/FcISLF6J5DNIuUvkeSrvbBnGPHBUDb3rCBIG9urWR 0+JmcZpfVjB+QlC0Mp1ME1+TmBTgkoty34cQjZe3PcEdi+y6LGzXhncIBnmOtQAfwaxd BpLhfUBTddc9YY9scE/8+4MaCt+BaMiRTAEkug0GuJYFhndJFHskhSkJpZf+LGKrpxqw lhQA== X-Gm-Message-State: APjAAAXTCeZzISX43Nxyy2Mgr5wjwCTNkY2rX8xbarmfQpObtNlH6AB8 +7A9ujr/R0QcgOYs/EimBh0= X-Google-Smtp-Source: APXvYqzpVnzwwPELJxPgXeJHCjxXfiTZgcb/v0tNab1Ci0ibrDgrY5LFm93Fm/MFdUIFdthUfFakLA== X-Received: by 2002:a63:5752:: with SMTP id h18mr15163154pgm.312.1572417161581; Tue, 29 Oct 2019 23:32:41 -0700 (PDT) Received: from voyager.ibm.com ([36.255.48.244]) by smtp.gmail.com with ESMTPSA id i102sm1028018pje.17.2019.10.29.23.32.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Oct 2019 23:32:41 -0700 (PDT) From: Joel Stanley To: Ryan Chen , Jeremy Kerr , Andrew Jeffery Subject: [PATCH u-boot aspeed-dev-v2019.04 3/7] aspeed: pinctrl: Add FSI support Date: Wed, 30 Oct 2019 17:02:21 +1030 Message-Id: <20191030063225.11319-4-joel@jms.id.au> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191030063225.11319-1-joel@jms.id.au> References: <20191030063225.11319-1-joel@jms.id.au> MIME-Version: 1.0 X-BeenThere: openbmc@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development list for OpenBMC List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: openbmc@lists.ozlabs.org Errors-To: openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "openbmc" Signed-off-by: Joel Stanley --- drivers/pinctrl/aspeed/pinctrl_ast2600.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/pinctrl/aspeed/pinctrl_ast2600.c b/drivers/pinctrl/aspeed/pinctrl_ast2600.c index b22f280e6979..e87b33687f51 100644 --- a/drivers/pinctrl/aspeed/pinctrl_ast2600.c +++ b/drivers/pinctrl/aspeed/pinctrl_ast2600.c @@ -242,6 +242,14 @@ static struct aspeed_sig_desc pcie_rc_reset_link[] = { { 0x500, BIT(24), 0 }, }; +static struct aspeed_sig_desc fsi1[] = { + { 0xd48, GENMASK(21, 20), 0 }, +}; + +static struct aspeed_sig_desc fsi2[] = { + { 0xd48, GENMASK(23, 22), 0 }, +}; + static const struct aspeed_group_config ast2600_groups[] = { { "MAC1LINK", ARRAY_SIZE(mac1_link), mac1_link }, { "MAC2LINK", ARRAY_SIZE(mac2_link), mac2_link }, @@ -282,6 +290,8 @@ static const struct aspeed_group_config ast2600_groups[] = { { "I2C15", ARRAY_SIZE(i2c15_link), i2c15_link }, { "I2C16", ARRAY_SIZE(i2c16_link), i2c16_link }, { "PCIERC", ARRAY_SIZE(pcie_rc_reset_link), pcie_rc_reset_link }, + { "FSI1", ARRAY_SIZE(fsi1), fsi1 }, + { "FSI2", ARRAY_SIZE(fsi2), fsi2 }, }; static int ast2600_pinctrl_get_groups_count(struct udevice *dev) From patchwork Wed Oct 30 06:32:22 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joel Stanley X-Patchwork-Id: 1186521 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 472zKx5FX1z9sPK for ; Wed, 30 Oct 2019 17:38:13 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=jms.id.au Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="klQ1wjf6"; dkim-atps=neutral Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 472zKx2glyzF3Xn for ; Wed, 30 Oct 2019 17:38:13 +1100 (AEDT) X-Original-To: openbmc@lists.ozlabs.org Delivered-To: openbmc@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gmail.com (client-ip=2607:f8b0:4864:20::643; helo=mail-pl1-x643.google.com; envelope-from=joel.stan@gmail.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=jms.id.au Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="klQ1wjf6"; dkim-atps=neutral Received: from mail-pl1-x643.google.com (mail-pl1-x643.google.com [IPv6:2607:f8b0:4864:20::643]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 472zCg09cgzF3dq for ; Wed, 30 Oct 2019 17:32:46 +1100 (AEDT) Received: by mail-pl1-x643.google.com with SMTP id t12so513222plo.6 for ; Tue, 29 Oct 2019 23:32:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=3Of0auCazJ9loN/dAPyYAyI5a13e9D0x8sOsXEd0Rsg=; b=klQ1wjf6oJE3JT8fKXrBtzrHXXG5TtWQBoJtBuGZU9g2W8VDbrI04Vfka8nHqXilA0 FGP3DrBnSa0Q4MI0A1u7irzElYt+MSrcFE2O4HLq0AEGypPLg1ebviF49PNs9Eo+o7mJ ICZWhRxrVkmbcluf6FVYtYgVtvfKL9rnT1N4dshmXPXrqpD8a7ACIMZKVXxDZZBqs0ZV NDzwtz4oJ8e7siPcoMyuQTU2HPjGJcssg35aGwy04msBhdtolIFDztvupqQCG8kzuBQK Wb/4rQNyuPl/sP5zAY3ePo7tfTEKymSm5lTIFUvFS1j/+8koEHSXgZ7g4BsLf8F9dYRI j0Og== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=3Of0auCazJ9loN/dAPyYAyI5a13e9D0x8sOsXEd0Rsg=; b=ZNvehyANC+UAuPVxyzI1wKm1K4JrNEdrCybQLsiO1qQQJy4gAZUBoK70v27K+yHN1b RMohmRzARzspbbF77gVt2Y0dUl6wiptMNqWUUUcZvwM3fNOsvzlV22m2uFgyUznP0rep aBt794J5AjZ45H/qOshEbAUh50nAYJBzWdMNwqT21S0l/dNKWcAa5tswMzxf7NHbE7TZ NAcMPYIuDlP1VglLkw2hcq6oFb8MnjXsE2dDVR1l2bxsULWPVkC8ByDasGQWs1bFt1uV ZyGMQ3Yb2bYezRrp/0zE+qKp1O/Cs31wX1Tym9exbeZrsHOw187OPxrb7MBL3Jc3+KiE nzmQ== X-Gm-Message-State: APjAAAVFgScXaqwoArkJEO1iifXnOo2bNZ4L82w4jwIBNjvPs0PHRUvE 2J5COcW0Vou7S4Fmya0eCfU= X-Google-Smtp-Source: APXvYqxEoWeb9TvR0UUX3s1T7tW9Lennr9cK7x4gfP88ClS+cHZ/wk2HRKlIc1PLtVwP7V22DEOm+A== X-Received: by 2002:a17:902:aa43:: with SMTP id c3mr2914979plr.145.1572417164298; Tue, 29 Oct 2019 23:32:44 -0700 (PDT) Received: from voyager.ibm.com ([36.255.48.244]) by smtp.gmail.com with ESMTPSA id i102sm1028018pje.17.2019.10.29.23.32.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Oct 2019 23:32:43 -0700 (PDT) From: Joel Stanley To: Ryan Chen , Jeremy Kerr , Andrew Jeffery Subject: [PATCH u-boot aspeed-dev-v2019.04 4/7] aspeed: clock: Add FSI clock Date: Wed, 30 Oct 2019 17:02:22 +1030 Message-Id: <20191030063225.11319-5-joel@jms.id.au> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191030063225.11319-1-joel@jms.id.au> References: <20191030063225.11319-1-joel@jms.id.au> MIME-Version: 1.0 X-BeenThere: openbmc@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development list for OpenBMC List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: openbmc@lists.ozlabs.org Errors-To: openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "openbmc" Signed-off-by: Joel Stanley --- drivers/clk/aspeed/clk_ast2600.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/drivers/clk/aspeed/clk_ast2600.c b/drivers/clk/aspeed/clk_ast2600.c index fab605a1428e..480f15e8dba8 100644 --- a/drivers/clk/aspeed/clk_ast2600.c +++ b/drivers/clk/aspeed/clk_ast2600.c @@ -969,6 +969,26 @@ static ulong ast2600_enable_extemmcclk(struct ast2600_scu *scu) return 0; } +#define SCU_CLKSTOP_FSICLK 30 + +static ulong ast2600_enable_fsiclk(struct ast2600_scu *scu) +{ + u32 reset_bit; + u32 clkstop_bit; + + reset_bit = BIT(ASPEED_RESET_FSI % 32); + clkstop_bit = BIT(SCU_CLKSTOP_FSICLK); + + writel(reset_bit, &scu->sysreset_ctrl2); + udelay(100); + //enable clk + writel(clkstop_bit, &scu->clk_stop_clr_ctrl2); + mdelay(10); + writel(reset_bit, &scu->sysreset_clr_ctrl2); + + return 0; +} + static int ast2600_clk_enable(struct clk *clk) { struct ast2600_clk_priv *priv = dev_get_priv(clk->dev); @@ -998,6 +1018,9 @@ static int ast2600_clk_enable(struct clk *clk) case ASPEED_CLK_GATE_EMMCEXTCLK: ast2600_enable_extemmcclk(priv->scu); break; + case ASPEED_CLK_GATE_FSICLK: + ast2600_enable_fsiclk(priv->scu); + break; default: pr_debug("can't enable clk \n"); return -ENOENT; From patchwork Wed Oct 30 06:32:23 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joel Stanley X-Patchwork-Id: 1186522 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 472zM520y5z9sPK for ; Wed, 30 Oct 2019 17:39:13 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=jms.id.au Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="BJa2kOMS"; dkim-atps=neutral Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 472zM512mPzF3kr for ; Wed, 30 Oct 2019 17:39:13 +1100 (AEDT) X-Original-To: openbmc@lists.ozlabs.org Delivered-To: openbmc@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gmail.com (client-ip=2607:f8b0:4864:20::536; helo=mail-pg1-x536.google.com; envelope-from=joel.stan@gmail.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=jms.id.au Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="BJa2kOMS"; dkim-atps=neutral Received: from mail-pg1-x536.google.com (mail-pg1-x536.google.com [IPv6:2607:f8b0:4864:20::536]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 472zCk4GRxzF3Wg for ; Wed, 30 Oct 2019 17:32:50 +1100 (AEDT) Received: by mail-pg1-x536.google.com with SMTP id c8so793071pgb.2 for ; Tue, 29 Oct 2019 23:32:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=6VMN1IKFIx3jGF5YftqewoqP/mwOTbnG816XtZGc/+I=; b=BJa2kOMSkTWIGc8Q9ZwkmxukFTYwejOUgnuRN1etQuRVvP+A3sK809TwJp5a+j3j3t zodaD55iSaG2DmMfAVjS0imlgaViWfIjRYBtn1ulUwFsDZS8XvLBOZbnClPlAxA+hs+a bfNg0bZPBsDRa+ViU/B8VtCDc5gEfWN6EFIPpZ9e3YelasnJcD4Jlib31taFZ0toWvKV KNFZzvJ9PzpV9rPPSsOimH/nyGQNywjty+eY7EIXo6ucQTSx0lvMRYBa8RtNgbkO5sD7 R9xfTo3eoLp90JGbQAt0yyet3i5QmXtHWnDR9h9eYa7HUzWTDkVTeYEas0fnCoZH6jbb 4yLg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=6VMN1IKFIx3jGF5YftqewoqP/mwOTbnG816XtZGc/+I=; b=FOp5V9MbldaKtEQFYG/z3YyqhXv3HyXx3wWSjCAIAOJ9A9BTTEFk6vquoDYsLPYa1v 54skajxhM4f0dfuxKPAsjNzV6p9YKPCF3DOaEITmEnAGxCu6XgqZBCyPEp4XZOmbqbJG YokUKf5H+aRcMeE6VISA0fruNAUHsFrlj68KAKXWn+pGxsq5Flf3kGO3XJ3ZORtThy+P 4lM/OA64zmOMBhvCwL9NID0ZHTOYeKHzCqoM4mTuFg36dewBW4VkATcbqoju6GbbeYU6 f6Nj/MyeJoG5t06+FWTzzgZEluq49xCkcLi36m5dosghTPNxrrSQ2S4i26pDQ4v9KTFE B4UQ== X-Gm-Message-State: APjAAAUv3wggUBbOTWW2EFKAGnndlEFYtBCUGnen4H0gKeB6F3xTLXTL OOqnQKWGQPY/frhfHXHuwek= X-Google-Smtp-Source: APXvYqxgY5phlRgfaIqm6k/UQ08/May4IvAwckUIYi7X/OU9yh6KmEiAr/xidXk128ivJ3JuYdZ9+w== X-Received: by 2002:a63:ae02:: with SMTP id q2mr10223332pgf.210.1572417168080; Tue, 29 Oct 2019 23:32:48 -0700 (PDT) Received: from voyager.ibm.com ([36.255.48.244]) by smtp.gmail.com with ESMTPSA id i102sm1028018pje.17.2019.10.29.23.32.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Oct 2019 23:32:47 -0700 (PDT) From: Joel Stanley To: Ryan Chen , Jeremy Kerr , Andrew Jeffery Subject: [PATCH u-boot aspeed-dev-v2019.04 5/7] dts: ast2600-evb: Enable FSI masters Date: Wed, 30 Oct 2019 17:02:23 +1030 Message-Id: <20191030063225.11319-6-joel@jms.id.au> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191030063225.11319-1-joel@jms.id.au> References: <20191030063225.11319-1-joel@jms.id.au> MIME-Version: 1.0 X-BeenThere: openbmc@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development list for OpenBMC List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: openbmc@lists.ozlabs.org Errors-To: openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "openbmc" Signed-off-by: Joel Stanley --- arch/arm/dts/ast2600-evb.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/dts/ast2600-evb.dts b/arch/arm/dts/ast2600-evb.dts index f8206c3ef0aa..1732424b0357 100644 --- a/arch/arm/dts/ast2600-evb.dts +++ b/arch/arm/dts/ast2600-evb.dts @@ -252,3 +252,11 @@ status = "okay"; }; #endif + +&fsim0 { + status = "okay"; +}; + +&fsim1 { + status = "okay"; +}; From patchwork Wed Oct 30 06:32:24 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joel Stanley X-Patchwork-Id: 1186523 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 472zNP5yXXz9sPK for ; Wed, 30 Oct 2019 17:40:21 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=jms.id.au Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="icyBij9R"; dkim-atps=neutral Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 472zNP2QrszF3lc for ; Wed, 30 Oct 2019 17:40:21 +1100 (AEDT) X-Original-To: openbmc@lists.ozlabs.org Delivered-To: openbmc@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gmail.com (client-ip=2607:f8b0:4864:20::643; helo=mail-pl1-x643.google.com; envelope-from=joel.stan@gmail.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=jms.id.au Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="icyBij9R"; dkim-atps=neutral Received: from mail-pl1-x643.google.com (mail-pl1-x643.google.com [IPv6:2607:f8b0:4864:20::643]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 472zCn0yp9zF3dq for ; Wed, 30 Oct 2019 17:32:53 +1100 (AEDT) Received: by mail-pl1-x643.google.com with SMTP id p5so510448plr.7 for ; Tue, 29 Oct 2019 23:32:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=FWUUmVkSSrsKHN00zrjqS9SsCMaN3B77zdCofuA+g7w=; b=icyBij9Ra/pgq7H7vE6nqrIbwFKttckuFrUllpSCDmCIK63OIRatDkJRDjvbvF5vxr 5xT2o2+t2xiKTIPwC6pH79V2Rvudn2nVQ2blCyjLgTGmneH37HP+IeHhdv1UF+rUNjOy rA6rBH9MPwVSGwhjiv7GfBk7lhW61yk8dtr93kFPzVWsiqaSn90rtgYeLEapJ61Vuw/8 hLO3YWKLIEhcsYEafRZHHC9cWZF2VJEVg0xvExYBvmrAeP0GN2591OpiT4Vr9ipX2FYw 67EE9HDUwiXm7WAzj0gebhFJKC/EAC6kF12yZyq2XL+Zz3yivnJZNTk6DgL6sXCLWHUm +PfQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=FWUUmVkSSrsKHN00zrjqS9SsCMaN3B77zdCofuA+g7w=; b=LTt4uUcMl5fOSnOPslScIza+8KshOvs1a5MF4Z4l8tPN4g9OMJDYC3X/8BO/tuP6QC jXDIOlJLlhrwTbyScKqni0ZeHD3a6jS9QCTil9hR3SaPlK9HEMAZQLUd3Mi8CwynnWMR 0383hB5Q/qM+XQtaRoByf3/c6O/tclwWoijB09FO/U9uQotQoYE6+InjI6O+oqv1+NQV +99r1CJ2oem1/iuko9bFRGYyuNuSE2XbbDQyxD1yqoMgBikabYyFOO24TDXtn9c+wwf4 SsSTuRwt5oM49DKjqlCRlBWrYHlujJwQBMPMjJr9saJZC+jXMZY/lpYzE6dnv+OZqxIh CbBA== X-Gm-Message-State: APjAAAWJxbS/DoAMwkZAQiXQQfCTcOz90YhQb1OGNPNAeRU21cMAN1dE RYxj8b9SWq1wGRUf6sN+QaM= X-Google-Smtp-Source: APXvYqy1SsOOuhXLt52EvdZz6sG5mLt7pCTWCAWHBHvgfT4K3ERylPIQqPoQAZ91/CNxwUSgW13kFA== X-Received: by 2002:a17:902:74c9:: with SMTP id f9mr2916714plt.105.1572417170901; Tue, 29 Oct 2019 23:32:50 -0700 (PDT) Received: from voyager.ibm.com ([36.255.48.244]) by smtp.gmail.com with ESMTPSA id i102sm1028018pje.17.2019.10.29.23.32.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Oct 2019 23:32:50 -0700 (PDT) From: Joel Stanley To: Ryan Chen , Jeremy Kerr , Andrew Jeffery Subject: [PATCH u-boot aspeed-dev-v2019.04 6/7] Add FSI driver Date: Wed, 30 Oct 2019 17:02:24 +1030 Message-Id: <20191030063225.11319-7-joel@jms.id.au> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191030063225.11319-1-joel@jms.id.au> References: <20191030063225.11319-1-joel@jms.id.au> MIME-Version: 1.0 X-BeenThere: openbmc@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development list for OpenBMC List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: openbmc@lists.ozlabs.org Errors-To: openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "openbmc" FSI is the Flexible Service Interface, an i2c-like bus used on IBM POWER processors for boot control, monitoring and debug. The ASPEED AST2600 contains a FSI master that can be used to talk to slaves on this bus. The u-boot driver is a light porting of the work in progress Linux driver. It allows basic reading and writing across the FSI link, as well as control of the bus speed divisor. Signed-off-by: Joel Stanley --- drivers/misc/Kconfig | 6 + drivers/misc/Makefile | 1 + drivers/misc/aspeed-fsi.c | 556 ++++++++++++++++++++++++++++++++++++++ include/aspeed_fsi.h | 14 + 4 files changed, 577 insertions(+) create mode 100644 drivers/misc/aspeed-fsi.c create mode 100644 include/aspeed_fsi.h diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig index e149d81fcc50..f73ab0755276 100644 --- a/drivers/misc/Kconfig +++ b/drivers/misc/Kconfig @@ -25,6 +25,12 @@ config ASPEED_H2X help Select this to enable AHB to PCIe bu Bridge driver for Aspeed SoC. +config ASPEED_FSI + bool "Enable ASPEED FSI driver" + depends on ARCH_ASPEED + help + Support the FSI master present in the ASPEED system on chips. + config ALTERA_SYSID bool "Altera Sysid support" depends on MISC diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index 61214bf9f17d..68713f149450 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -65,3 +65,4 @@ obj-$(CONFIG_TWL4030_LED) += twl4030_led.o obj-$(CONFIG_VEXPRESS_CONFIG) += vexpress_config.o obj-$(CONFIG_WINBOND_W83627) += winbond_w83627.o obj-$(CONFIG_JZ4780_EFUSE) += jz4780_efuse.o +obj-$(CONFIG_ASPEED_FSI) += aspeed-fsi.o diff --git a/drivers/misc/aspeed-fsi.c b/drivers/misc/aspeed-fsi.c new file mode 100644 index 000000000000..c41053252b10 --- /dev/null +++ b/drivers/misc/aspeed-fsi.c @@ -0,0 +1,556 @@ +// SPDX-License-Identifier: GPL-2.0+ +// Copyright (C) IBM Corporation 2018 +// FSI master driver for AST2600 + +#include +#include +#include +#include +#include + +#include +#include + +#include +#include + +/* Control Registers */ +#define FSI_MMODE 0x0 /* R/W: mode */ +#define FSI_MDLYR 0x4 /* R/W: delay */ +#define FSI_MCRSP 0x8 /* R/W: clock rate */ +#define FSI_MENP0 0x10 /* R/W: enable */ +#define FSI_MLEVP0 0x18 /* R: plug detect */ +#define FSI_MSENP0 0x18 /* S: Set enable */ +#define FSI_MCENP0 0x20 /* C: Clear enable */ +#define FSI_MAEB 0x70 /* R: Error address */ +#define FSI_MVER 0x74 /* R: master version/type */ +#define FSI_MSTAP0 0xd0 /* R: Port status */ +#define FSI_MRESP0 0xd0 /* W: Port reset */ +#define FSI_MESRB0 0x1d0 /* R: Master error status */ +#define FSI_MRESB0 0x1d0 /* W: Reset bridge */ +#define FSI_MSCSB0 0x1d4 /* R: Master sub command stack */ +#define FSI_MATRB0 0x1d8 /* R: Master address trace */ +#define FSI_MDTRB0 0x1dc /* R: Master data trace */ +#define FSI_MECTRL 0x2e0 /* W: Error control */ + +/* MMODE: Mode control */ +#define FSI_MMODE_EIP 0x80000000 /* Enable interrupt polling */ +#define FSI_MMODE_ECRC 0x40000000 /* Enable error recovery */ +#define FSI_MMODE_RELA 0x20000000 /* Enable relative address commands */ +#define FSI_MMODE_EPC 0x10000000 /* Enable parity checking */ +#define FSI_MMODE_P8_TO_LSB 0x00000010 /* Timeout value LSB */ + /* MSB=1, LSB=0 is 0.8 ms */ + /* MSB=0, LSB=1 is 0.9 ms */ +#define FSI_MMODE_CRS0SHFT 18 /* Clk rate selection 0 shift */ +#define FSI_MMODE_CRS0MASK 0x3ff /* Clk rate selection 0 mask */ +#define FSI_MMODE_CRS1SHFT 8 /* Clk rate selection 1 shift */ +#define FSI_MMODE_CRS1MASK 0x3ff /* Clk rate selection 1 mask */ + +/* MRESB: Reset brindge */ +#define FSI_MRESB_RST_GEN 0x80000000 /* General reset */ +#define FSI_MRESB_RST_ERR 0x40000000 /* Error Reset */ + +/* MRESB: Reset port */ +#define FSI_MRESP_RST_ALL_MASTER 0x20000000 /* Reset all FSI masters */ +#define FSI_MRESP_RST_ALL_LINK 0x10000000 /* Reset all FSI port contr. */ +#define FSI_MRESP_RST_MCR 0x08000000 /* Reset FSI master reg. */ +#define FSI_MRESP_RST_PYE 0x04000000 /* Reset FSI parity error */ +#define FSI_MRESP_RST_ALL 0xfc000000 /* Reset any error */ + +/* MECTRL: Error control */ +#define FSI_MECTRL_EOAE 0x8000 /* Enable machine check when */ + /* master 0 in error */ +#define FSI_MECTRL_P8_AUTO_TERM 0x4000 /* Auto terminate */ + +#define FSI_ENGID_HUB_MASTER 0x1c +#define FSI_HUB_LINK_OFFSET 0x80000 +#define FSI_HUB_LINK_SIZE 0x80000 +#define FSI_HUB_MASTER_MAX_LINKS 8 + +#define FSI_LINK_ENABLE_SETUP_TIME 10 /* in mS */ + +#define FSI_NUM_DEBUGFS_ENTRIES 17 + +#define DEFAULT_DIVISOR 14 + +struct fsi_master_aspeed; + +struct fsi_master_aspeed { + struct udevice *dev; + void __iomem *base; + struct clk clk; +}; + +#define to_fsi_master_aspeed(m) \ + container_of(m, struct fsi_master_aspeed, master) + +/* Control register (size 0x400) */ +static const u32 ctrl_base = 0x80000000; + +static const u32 fsi_base = 0xa0000000; + +#define OPB_FSI_VER 0x00 +#define OPB_TRIGGER 0x04 +#define OPB_CTRL_BASE 0x08 +#define OPB_FSI_BASE 0x0c +#define OPB_CLK_SYNC 0x3c +#define OPB_IRQ_CLEAR 0x40 +#define OPB_IRQ_MASK 0x44 +#define OPB_IRQ_STATUS 0x48 + +#define OPB0_SELECT 0x10 +#define OPB0_RW 0x14 +#define OPB0_XFER_SIZE 0x18 +#define OPB0_FSI_ADDR 0x1c +#define OPB0_FSI_DATA_W 0x20 +#define OPB0_STATUS 0x80 +/* half world */ +#define STATUS_HW_ACK BIT(0) +/* full word */ +#define STATUS_FW_ACK BIT(1) +#define STATUS_ERR_ACK BIT(2) +#define OPB0_FSI_DATA_R 0x84 + +#define OPB0_W_ENDIAN 0x4c +#define OPB0_R_ENDIAN 0x5c + +/* OPB_IRQ_MASK */ +#define OPB1_XFER_ACK_EN BIT(17) +#define OPB0_XFER_ACK_EN BIT(16) + +#define OPB_IRQ_CH0_DMA_EOT BIT(0) +#define OPB_IRQ_CH1_DMA_EOT BIT(1) +#define OPB_IRQ_CH2_DMA_EOT BIT(2) +#define OPB_IRQ_CH3_DMA_EOT BIT(3) +#define OPB_IRQ_CH0_DMA_FIFO_FULL BIT(4) +#define OPB_IRQ_CH1_DMA_FIFO_FULL BIT(5) +#define OPB_IRQ_CH2_DMA_FIFO_FULL BIT(6) +#define OPB_IRQ_CH3_DMA_FIFO_FULL BIT(7) +#define OPB_IRQ_CH0_DMA_FIFO_EMPTY BIT(8) +#define OPB_IRQ_CH1_DMA_FIFO_EMPTY BIT(9) +#define OPB_IRQ_CH2_DMA_FIFO_EMPTY BIT(10) +#define OPB_IRQ_CH3_DMA_FIFO_EMPTY BIT(11) +#define OPB_IRQ_CH0_DMA_TCONT_DONE BIT(12) +#define OPB_IRQ_CH1_DMA_TCONT_DONE BIT(13) +#define OPB_IRQ_CH2_DMA_TCONT_DONE BIT(14) +#define OPB_IRQ_CH3_DMA_TCONT_DONE BIT(15) +#define OPB_IRQ_OPB1_XFER_ACK BIT(16) +#define OPB_IRQ_OPB0_XFER_ACK BIT(17) +#define OPB_IRQ_SLAVE0 BIT(18) +#define OPB_IRQ_SLAVE1 BIT(19) +#define OPB_IRQ_SLAVE2 BIT(20) +#define OPB_IRQ_SLAVE3 BIT(21) +#define OPB_IRQ_SLAVE4 BIT(22) +#define OPB_IRQ_SLAVE5 BIT(23) +#define OPB_IRQ_SLAVE6 BIT(24) +#define OPB_IRQ_SLAVE7 BIT(25) +#define OPB_IRQ_ANY_HOTPLUG BIT(26) +#define OPB_IRQ_ANY_PORT_ERROR BIT(27) +#define OPB_IRQ_ANY_MST_ERROR BIT(28) + +/* OPB_RW */ +#define CMD_READ BIT(0) +#define CMD_WRITE 0 + +/* OPBx_XFER_SIZE */ +#define XFER_WORD (BIT(1) | BIT(0)) +#define XFER_NIBBLE (BIT(0)) +#define XFER_BYTE (0) + +#define trace_aspeed_fsi_opb_write(addr, val, size, status, reg) \ + debug("aspeed_opb_write: addr %08x val %08x size %d status %08d reg %08d\n", \ + addr, val, size, status, reg) + +#define trace_aspeed_fsi_opb_read(addr, size, result, status, reg) \ + debug("aspeed_opb_read: addr %08x size %d result %08x status %08d reg %08d\n", \ + addr, size, result, status, reg) + +#define trace_aspeed_fsi_opb_error(mresp0, mstap0, mesrb0) \ + debug("aspeed_opb_error: mresp %08d mstap %08x mesrb %08x\n", \ + mresp0, mstap0, mesrb0) + +#define trace_aspeed_fsi_opb_error_enabled() (_DEBUG) + +static u32 opb_write(struct fsi_master_aspeed *aspeed, uint32_t addr, + uint32_t val, size_t size) +{ + void __iomem *base = aspeed->base; + u32 reg, ret, status; + + /* TODO: implement other sizes, see 0x18 */ + WARN_ON(size != 4); + + writel(CMD_WRITE, base + OPB0_RW); + writel(XFER_WORD, base + OPB0_XFER_SIZE); + writel(addr, base + OPB0_FSI_ADDR); + writel(val, base + OPB0_FSI_DATA_W); + writel(0x1, base + OPB_IRQ_CLEAR); + writel(0x1, base + OPB_TRIGGER); + + ret = readl_poll_timeout(base + OPB_IRQ_STATUS, reg, + (reg & OPB0_XFER_ACK_EN) != 0, + 10000); + + status = readl(base + OPB0_STATUS); + + trace_aspeed_fsi_opb_write(addr, val, size, status, reg); + + /* Return error when poll timed out */ + if (ret) + return ret; + + /* Command failed, master will reset */ + if (status & STATUS_ERR_ACK) + return -EIO; + + return 0; +} + +static int opb_read(struct fsi_master_aspeed *aspeed, uint32_t addr, + size_t size, u32 *out) +{ + void __iomem *base = aspeed->base; + u32 result, reg; + int status, ret; + + /* TODO: implement other sizes, see 0x18 */ + WARN_ON(size != 4); + + writel(CMD_READ, base + OPB0_RW); + writel(XFER_WORD, base + OPB0_XFER_SIZE); + writel(addr, base + OPB0_FSI_ADDR); + writel(0x1, base + OPB_IRQ_CLEAR); + writel(0x1, base + OPB_TRIGGER); + + ret = readl_poll_timeout(base + OPB_IRQ_STATUS, reg, + (reg & OPB0_XFER_ACK_EN) != 0, + 10000); + + status = readl(base + OPB0_STATUS); + + result = readl(base + OPB0_FSI_DATA_R); + + trace_aspeed_fsi_opb_read(addr, size, result, + readl(base + OPB0_STATUS), + reg); + + /* Return error when poll timed out */ + if (ret) + return ret; + + /* Command failed, master will reset */ + if (status & STATUS_ERR_ACK) + return -EIO; + + if (out) + *out = result; + + return 0; +} + +static int check_errors(struct fsi_master_aspeed *aspeed, int err) +{ + int ret; + + if (trace_aspeed_fsi_opb_error_enabled()) { + __be32 mresp0, mstap0, mesrb0; + + opb_read(aspeed, ctrl_base + FSI_MRESP0, 4, &mresp0); + opb_read(aspeed, ctrl_base + FSI_MSTAP0, 4, &mstap0); + opb_read(aspeed, ctrl_base + FSI_MESRB0, 4, &mesrb0); + + trace_aspeed_fsi_opb_error( + be32_to_cpu(mresp0), + be32_to_cpu(mstap0), + be32_to_cpu(mesrb0)); + }; + + if (err == -EIO) { + /* Check MAEB (0x70) ? */ + + /* Then clear errors in master */ + ret = opb_write(aspeed, ctrl_base + 0xd0, + cpu_to_be32(0x20000000), 4); + if (ret) { + /* TODO: log? return different code? */ + return ret; + } + /* TODO: confirm that 0x70 was okay */ + } + + /* This will pass through timeout errors */ + return err; +} + +int aspeed_fsi_read(struct fsi_master_aspeed *aspeed, int link, + uint32_t addr, void *val, size_t size) +{ + int ret; + + addr += link * FSI_HUB_LINK_SIZE; + ret = opb_read(aspeed, fsi_base + addr, size, val); + + ret = check_errors(aspeed, ret); + if (ret) + return ret; + + return 0; +} + +int aspeed_fsi_write(struct fsi_master_aspeed *aspeed, int link, + uint8_t id, uint32_t addr, const void *val, size_t size) +{ + int ret; + + if (id != 0) + return -EINVAL; + + addr += link * FSI_HUB_LINK_SIZE; + ret = opb_write(aspeed, fsi_base + addr, *(uint32_t *)val, size); + + ret = check_errors(aspeed, ret); + if (ret) + return ret; + + return 0; +} + +int aspeed_fsi_link_enable(struct fsi_master_aspeed *aspeed, int link) +{ + int idx, bit, ret; + __be32 reg, result; + + idx = link / 32; + bit = link % 32; + + reg = cpu_to_be32(0x80000000 >> bit); + + result = opb_write(aspeed, ctrl_base + FSI_MSENP0 + (4 * idx), + reg, 4); + + mdelay(FSI_LINK_ENABLE_SETUP_TIME); + + ret = opb_read(aspeed, ctrl_base + FSI_MENP0 + (4 * idx), + 4, &result); + if (ret) + return ret; + + if (result != reg) { + dev_err(aspeed->dev, "%s failed: %08x\n", __func__, result); + return -EIO; + } + + return 0; +} + +int aspeed_fsi_break(struct fsi_master_aspeed *aspeed, int link) +{ + uint32_t addr; + __be32 cmd; + int rc; + + addr = 0x0; + cmd = cpu_to_be32(0xc0de0000); + + dev_dbg(aspeed->dev, "sending break to link %d\n", link); + + rc = aspeed_fsi_write(aspeed, link, 0, addr, &cmd, 4); + + dev_dbg(aspeed->dev, "break done (%d)\n", rc); + + return rc; +} + +void aspeed_fsi_status(struct fsi_master_aspeed *aspeed) +{ + __be32 mmode, mresp0, mstap0, mesrb0; + + printf("%s\n", aspeed->dev->name); + + opb_read(aspeed, ctrl_base + FSI_MMODE, 4, &mmode); + opb_read(aspeed, ctrl_base + FSI_MRESP0, 4, &mresp0); + opb_read(aspeed, ctrl_base + FSI_MSTAP0, 4, &mstap0); + opb_read(aspeed, ctrl_base + FSI_MESRB0, 4, &mesrb0); + + printf("mmode %08x\n", be32_to_cpu(mmode)); + printf("mresp %08x\n", be32_to_cpu(mresp0)); + printf("mresp %08x\n", be32_to_cpu(mstap0)); + printf("mresp %08x\n", be32_to_cpu(mesrb0)); +} + +int aspeed_fsi_divisor(struct fsi_master_aspeed *aspeed, uint16_t divisor) +{ + __be32 reg; + int rc; + + rc = opb_read(aspeed, ctrl_base, 4, ®); + if (rc) + return rc; + + if (!divisor) + return (be32_to_cpu(reg) >> 18) & 0x3ff; + + if (divisor > 0x3ff) + return -EINVAL; + + reg &= ~(0x3ff << 18); + reg |= (divisor & 0x3ff) << 18; + + return 0; +} + +/* mmode encoders */ +static inline u32 fsi_mmode_crs0(u32 x) +{ + return (x & FSI_MMODE_CRS0MASK) << FSI_MMODE_CRS0SHFT; +} + +static inline u32 fsi_mmode_crs1(u32 x) +{ + return (x & FSI_MMODE_CRS1MASK) << FSI_MMODE_CRS1SHFT; +} + +static int aspeed_fsi_init(struct fsi_master_aspeed *aspeed) +{ + __be32 reg; + + reg = cpu_to_be32(FSI_MRESP_RST_ALL_MASTER | FSI_MRESP_RST_ALL_LINK + | FSI_MRESP_RST_MCR | FSI_MRESP_RST_PYE); + opb_write(aspeed, ctrl_base + FSI_MRESP0, reg, 4); + + /* Initialize the MFSI (hub master) engine */ + reg = cpu_to_be32(FSI_MRESP_RST_ALL_MASTER | FSI_MRESP_RST_ALL_LINK + | FSI_MRESP_RST_MCR | FSI_MRESP_RST_PYE); + opb_write(aspeed, ctrl_base + FSI_MRESP0, reg, 4); + + reg = cpu_to_be32(FSI_MECTRL_EOAE | FSI_MECTRL_P8_AUTO_TERM); + opb_write(aspeed, ctrl_base + FSI_MECTRL, reg, 4); + + reg = cpu_to_be32(FSI_MMODE_ECRC | FSI_MMODE_EPC | FSI_MMODE_RELA + | fsi_mmode_crs0(DEFAULT_DIVISOR) + | fsi_mmode_crs1(DEFAULT_DIVISOR) + | FSI_MMODE_P8_TO_LSB); + opb_write(aspeed, ctrl_base + FSI_MMODE, reg, 4); + + reg = cpu_to_be32(0xffff0000); + opb_write(aspeed, ctrl_base + FSI_MDLYR, reg, 4); + + reg = cpu_to_be32(~0); + opb_write(aspeed, ctrl_base + FSI_MSENP0, reg, 4); + + /* Leave enabled long enough for master logic to set up */ + mdelay(FSI_LINK_ENABLE_SETUP_TIME); + + opb_write(aspeed, ctrl_base + FSI_MCENP0, reg, 4); + + opb_read(aspeed, ctrl_base + FSI_MAEB, 4, NULL); + + reg = cpu_to_be32(FSI_MRESP_RST_ALL_MASTER | FSI_MRESP_RST_ALL_LINK); + opb_write(aspeed, ctrl_base + FSI_MRESP0, reg, 4); + + opb_read(aspeed, ctrl_base + FSI_MLEVP0, 4, NULL); + + /* Reset the master bridge */ + reg = cpu_to_be32(FSI_MRESB_RST_GEN); + opb_write(aspeed, ctrl_base + FSI_MRESB0, reg, 4); + + reg = cpu_to_be32(FSI_MRESB_RST_ERR); + opb_write(aspeed, ctrl_base + FSI_MRESB0, reg, 4); + + return 0; +} + +static int aspeed_fsi_probe(struct udevice *dev) +{ + struct fsi_master_aspeed *aspeed = dev_get_priv(dev); + int ret, links, reg; + __be32 raw; + + printf("%s\n", __func__); + + aspeed->dev = dev; + + aspeed->base = (void *)devfdt_get_addr(dev); + + ret = clk_get_by_index(dev, 0, &aspeed->clk); + if (ret < 0) { + dev_err(dev, "Can't get clock for %s: %d\n", dev->name, ret); + return ret; + } + + ret = clk_enable(&aspeed->clk); + if (ret) { + dev_err(dev, "failed to enable fsi clock (%d)\n", ret); + return ret; + } + + printf("%s %d\n", __func__, __LINE__); + + writel(0x1, aspeed->base + OPB_CLK_SYNC); + writel(OPB1_XFER_ACK_EN | OPB0_XFER_ACK_EN, + aspeed->base + OPB_IRQ_MASK); + + writel(ctrl_base, aspeed->base + OPB_CTRL_BASE); + writel(fsi_base, aspeed->base + OPB_FSI_BASE); + + /* Set read data order */ + writel(0x00030b1b, aspeed->base + OPB0_R_ENDIAN); + + /* Set write data order */ + writel(0x0011bb1b, aspeed->base + OPB0_W_ENDIAN); + writel(0xffaa5500, aspeed->base + 0x50); + + /* + * Select OPB0 for all operations. + * Will need to be reworked when enabling DMA or anything that uses + * OPB1. + */ + writel(0x1, aspeed->base + OPB0_SELECT); + + printf("%s %d\n", __func__, __LINE__); + + ret = opb_read(aspeed, ctrl_base + FSI_MVER, 4, &raw); + if (ret) { + dev_err(&pdev->dev, "failed to read hub version\n"); + goto err; + } + + printf("%s %d\n", __func__, __LINE__); + + reg = be32_to_cpu(raw); + links = (reg >> 8) & 0xff; + dev_info(&pdev->dev, "hub version %08x (%d links)\n", reg, links); + + aspeed_fsi_init(aspeed); + + printf("%s: probe done\n", __func__); + + return 0; + +err: + clk_disable(&aspeed->clk); + return ret; +} + +static int aspeed_fsi_remove(struct udevice *dev) +{ + struct fsi_master_aspeed *aspeed = dev_get_priv(dev); + + clk_disable(&aspeed->clk); + + return 0; +} + +static const struct udevice_id aspeed_fsi_ids[] = { + { .compatible = "aspeed,ast2600-fsi-master" }, + { } +}; + +U_BOOT_DRIVER(aspeed_fsi) = { + .name = "aspeed_fsi", + .id = UCLASS_MISC, + .of_match = aspeed_fsi_ids, + .probe = aspeed_fsi_probe, + .remove = aspeed_fsi_remove, + .priv_auto_alloc_size = sizeof(struct fsi_master_aspeed), +}; diff --git a/include/aspeed_fsi.h b/include/aspeed_fsi.h new file mode 100644 index 000000000000..c8d6616ef8e1 --- /dev/null +++ b/include/aspeed_fsi.h @@ -0,0 +1,14 @@ +struct fsi_master_aspeed; + +int aspeed_fsi_read(struct fsi_master_aspeed *aspeed, int link, + uint32_t addr, void *val, size_t size); + +int aspeed_fsi_write(struct fsi_master_aspeed *aspeed, int link, + uint32_t addr, const void *val, size_t size); + +int aspeed_fsi_break(struct fsi_master_aspeed *aspeed, int link); + +int aspeed_fsi_status(struct fsi_master_aspeed *aspeed); + +int aspeed_fsi_divisor(struct fsi_master_aspeed *aspeed, uint16_t divisor); + From patchwork Wed Oct 30 06:32:25 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Joel Stanley X-Patchwork-Id: 1186524 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 472zQS6Ybqz9sPK for ; Wed, 30 Oct 2019 17:42:08 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=jms.id.au Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="cfubxFSL"; dkim-atps=neutral Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 472zQR49LRzF38g for ; Wed, 30 Oct 2019 17:42:07 +1100 (AEDT) X-Original-To: openbmc@lists.ozlabs.org Delivered-To: openbmc@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=gmail.com (client-ip=2607:f8b0:4864:20::531; helo=mail-pg1-x531.google.com; envelope-from=joel.stan@gmail.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=jms.id.au Authentication-Results: lists.ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="cfubxFSL"; dkim-atps=neutral Received: from mail-pg1-x531.google.com (mail-pg1-x531.google.com [IPv6:2607:f8b0:4864:20::531]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 472zCr232HzF3Wx for ; Wed, 30 Oct 2019 17:32:56 +1100 (AEDT) Received: by mail-pg1-x531.google.com with SMTP id p12so778794pgn.6 for ; Tue, 29 Oct 2019 23:32:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=iDMyEbE5ColevdJEwW59F/OD86x49Mmi6aNDASg5oYY=; b=cfubxFSLY9FNpQzSTVgeKs3vEJKqFudxuDqNw6yKaPhcAfUZIUdokkbtyXotHUjaMu wpGC3bs5gTHiIKUGgxpohOuF0gB0PpvmOYynI9wo+neDLWV6islQjQEl/vNAHyeVMjIr hOA7Um/wBbqirNU39V09J/8a6EJ88ZuO/twYWs5/TsSZWhw4VcWWANLROudbPbG0ggSz cKRl/QW0b91sqv3+bH3BThu3m0HWhgdEnx2a6tZD1Sd6w/xaO2/8/hLrdiTiY+WXZShU T2WJcAm8kcUyEsYwlhLg1qfJUyySJq0qaRs6wwVNYq282+qCVmrrt5xKIhX1B+E5i7px P3Zg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=iDMyEbE5ColevdJEwW59F/OD86x49Mmi6aNDASg5oYY=; b=sbT5CsXiYBBzpYD6LB3tf3EeJAO6/DjhbKKxDS4Iz7IP3q6GUtvnTBdPJHSxFoG5+f CxQHIto0/oZytPBmhXWsc5JbhcvouAmRgPlgONyYxxx7Jog65BNLNFN1Ozr5ywHpJ7FZ nZnvAKAaAQuabGRl145b1LlrF9An0VOvgzVVHMfnQG6AVuDTph8bUlcKsMk2f0RslukI FPPO1Rg1gGMp8zEyrYRR+rHS/z9oqGnQFlcdeM4WuCMBTMNN7Pmng+i/A8TuH++ZyQPY c4+J1ei+P4Ns6Z5zDytftPHQJgszWmF3aWahIWDbSn8U55p6TAZZYxJfXYehQVjSdeSp ozjg== X-Gm-Message-State: APjAAAUIBvJoiK4LmEM8T7L1m6gg54ptd/2DmliPusw3/rFzsRuwi/QW f7wC5tTmYCsZ7FvebWf29Dqdii3NEX8= X-Google-Smtp-Source: APXvYqzR5wz4nS7MVREyXyVXxDjmFeOZHNakAn3vBdzELQQwTbIliSF6g6GnIM9TL/dTQ1sXagj4Jw== X-Received: by 2002:a17:90a:178e:: with SMTP id q14mr323477pja.134.1572417173701; Tue, 29 Oct 2019 23:32:53 -0700 (PDT) Received: from voyager.ibm.com ([36.255.48.244]) by smtp.gmail.com with ESMTPSA id i102sm1028018pje.17.2019.10.29.23.32.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 29 Oct 2019 23:32:53 -0700 (PDT) From: Joel Stanley To: Ryan Chen , Jeremy Kerr , Andrew Jeffery Subject: [PATCH u-boot aspeed-dev-v2019.04 7/7] cmd: Add FSI command Date: Wed, 30 Oct 2019 17:02:25 +1030 Message-Id: <20191030063225.11319-8-joel@jms.id.au> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191030063225.11319-1-joel@jms.id.au> References: <20191030063225.11319-1-joel@jms.id.au> MIME-Version: 1.0 X-BeenThere: openbmc@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development list for OpenBMC List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: openbmc@lists.ozlabs.org Errors-To: openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "openbmc" This allows a user to issue breaks, and read and write CFAM (remote FSI) addresses. The master to use on the command line can be selected from the probe command. # fsi probe 0 # fsi break Signed-off-by: Joel Stanley --- cmd/Kconfig | 6 ++ cmd/Makefile | 1 + cmd/fsi.c | 153 +++++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 160 insertions(+) create mode 100644 cmd/fsi.c diff --git a/cmd/Kconfig b/cmd/Kconfig index 68afd06b101e..221a07eed5a6 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -692,6 +692,12 @@ config CMD_FDC help The 'fdtboot' command allows booting an image from a floppy disk. +config CMD_FSI + bool "fsi - use FSI master" + depends on ASPEED_FSI + help + The 'fsi' command allows use of the FSI master present in ASPEED SoCs + config CMD_FLASH bool "flinfo, erase, protect" default y diff --git a/cmd/Makefile b/cmd/Makefile index 493f241f39d6..05bc0410d5d1 100644 --- a/cmd/Makefile +++ b/cmd/Makefile @@ -64,6 +64,7 @@ obj-$(CONFIG_CMD_FLASH) += flash.o obj-$(CONFIG_CMD_FPGA) += fpga.o obj-$(CONFIG_CMD_FPGAD) += fpgad.o obj-$(CONFIG_CMD_FS_GENERIC) += fs.o +obj-$(CONFIG_CMD_FSI) += fsi.o obj-$(CONFIG_CMD_FUSE) += fuse.o obj-$(CONFIG_CMD_GETTIME) += gettime.o obj-$(CONFIG_CMD_GPIO) += gpio.o diff --git a/cmd/fsi.c b/cmd/fsi.c new file mode 100644 index 000000000000..7dacf7957961 --- /dev/null +++ b/cmd/fsi.c @@ -0,0 +1,153 @@ +#include +#include +#include +#include +#include + +struct fsi_master_aspeed *fsi; + +static void do_break(void) +{ + debug("%s\n", __func__); + aspeed_fsi_break(fsi, 0); +} + +static void do_status(void) +{ + debug("%s\n", __func__); + aspeed_fsi_status(fsi); +} + +static void do_getcfam(int argc, char *const argv[]) +{ + int rc; + uint32_t addr, val; + + if (argc != 3) { + printf("invalid arguments to getcfam\n"); + return; + } + + addr = simple_strtoul(argv[2], NULL, 16); + + debug("%s %08x\n", __func__, addr); + rc = aspeed_fsi_read(fsi, 0, addr, &val, 4); + if (rc) { + printf("error reading: %d\n", rc); + return; + } + + printf("0x%08x\n", be32_to_cpu(val)); +} + +static void do_putcfam(int argc, char *const argv[]) +{ + int rc; + uint32_t addr, val; + + if (argc != 4) { + printf("invalid arguments to putcfam\n"); + return; + } + + addr = simple_strtoul(argv[2], NULL, 16); + val = simple_strtoul(argv[3], NULL, 16); + + debug("%s %08x %08x\n", __func__, addr, val); + rc = aspeed_fsi_write(fsi, 0, addr, &val, 4); + if (rc) + printf("error writing: %d\n", rc); +} + +static void do_divisor(int argc, char *const argv[]) +{ + int rc; + uint32_t val; + + if (argc == 2) { + rc = aspeed_fsi_divisor(fsi, 0); + if (rc > 0) + printf("divsior: %d (%d MHz)\n", rc, rc * 166); + } else if (argc == 3) { + val = simple_strtoul(argv[2], NULL, 16); + rc = aspeed_fsi_divisor(fsi, val); + } else { + printf("invalid arguments to divisor\n"); + return; + } + + if (rc < 0) + printf("divisor error: %d\n", rc); +} + +static struct fsi_master_aspeed *do_probe(int argc, char *const argv[]) +{ + struct udevice *dev; + const char *devices[] = {"fsi@1e79b000", "fsi@1e79b100"}; + int rc, id; + + if (argc > 3) { + printf("invalid arguments to probe\n"); + return NULL; + } + + if (argc == 2) + id = 0; + else + id = simple_strtoul(argv[2], NULL, 10); + + if (id > 1) { + printf("valid devices: 0, 1\n"); + return NULL; + } + + rc = uclass_get_device_by_name(UCLASS_MISC, devices[id], &dev); + if (rc) { + printf("fsi device %s not found\n", devices[id]); + return NULL; + } + return dev_get_priv(dev); +} + + +static int do_fsi(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) +{ + + if (!strcmp(argv[1], "probe")) { + fsi = do_probe(argc, argv); + return 0; + } + + if (fsi == NULL) { + printf("Run probe first\n"); + return -EINVAL; + } + + if (!strcmp(argv[1], "break")) + do_break(); + else if (!strcmp(argv[1], "status")) + do_status(); + else if (!strncmp(argv[1], "put", 3)) + do_putcfam(argc, argv); + else if (!strncmp(argv[1], "get", 3)) + do_getcfam(argc, argv); + else if (!strncmp(argv[1], "div", 3)) + do_divisor(argc, argv); + + return 0; +} + +static char fsi_help_text[] = + "fsi probe []\n" + "fsi break\n" + "fsi getcfam \n" + "fsi putcfam \n" + "fsi divisor []\n" + "fsi status\n"; + +U_BOOT_CMD( + fsi, 4, 1, do_fsi, + "IBM FSI commands", + fsi_help_text +); +