From patchwork Mon Oct 28 15:48:45 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Palmer Dabbelt X-Patchwork-Id: 1185521 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=sifive.com header.i=@sifive.com header.b="DS658puG"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4720Nn6pY3z9sPL for ; Tue, 29 Oct 2019 03:22:17 +1100 (AEDT) Received: from localhost ([::1]:57668 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iP7mZ-0000ah-C3 for incoming@patchwork.ozlabs.org; Mon, 28 Oct 2019 12:22:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34458) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iP7PQ-0004yP-Bt for qemu-devel@nongnu.org; Mon, 28 Oct 2019 11:58:21 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iP7PP-0003i7-58 for qemu-devel@nongnu.org; Mon, 28 Oct 2019 11:58:20 -0400 Received: from mail-pf1-x431.google.com ([2607:f8b0:4864:20::431]:44014) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iP7PO-0003hr-WB for qemu-devel@nongnu.org; Mon, 28 Oct 2019 11:58:19 -0400 Received: by mail-pf1-x431.google.com with SMTP id 3so7142258pfb.10 for ; Mon, 28 Oct 2019 08:58:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding:cc:from:to; bh=82Sn/rUNpaBL69nnrf10mEtZ0FP8XTRyAcCtMChhF04=; b=DS658puGtOK1gm7nUVpoEeQqkx5tP6LrucwbcXZ0fe8FkaLNKvJyqFUo4xyTXlTjOI eHuW374OIu98yw4RbKlGP37ree7TQsZl1hWu1KKrUEJvmZt1xijwegjFj4yUZosrN313 wmZphjgiFWdha85551b/WMI6YnGINgAegsyYnG/JUER1jpgtsOiFJefzFYaJWTOd1GYH 6JA4Ct9/0dD6TEVBScP7Ip09aZxsNKDhcI34WKLei2hsWxFhpgtveWdBPtHP1CYYXRpi ZYFH47TSAd1S0QEWXh2Km7EhZ7BwM9IvSk5cwcg3WjuEp65AXwIzaeZGFgWfPJGyg/kH 4s1Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:cc:from:to; bh=82Sn/rUNpaBL69nnrf10mEtZ0FP8XTRyAcCtMChhF04=; b=GBHScEKprC/n8Xxq8hOgZ9ISVWQeDsUgx3yvzlTMW0iRyWgHlS+4dE73pTfEsEZmmw BT5SCRLx7X4CcdYqRJ506D+Ayq6i8hCFsR+iSD9BwFdJdAVgam4yb8/cqkHLWCqv0e7s aQHFWqcdjdtxQaqosmmwWTRgGRqXQOnP9O83N5YwmNWxFR30wK3OfKhxA/9eTp/OfHLL KFH/E608j4kY40utbZ17HD+m9+odQhueaY5s+ES8Kjd0nodN7D4FuPg6V4FHUoAFza5X U6oCAeWm4o9HRwatU6v12kGRM4+b9AecpvsyM7Qari+HNo+0GLnIh2Hu3YGXooIY8Bxd 2VBw== X-Gm-Message-State: APjAAAUJvajEuIlLD0F5FZpBBZHsGDTwqUQtihweTXD72h/emqIv1BVX 6rhZFkHLFMfVxFZnZU30XQcucGbWS7kRCg== X-Google-Smtp-Source: APXvYqxYKk+tJb3qDpAVHf+0eH4qtoKBrMgx6VE1Z5IjTN2gkfGOIOSdOXJhCBy9iaA4CpceEEhCbA== X-Received: by 2002:a17:90a:cb8e:: with SMTP id a14mr902633pju.64.1572278297705; Mon, 28 Oct 2019 08:58:17 -0700 (PDT) Received: from localhost ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id l64sm12865766pga.88.2019.10.28.08.58.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Oct 2019 08:58:16 -0700 (PDT) Subject: [PULL 01/18] riscv: Skip checking CSR privilege level in debugger mode Date: Mon, 28 Oct 2019 08:48:45 -0700 Message-Id: <20191028154902.32491-2-palmer@sifive.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191028154902.32491-1-palmer@sifive.com> References: <20191028154902.32491-1-palmer@sifive.com> MIME-Version: 1.0 From: Palmer Dabbelt To: Peter Maydell X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::431 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, Palmer Dabbelt , qemu-devel@nongnu.org, Alistair Francis , Zong Li , Bin Meng Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng If we are in debugger mode, skip the CSR privilege level checking so that we can read/write all CSRs. Otherwise we get: (gdb) p/x $mtvec Could not fetch register "mtvec"; remote failure reply 'E14' when the hart is currently in S-mode. Reported-by: Zong Li Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Signed-off-by: Palmer Dabbelt --- target/riscv/csr.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index f767ad24be..974c9c20b5 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -801,7 +801,10 @@ int riscv_csrrw(CPURISCVState *env, int csrno, target_ulong *ret_value, #if !defined(CONFIG_USER_ONLY) int csr_priv = get_field(csrno, 0x300); int read_only = get_field(csrno, 0xC00) == 3; - if ((write_mask && read_only) || (env->priv < csr_priv)) { + if ((!env->debugger) && (env->priv < csr_priv)) { + return -1; + } + if (write_mask && read_only) { return -1; } #endif From patchwork Mon Oct 28 15:48:46 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Palmer Dabbelt X-Patchwork-Id: 1185527 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=sifive.com header.i=@sifive.com header.b="hd8eDErr"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4720Wp5x62z9sPK for ; Tue, 29 Oct 2019 03:28:22 +1100 (AEDT) Received: from localhost ([::1]:58110 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iP7sS-0004bD-7i for incoming@patchwork.ozlabs.org; Mon, 28 Oct 2019 12:28:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34494) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iP7PS-00051u-6s for qemu-devel@nongnu.org; Mon, 28 Oct 2019 11:58:23 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iP7PR-0003jJ-2h for qemu-devel@nongnu.org; Mon, 28 Oct 2019 11:58:22 -0400 Received: from mail-pl1-x641.google.com ([2607:f8b0:4864:20::641]:36294) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iP7PQ-0003j0-Tl for qemu-devel@nongnu.org; Mon, 28 Oct 2019 11:58:21 -0400 Received: by mail-pl1-x641.google.com with SMTP id g9so5183624plp.3 for ; Mon, 28 Oct 2019 08:58:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding:cc:from:to; bh=D5lUa8xwyAhQuJBABUbBfsge6X0s1+ub7iA6TO4kaOc=; b=hd8eDErr/6e475gD3H5orDwGbZdvxBBHYUa3YRamsq5Tc0viHoPNow12xJJh8unBJl plKFgjXV9PIu4L1dn0FMQQQWYYHgHTkQHeZX7Ebg4rSQU9d+MbfD/4an0czA++PZ27gq +ecEmqz6/EaZqc2B+uNeb+ykS2Ky0CXw1CRaI5smQ4AmRi8pjmpFYZqAU6RPL023YUG4 W0tQU8NkuNRBOB3FeIIpsUvb8P6MN5UawV6TYt7lYRvsCEGfxUFDGrngjwXn+nZbS65Y y9RKm7zAhgIO8Z9reQbV1nIR5A4CUBMJ7tiVHRDQCeI94RTV7Wae37WEWAe7NlMSIOaQ +6hw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:cc:from:to; bh=D5lUa8xwyAhQuJBABUbBfsge6X0s1+ub7iA6TO4kaOc=; b=YMvpXMe2wXBii4ycRtXpVHQ6dvs3AS62dxSzg4bvm3QM27Mz558ck8OEblleRh8xZ+ VEor+fidI1Z/zVM7EXawje3oswiEED8uq2o+OrGfP/OV5jQCl9hsSWgKeqOgMQvCrqru 9Bp7MCxZqo7BGceAuG+vHUvu4Y6UCeAmwdzgKl4SphNWVfhX0Y6M6miQ3/qRnC/QHoHY g8VKgs6hEFz9V4O7dQkvjMr1PiXyBvZJTw4OWKjcES8ZhdExufUs2jF5PRM0zqzgWnpV YPCk1MYAYvORM4o6v1RS87oT7Pe7zvUPxrH044ACpYkFOYb8oqIfvy4T2LmZFUOfzoKQ Dx1A== X-Gm-Message-State: APjAAAUJJH1wGq3ydiPj3Mm+5PSY1z4ucjPFl8SxcKVZdEvcoU2o/trU 9+yIj0KNQdM1UuDsgYoFij1xKZPzxFE7Vg== X-Google-Smtp-Source: APXvYqyq3M+syw8xc6lucIqG7RBmg6RqYTXD2wiHLFaNKi4f+rK2gBJb05CmXV70xHeTohNZ5o5PKQ== X-Received: by 2002:a17:902:7c07:: with SMTP id x7mr1754209pll.210.1572278299477; Mon, 28 Oct 2019 08:58:19 -0700 (PDT) Received: from localhost ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id d14sm13225525pfh.36.2019.10.28.08.58.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Oct 2019 08:58:18 -0700 (PDT) Subject: [PULL 02/18] RISC-V: Handle bus errors in the page table walker Date: Mon, 28 Oct 2019 08:48:46 -0700 Message-Id: <20191028154902.32491-3-palmer@sifive.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191028154902.32491-1-palmer@sifive.com> References: <20191028154902.32491-1-palmer@sifive.com> MIME-Version: 1.0 From: Palmer Dabbelt To: Peter Maydell X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::641 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, Palmer Dabbelt , Richard Henderson , qemu-devel@nongnu.org, Alistair Francis , ilippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" We directly access physical memory while walking the page tables on RISC-V, but while doing so we were using cpu_ld*() which does not report bus errors. This patch converts the page table walker over to use address_space_ld*(), which allows bus errors to be detected. Signed-off-by: Palmer Dabbelt Signed-off-by: Alistair Francis Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Palmer Dabbelt --- target/riscv/cpu_helper.c | 12 +++++++++--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 87dd6a6ece..c82e7ed52b 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -169,7 +169,8 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical, /* NOTE: the env->pc value visible here will not be * correct, but the value visible to the exception handler * (riscv_cpu_do_interrupt) is correct */ - + MemTxResult res; + MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED; int mode = mmu_idx; if (mode == PRV_M && access_type != MMU_INST_FETCH) { @@ -256,11 +257,16 @@ restart: 1 << MMU_DATA_LOAD, PRV_S)) { return TRANSLATE_PMP_FAIL; } + #if defined(TARGET_RISCV32) - target_ulong pte = ldl_phys(cs->as, pte_addr); + target_ulong pte = address_space_ldl(cs->as, pte_addr, attrs, &res); #elif defined(TARGET_RISCV64) - target_ulong pte = ldq_phys(cs->as, pte_addr); + target_ulong pte = address_space_ldq(cs->as, pte_addr, attrs, &res); #endif + if (res != MEMTX_OK) { + return TRANSLATE_FAIL; + } + hwaddr ppn = pte >> PTE_PPN_SHIFT; if (!(pte & PTE_V)) { From patchwork Mon Oct 28 15:48:47 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Palmer Dabbelt X-Patchwork-Id: 1185563 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=sifive.com header.i=@sifive.com header.b="SvAdebdV"; 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Mon, 28 Oct 2019 08:58:21 -0700 (PDT) Received: from localhost ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id f25sm15812305pfk.10.2019.10.28.08.58.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Oct 2019 08:58:20 -0700 (PDT) Subject: [PULL 03/18] RISC-V: Implement cpu_do_transaction_failed Date: Mon, 28 Oct 2019 08:48:47 -0700 Message-Id: <20191028154902.32491-4-palmer@sifive.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191028154902.32491-1-palmer@sifive.com> References: <20191028154902.32491-1-palmer@sifive.com> MIME-Version: 1.0 From: Palmer Dabbelt To: Peter Maydell X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::444 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, Palmer Dabbelt , Richard Henderson , qemu-devel@nongnu.org, Alistair Francis , ilippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" This converts our port over from cpu_do_unassigned_access to cpu_do_transaction_failed, as cpu_do_unassigned_access has been deprecated. Signed-off-by: Palmer Dabbelt Signed-off-by: Alistair Francis Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Palmer Dabbelt --- target/riscv/cpu.c | 2 +- target/riscv/cpu.h | 7 +++++-- target/riscv/cpu_helper.c | 11 +++++++---- 3 files changed, 13 insertions(+), 7 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index f13e298a36..3939963b71 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -484,7 +484,7 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data) cc->gdb_stop_before_watchpoint = true; cc->disas_set_info = riscv_cpu_disas_set_info; #ifndef CONFIG_USER_ONLY - cc->do_unassigned_access = riscv_cpu_unassigned_access; + cc->do_transaction_failed = riscv_cpu_do_transaction_failed; cc->do_unaligned_access = riscv_cpu_do_unaligned_access; cc->get_phys_page_debug = riscv_cpu_get_phys_page_debug; #endif diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 124ed33ee4..8c64c68538 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -264,8 +264,11 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); -void riscv_cpu_unassigned_access(CPUState *cpu, hwaddr addr, bool is_write, - bool is_exec, int unused, unsigned size); +void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, + vaddr addr, unsigned size, + MMUAccessType access_type, + int mmu_idx, MemTxAttrs attrs, + MemTxResult response, uintptr_t retaddr); char *riscv_isa_string(RISCVCPU *cpu); void riscv_cpu_list(void); diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index c82e7ed52b..917252f71b 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -408,20 +408,23 @@ hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) return phys_addr; } -void riscv_cpu_unassigned_access(CPUState *cs, hwaddr addr, bool is_write, - bool is_exec, int unused, unsigned size) +void riscv_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, + vaddr addr, unsigned size, + MMUAccessType access_type, + int mmu_idx, MemTxAttrs attrs, + MemTxResult response, uintptr_t retaddr) { RISCVCPU *cpu = RISCV_CPU(cs); CPURISCVState *env = &cpu->env; - if (is_write) { + if (access_type == MMU_DATA_STORE) { cs->exception_index = RISCV_EXCP_STORE_AMO_ACCESS_FAULT; } else { cs->exception_index = RISCV_EXCP_LOAD_ACCESS_FAULT; } env->badaddr = addr; - riscv_raise_exception(&cpu->env, cs->exception_index, GETPC()); + riscv_raise_exception(&cpu->env, cs->exception_index, retaddr); } void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, From patchwork Mon Oct 28 15:48:48 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Palmer Dabbelt X-Patchwork-Id: 1185507 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: ozlabs.org; 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Mon, 28 Oct 2019 08:58:23 -0700 (PDT) Received: from localhost ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id i63sm5234094pgc.31.2019.10.28.08.58.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Oct 2019 08:58:22 -0700 (PDT) Subject: [PULL 04/18] riscv: hw: Drop "clock-frequency" property of cpu nodes Date: Mon, 28 Oct 2019 08:48:48 -0700 Message-Id: <20191028154902.32491-5-palmer@sifive.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191028154902.32491-1-palmer@sifive.com> References: <20191028154902.32491-1-palmer@sifive.com> MIME-Version: 1.0 From: Palmer Dabbelt To: Peter Maydell X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::644 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , Bin Meng , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Palmer Dabbelt Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng The "clock-frequency" property of cpu nodes isn't required. Drop it. This is to keep in sync with Linux kernel commit below: https://patchwork.kernel.org/patch/11133031/ Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Signed-off-by: Palmer Dabbelt --- hw/riscv/sifive_u.c | 2 -- hw/riscv/spike.c | 2 -- hw/riscv/virt.c | 2 -- include/hw/riscv/sifive_u.h | 1 - include/hw/riscv/spike.h | 4 ---- include/hw/riscv/virt.h | 4 ---- 6 files changed, 15 deletions(-) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 9f8e84bf2e..02dd76176e 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -151,8 +151,6 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); char *isa; qemu_fdt_add_subnode(fdt, nodename); - qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", - SIFIVE_U_CLOCK_FREQ); /* cpu 0 is the management hart that does not have mmu */ if (cpu != 0) { qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48"); diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index d60415d190..8bbffbcd0f 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -102,8 +102,6 @@ static void create_fdt(SpikeState *s, const struct MemmapEntry *memmap, char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); char *isa = riscv_isa_string(&s->soc.harts[cpu]); qemu_fdt_add_subnode(fdt, nodename); - qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", - SPIKE_CLOCK_FREQ); qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48"); qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa); qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv"); diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index d36f5625ec..13030619d4 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -161,8 +161,6 @@ static void create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap, char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); char *isa = riscv_isa_string(&s->soc.harts[cpu]); qemu_fdt_add_subnode(fdt, nodename); - qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", - VIRT_CLOCK_FREQ); qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48"); qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa); qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv"); diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index e4df298c23..4850805ee7 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -75,7 +75,6 @@ enum { }; enum { - SIFIVE_U_CLOCK_FREQ = 1000000000, SIFIVE_U_HFCLK_FREQ = 33333333, SIFIVE_U_RTCCLK_FREQ = 1000000 }; diff --git a/include/hw/riscv/spike.h b/include/hw/riscv/spike.h index 03d870363c..dc770421bc 100644 --- a/include/hw/riscv/spike.h +++ b/include/hw/riscv/spike.h @@ -38,10 +38,6 @@ enum { SPIKE_DRAM }; -enum { - SPIKE_CLOCK_FREQ = 1000000000 -}; - #if defined(TARGET_RISCV32) #define SPIKE_V1_09_1_CPU TYPE_RISCV_CPU_RV32GCSU_V1_09_1 #define SPIKE_V1_10_0_CPU TYPE_RISCV_CPU_RV32GCSU_V1_10_0 diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h index 6e5fbe5d3b..68978a13e8 100644 --- a/include/hw/riscv/virt.h +++ b/include/hw/riscv/virt.h @@ -55,10 +55,6 @@ enum { VIRTIO_NDEV = 0x35 /* Arbitrary maximum number of interrupts */ }; -enum { - VIRT_CLOCK_FREQ = 1000000000 -}; - #define VIRT_PLIC_HART_CONFIG "MS" #define VIRT_PLIC_NUM_SOURCES 127 #define VIRT_PLIC_NUM_PRIORITIES 7 From patchwork Mon Oct 28 15:48:49 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Palmer Dabbelt X-Patchwork-Id: 1185511 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=sifive.com header.i=@sifive.com header.b="E7Bv8nsz"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 47205H0sW5z9sPK for ; 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Mon, 28 Oct 2019 08:58:24 -0700 (PDT) Received: from localhost ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id i123sm13313009pfe.145.2019.10.28.08.58.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Oct 2019 08:58:24 -0700 (PDT) Subject: [PULL 05/18] riscv: sifive_u: Add ethernet0 to the aliases node Date: Mon, 28 Oct 2019 08:48:49 -0700 Message-Id: <20191028154902.32491-6-palmer@sifive.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191028154902.32491-1-palmer@sifive.com> References: <20191028154902.32491-1-palmer@sifive.com> MIME-Version: 1.0 From: Palmer Dabbelt To: Peter Maydell X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::541 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, Palmer Dabbelt , qemu-devel@nongnu.org, Alistair Francis , Bin Meng , ilippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Bin Meng U-Boot expects this alias to be in place in order to fix up the mac address of the ethernet node. This is to keep in sync with Linux kernel commit below: https://patchwork.kernel.org/patch/11133033/ Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Palmer Dabbelt --- hw/riscv/sifive_u.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 02dd76176e..1ac51e3632 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -270,6 +270,10 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, s->soc.gem.conf.macaddr.a, ETH_ALEN); qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1); qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0); + + qemu_fdt_add_subnode(fdt, "/aliases"); + qemu_fdt_setprop_string(fdt, "/aliases", "ethernet0", nodename); + g_free(nodename); nodename = g_strdup_printf("/soc/ethernet@%lx/ethernet-phy@0", @@ -297,7 +301,6 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline); } - qemu_fdt_add_subnode(fdt, "/aliases"); qemu_fdt_setprop_string(fdt, "/aliases", "serial0", nodename); g_free(nodename); From patchwork Mon Oct 28 15:48:50 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Palmer Dabbelt X-Patchwork-Id: 1185570 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=sifive.com header.i=@sifive.com header.b="YJh3uCNo"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4721CG6ftdz9s7T for ; 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Mon, 28 Oct 2019 08:58:26 -0700 (PDT) Received: from localhost ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id 66sm3855027pgi.49.2019.10.28.08.58.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Oct 2019 08:58:25 -0700 (PDT) Subject: [PULL 06/18] linux-user/riscv: Propagate fault address Date: Mon, 28 Oct 2019 08:48:50 -0700 Message-Id: <20191028154902.32491-7-palmer@sifive.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191028154902.32491-1-palmer@sifive.com> References: <20191028154902.32491-1-palmer@sifive.com> MIME-Version: 1.0 From: Palmer Dabbelt To: Peter Maydell X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::443 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Giuseppe Musacchio , Palmer Dabbelt , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Giuseppe Musacchio The CPU loop tagged all the queued signals as QEMU_SI_KILL while it was filling the `_sigfault` part of `siginfo`: this caused QEMU to copy the wrong fields over to the userspace program. Make sure the fault address recorded by the MMU is is stored in the CPU environment structure. In case of memory faults store the exception address into `siginfo`. Signed-off-by: Giuseppe Musacchio Reviewed-by: Palmer Dabbelt Signed-off-by: Palmer Dabbelt --- linux-user/riscv/cpu_loop.c | 3 ++- target/riscv/cpu_helper.c | 5 ++++- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/linux-user/riscv/cpu_loop.c b/linux-user/riscv/cpu_loop.c index 12aa3c0f16..aa9e437875 100644 --- a/linux-user/riscv/cpu_loop.c +++ b/linux-user/riscv/cpu_loop.c @@ -89,6 +89,7 @@ void cpu_loop(CPURISCVState *env) case RISCV_EXCP_STORE_PAGE_FAULT: signum = TARGET_SIGSEGV; sigcode = TARGET_SEGV_MAPERR; + sigaddr = env->badaddr; break; case EXCP_DEBUG: gdbstep: @@ -108,7 +109,7 @@ void cpu_loop(CPURISCVState *env) .si_code = sigcode, ._sifields._sigfault._addr = sigaddr }; - queue_signal(env, info.si_signo, QEMU_SI_KILL, &info); + queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); } process_pending_signals(env); diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 917252f71b..f13131a51b 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -455,9 +455,9 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr) { -#ifndef CONFIG_USER_ONLY RISCVCPU *cpu = RISCV_CPU(cs); CPURISCVState *env = &cpu->env; +#ifndef CONFIG_USER_ONLY hwaddr pa = 0; int prot; bool pmp_violation = false; @@ -508,7 +508,10 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, case MMU_DATA_STORE: cs->exception_index = RISCV_EXCP_STORE_PAGE_FAULT; break; + default: + g_assert_not_reached(); } + env->badaddr = address; cpu_loop_exit_restore(cs, retaddr); #endif } From patchwork Mon Oct 28 15:48:51 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Palmer Dabbelt X-Patchwork-Id: 1185564 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: ozlabs.org; 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Mon, 28 Oct 2019 08:58:27 -0700 (PDT) Received: from localhost ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id v25sm10646364pfn.78.2019.10.28.08.58.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Oct 2019 08:58:27 -0700 (PDT) Subject: [PULL 07/18] riscv/sifive_u: Add L2-LIM cache memory Date: Mon, 28 Oct 2019 08:48:51 -0700 Message-Id: <20191028154902.32491-8-palmer@sifive.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191028154902.32491-1-palmer@sifive.com> References: <20191028154902.32491-1-palmer@sifive.com> MIME-Version: 1.0 From: Palmer Dabbelt To: Peter Maydell X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::444 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , Bin Meng , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Palmer Dabbelt Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Alistair Francis On reset only a single L2 cache way is enabled, the others are exposed as memory that can be used by early boot firmware. This L2 region is generally disabled using the WayEnable register at a later stage in the boot process. To allow firmware to target QEMU and the HiFive Unleashed let's add the L2 LIM (LooselyIntegrated Memory). Ideally we would want to adjust the size of this chunk of memory as the L2 Cache Controller WayEnable register is incremented. Unfortunately I don't see a nice way to handle reducing or blocking out the L2 LIM while still allowing it be re returned to all enabled from a reset. Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Signed-off-by: Palmer Dabbelt --- hw/riscv/sifive_u.c | 16 ++++++++++++++++ include/hw/riscv/sifive_u.h | 1 + 2 files changed, 17 insertions(+) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 1ac51e3632..fbaa3a234e 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -65,6 +65,7 @@ static const struct MemmapEntry { [SIFIVE_U_DEBUG] = { 0x0, 0x100 }, [SIFIVE_U_MROM] = { 0x1000, 0x11000 }, [SIFIVE_U_CLINT] = { 0x2000000, 0x10000 }, + [SIFIVE_U_L2LIM] = { 0x8000000, 0x2000000 }, [SIFIVE_U_PLIC] = { 0xc000000, 0x4000000 }, [SIFIVE_U_PRCI] = { 0x10000000, 0x1000 }, [SIFIVE_U_UART0] = { 0x10010000, 0x1000 }, @@ -432,6 +433,7 @@ static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp) const struct MemmapEntry *memmap = sifive_u_memmap; MemoryRegion *system_memory = get_system_memory(); MemoryRegion *mask_rom = g_new(MemoryRegion, 1); + MemoryRegion *l2lim_mem = g_new(MemoryRegion, 1); qemu_irq plic_gpios[SIFIVE_U_PLIC_NUM_SOURCES]; char *plic_hart_config; size_t plic_hart_config_len; @@ -460,6 +462,20 @@ static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp) memory_region_add_subregion(system_memory, memmap[SIFIVE_U_MROM].base, mask_rom); + /* + * Add L2-LIM at reset size. + * This should be reduced in size as the L2 Cache Controller WayEnable + * register is incremented. Unfortunately I don't see a nice (or any) way + * to handle reducing or blocking out the L2 LIM while still allowing it + * be re returned to all enabled after a reset. For the time being, just + * leave it enabled all the time. This won't break anything, but will be + * too generous to misbehaving guests. + */ + memory_region_init_ram(l2lim_mem, NULL, "riscv.sifive.u.l2lim", + memmap[SIFIVE_U_L2LIM].size, &error_fatal); + memory_region_add_subregion(system_memory, memmap[SIFIVE_U_L2LIM].base, + l2lim_mem); + /* create PLIC hart topology configuration string */ plic_hart_config_len = (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1) * ms->smp.cpus; diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index 4850805ee7..66ee76a780 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -58,6 +58,7 @@ enum { SIFIVE_U_DEBUG, SIFIVE_U_MROM, SIFIVE_U_CLINT, + SIFIVE_U_L2LIM, SIFIVE_U_PLIC, SIFIVE_U_PRCI, SIFIVE_U_UART0, From patchwork Mon Oct 28 15:48:52 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Palmer Dabbelt X-Patchwork-Id: 1185565 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=sifive.com header.i=@sifive.com header.b="WMzbUqIE"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4720yl451Pz9sPK for ; Tue, 29 Oct 2019 03:48:15 +1100 (AEDT) Received: from localhost ([::1]:59362 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iP8Bg-0001lD-O5 for incoming@patchwork.ozlabs.org; Mon, 28 Oct 2019 12:48:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34719) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iP7Pc-0005Jt-Sk for qemu-devel@nongnu.org; Mon, 28 Oct 2019 11:58:34 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iP7Pb-0003rz-Hx for qemu-devel@nongnu.org; Mon, 28 Oct 2019 11:58:32 -0400 Received: from mail-pg1-x542.google.com ([2607:f8b0:4864:20::542]:42998) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iP7Pb-0003rQ-Ci for qemu-devel@nongnu.org; Mon, 28 Oct 2019 11:58:31 -0400 Received: by mail-pg1-x542.google.com with SMTP id f14so7152375pgi.9 for ; Mon, 28 Oct 2019 08:58:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding:cc:from:to; bh=e7M7/g3Lxi9UwHK1x9XgkX5SPo7otVzIHSY4iLY4NQw=; b=WMzbUqIEG28xpHs6tMe/y+DW0zlwaXdKlHfXv8sJZowe0ki4eerPCVb9XTQ7tLIHkc dKBAl0vhKTr1y9PdXHjbNdwv3ShMUm0sfs80hvbBPjSulHo05HjyTIWDZFVdHEZFtfrB CAznVIdGtvpjNFoMuivYUgEJl1/srbvvZ7VPpKOZfkYRxV8LRknUKbAqLAVOuVCAY/g1 o1dctuHostUthxAHDH6pTqo6x6rggjXXYTYyq3/JmXJvXojWVfMxYCeyrtFIloHtTWsP 8MCDLIjY+wWhpYW29sQ7kupqFh2EVtHB+X2UhCIf8lWcykAztCCT9FU1l56qW6Mm87m+ Fitw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:cc:from:to; bh=e7M7/g3Lxi9UwHK1x9XgkX5SPo7otVzIHSY4iLY4NQw=; b=jcEJRJw1FQjk8uSLhg+MoLUBczLTZeDW2XMSr35gjVYzPpHFm1wGtBXZncu3k99BlS 4KWohJbfsDhK950uBgRVwX2340s4Z+XV/GKqesFz4aWnc2ErDnFSyc1QG5mfoieQS53u m3wLAlq8zI7d/oWLBpNO8RYmc4vef7bsrfH/QCZS74vES7DD5KfQpj6JpA84S+il0Lw+ iUR7dGIo0UkUvbR4zoCFwORSBSB8T2Vu50pXjAZrhyaH9+zywx6ZuQrKMCiUtX2Fi4OE y6iz0TI5rnHGEdfAggYkXm7ogjnkynM/P4wgSQ1R0/KlVfGM+YZqqs3Aeb59OruFB13/ omvw== X-Gm-Message-State: APjAAAUYqYEOuSOpiIEP7xgw4k5yxady/0hh/IO6VGMj6ILaZJeW/81+ 5Gp1UPg654+6YyVj/9NOcaLIgXiFdkLvIQ== X-Google-Smtp-Source: APXvYqzHLJyhtdaSgzal0XpUko9I7J+6wasJrNFWVDwB0l7HmdoDXXNpG8+uLNIOO3QLOsZkAm4Omg== X-Received: by 2002:a63:9543:: with SMTP id t3mr21805496pgn.350.1572278310012; Mon, 28 Oct 2019 08:58:30 -0700 (PDT) Received: from localhost ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id l11sm12942229pgf.73.2019.10.28.08.58.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Oct 2019 08:58:29 -0700 (PDT) Subject: [PULL 08/18] riscv/sifive_u: Add QSPI memory region Date: Mon, 28 Oct 2019 08:48:52 -0700 Message-Id: <20191028154902.32491-9-palmer@sifive.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191028154902.32491-1-palmer@sifive.com> References: <20191028154902.32491-1-palmer@sifive.com> MIME-Version: 1.0 From: Palmer Dabbelt To: Peter Maydell X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::542 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , Bin Meng , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Palmer Dabbelt Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Alistair Francis The HiFive Unleashed uses is25wp256 SPI NOR flash. There is currently no model of this in QEMU, so to allow boot firmware developers to use QEMU to target the Unleashed let's add a chunk of memory to represent the QSPI0 memory mapped flash. This can be targeted using QEMU's -device loader command line option. In the future we can look at adding a model for the is25wp256 flash. Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Signed-off-by: Palmer Dabbelt --- hw/riscv/sifive_u.c | 8 ++++++++ include/hw/riscv/sifive_u.h | 1 + 2 files changed, 9 insertions(+) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index fbaa3a234e..a32d6773a8 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -71,6 +71,7 @@ static const struct MemmapEntry { [SIFIVE_U_UART0] = { 0x10010000, 0x1000 }, [SIFIVE_U_UART1] = { 0x10011000, 0x1000 }, [SIFIVE_U_OTP] = { 0x10070000, 0x1000 }, + [SIFIVE_U_FLASH0] = { 0x20000000, 0x10000000 }, [SIFIVE_U_DRAM] = { 0x80000000, 0x0 }, [SIFIVE_U_GEM] = { 0x10090000, 0x2000 }, [SIFIVE_U_GEM_MGMT] = { 0x100a0000, 0x1000 }, @@ -314,6 +315,7 @@ static void riscv_sifive_u_init(MachineState *machine) SiFiveUState *s = g_new0(SiFiveUState, 1); MemoryRegion *system_memory = get_system_memory(); MemoryRegion *main_mem = g_new(MemoryRegion, 1); + MemoryRegion *flash0 = g_new(MemoryRegion, 1); int i; /* Initialize SoC */ @@ -329,6 +331,12 @@ static void riscv_sifive_u_init(MachineState *machine) memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DRAM].base, main_mem); + /* register QSPI0 Flash */ + memory_region_init_ram(flash0, NULL, "riscv.sifive.u.flash0", + memmap[SIFIVE_U_FLASH0].size, &error_fatal); + memory_region_add_subregion(system_memory, memmap[SIFIVE_U_FLASH0].base, + flash0); + /* create device tree */ create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline); diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index 66ee76a780..0062276190 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -64,6 +64,7 @@ enum { SIFIVE_U_UART0, SIFIVE_U_UART1, SIFIVE_U_OTP, + SIFIVE_U_FLASH0, SIFIVE_U_DRAM, SIFIVE_U_GEM, SIFIVE_U_GEM_MGMT From patchwork Mon Oct 28 15:48:53 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Palmer Dabbelt X-Patchwork-Id: 1185516 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; 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Mon, 28 Oct 2019 08:58:31 -0700 (PDT) Subject: [PULL 09/18] riscv/sifive_u: Manually define the machine Date: Mon, 28 Oct 2019 08:48:53 -0700 Message-Id: <20191028154902.32491-10-palmer@sifive.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191028154902.32491-1-palmer@sifive.com> References: <20191028154902.32491-1-palmer@sifive.com> MIME-Version: 1.0 From: Palmer Dabbelt To: Peter Maydell X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::441 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , Bin Meng , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Palmer Dabbelt Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Alistair Francis Instead of using the DEFINE_MACHINE() macro to define the machine let's do it manually. This allows us to specify machine properties. This patch is no functional change. Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Tested-by: Bin Meng Signed-off-by: Palmer Dabbelt --- hw/riscv/sifive_u.c | 44 ++++++++++++++++++++++++++----------- include/hw/riscv/sifive_u.h | 7 +++++- 2 files changed, 37 insertions(+), 14 deletions(-) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index a32d6773a8..eb4124f5b4 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -311,8 +311,7 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, static void riscv_sifive_u_init(MachineState *machine) { const struct MemmapEntry *memmap = sifive_u_memmap; - - SiFiveUState *s = g_new0(SiFiveUState, 1); + SiFiveUState *s = RISCV_U_MACHINE(machine); MemoryRegion *system_memory = get_system_memory(); MemoryRegion *main_mem = g_new(MemoryRegion, 1); MemoryRegion *flash0 = g_new(MemoryRegion, 1); @@ -434,6 +433,10 @@ static void riscv_sifive_u_soc_init(Object *obj) TYPE_CADENCE_GEM); } +static void riscv_sifive_u_machine_instance_init(Object *obj) +{ +} + static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp) { MachineState *ms = MACHINE(qdev_get_machine()); @@ -547,17 +550,6 @@ static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp) memmap[SIFIVE_U_GEM_MGMT].base, memmap[SIFIVE_U_GEM_MGMT].size); } -static void riscv_sifive_u_machine_init(MachineClass *mc) -{ - mc->desc = "RISC-V Board compatible with SiFive U SDK"; - mc->init = riscv_sifive_u_init; - mc->max_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + SIFIVE_U_COMPUTE_CPU_COUNT; - mc->min_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + 1; - mc->default_cpus = mc->min_cpus; -} - -DEFINE_MACHINE("sifive_u", riscv_sifive_u_machine_init) - static void riscv_sifive_u_soc_class_init(ObjectClass *oc, void *data) { DeviceClass *dc = DEVICE_CLASS(oc); @@ -581,3 +573,29 @@ static void riscv_sifive_u_soc_register_types(void) } type_init(riscv_sifive_u_soc_register_types) + +static void riscv_sifive_u_machine_class_init(ObjectClass *oc, void *data) +{ + MachineClass *mc = MACHINE_CLASS(oc); + + mc->desc = "RISC-V Board compatible with SiFive U SDK"; + mc->init = riscv_sifive_u_init; + mc->max_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + SIFIVE_U_COMPUTE_CPU_COUNT; + mc->min_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + 1; + mc->default_cpus = mc->min_cpus; +} + +static const TypeInfo riscv_sifive_u_machine_typeinfo = { + .name = MACHINE_TYPE_NAME("sifive_u"), + .parent = TYPE_MACHINE, + .class_init = riscv_sifive_u_machine_class_init, + .instance_init = riscv_sifive_u_machine_instance_init, + .instance_size = sizeof(SiFiveUState), +}; + +static void riscv_sifive_u_machine_init_register_types(void) +{ + type_register_static(&riscv_sifive_u_machine_typeinfo); +} + +type_init(riscv_sifive_u_machine_init_register_types) diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index 0062276190..794b958dcc 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -44,12 +44,17 @@ typedef struct SiFiveUSoCState { CadenceGEMState gem; } SiFiveUSoCState; +#define TYPE_RISCV_U_MACHINE MACHINE_TYPE_NAME("sifive_u") +#define RISCV_U_MACHINE(obj) \ + OBJECT_CHECK(SiFiveUState, (obj), TYPE_RISCV_U_MACHINE) + typedef struct SiFiveUState { /*< private >*/ - SysBusDevice parent_obj; + MachineState parent_obj; /*< public >*/ SiFiveUSoCState soc; + void *fdt; int fdt_size; } SiFiveUState; From patchwork Mon Oct 28 15:48:54 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Palmer Dabbelt X-Patchwork-Id: 1185568 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=sifive.com header.i=@sifive.com header.b="F8jCX7JZ"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4721601y2yz9sPK for ; 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Mon, 28 Oct 2019 08:58:34 -0700 (PDT) Received: from localhost ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id a6sm11595869pfn.99.2019.10.28.08.58.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Oct 2019 08:58:33 -0700 (PDT) Subject: [PULL 10/18] riscv/sifive_u: Add the start-in-flash property Date: Mon, 28 Oct 2019 08:48:54 -0700 Message-Id: <20191028154902.32491-11-palmer@sifive.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191028154902.32491-1-palmer@sifive.com> References: <20191028154902.32491-1-palmer@sifive.com> MIME-Version: 1.0 From: Palmer Dabbelt To: Peter Maydell X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::633 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , Bin Meng , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Palmer Dabbelt Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Alistair Francis Add a property that when set to true QEMU will jump from the ROM code to the start of flash memory instead of DRAM which is the default behaviour. Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Tested-by: Bin Meng Signed-off-by: Palmer Dabbelt --- hw/riscv/sifive_u.c | 30 +++++++++++++++++++++++++++++- include/hw/riscv/sifive_u.h | 2 ++ 2 files changed, 31 insertions(+), 1 deletion(-) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index eb4124f5b4..9552abf4dd 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -315,6 +315,7 @@ static void riscv_sifive_u_init(MachineState *machine) MemoryRegion *system_memory = get_system_memory(); MemoryRegion *main_mem = g_new(MemoryRegion, 1); MemoryRegion *flash0 = g_new(MemoryRegion, 1); + target_ulong start_addr = memmap[SIFIVE_U_DRAM].base; int i; /* Initialize SoC */ @@ -357,6 +358,10 @@ static void riscv_sifive_u_init(MachineState *machine) } } + if (s->start_in_flash) { + start_addr = memmap[SIFIVE_U_FLASH0].base; + } + /* reset vector */ uint32_t reset_vec[8] = { 0x00000297, /* 1: auipc t0, %pcrel_hi(dtb) */ @@ -369,7 +374,7 @@ static void riscv_sifive_u_init(MachineState *machine) #endif 0x00028067, /* jr t0 */ 0x00000000, - memmap[SIFIVE_U_DRAM].base, /* start: .dword DRAM_BASE */ + start_addr, /* start: .dword */ 0x00000000, /* dtb: */ }; @@ -433,8 +438,31 @@ static void riscv_sifive_u_soc_init(Object *obj) TYPE_CADENCE_GEM); } +static bool sifive_u_get_start_in_flash(Object *obj, Error **errp) +{ + SiFiveUState *s = RISCV_U_MACHINE(obj); + + return s->start_in_flash; +} + +static void sifive_u_set_start_in_flash(Object *obj, bool value, Error **errp) +{ + SiFiveUState *s = RISCV_U_MACHINE(obj); + + s->start_in_flash = value; +} + static void riscv_sifive_u_machine_instance_init(Object *obj) { + SiFiveUState *s = RISCV_U_MACHINE(obj); + + s->start_in_flash = false; + object_property_add_bool(obj, "start-in-flash", sifive_u_get_start_in_flash, + sifive_u_set_start_in_flash, NULL); + object_property_set_description(obj, "start-in-flash", + "Set on to tell QEMU's ROM to jump to " \ + "flash. Otherwise QEMU will jump to DRAM", + NULL); } static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp) diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index 794b958dcc..82667b5746 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -57,6 +57,8 @@ typedef struct SiFiveUState { void *fdt; int fdt_size; + + bool start_in_flash; } SiFiveUState; enum { From patchwork Mon Oct 28 15:48:55 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Palmer Dabbelt X-Patchwork-Id: 1185574 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=sifive.com header.i=@sifive.com header.b="JXDOeJUW"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4721Dh039mz9s7T for ; Tue, 29 Oct 2019 04:00:18 +1100 (AEDT) Received: from localhost ([::1]:60700 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iP8NL-0001S9-TG for incoming@patchwork.ozlabs.org; Mon, 28 Oct 2019 13:00:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34831) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iP7Pk-0005X7-03 for qemu-devel@nongnu.org; Mon, 28 Oct 2019 11:58:41 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iP7Pi-0003xk-JD for qemu-devel@nongnu.org; Mon, 28 Oct 2019 11:58:39 -0400 Received: from mail-pl1-x62b.google.com ([2607:f8b0:4864:20::62b]:45639) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iP7Pi-0003wv-Ds for qemu-devel@nongnu.org; Mon, 28 Oct 2019 11:58:38 -0400 Received: by mail-pl1-x62b.google.com with SMTP id y24so5768796plr.12 for ; Mon, 28 Oct 2019 08:58:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding:cc:from:to; bh=37C4bJsqwTYJDhkHJBdMxhyCv+2so2gtmom4EOj9zjo=; b=JXDOeJUWYhMycj2BTvOKus1X4Ik0jtZ7jbj+pPkWeYEvoGwTcUASClHKuIdVLhRRM6 jqXq37jvmaQImZs1LH6l7CBEVkabWfTYeCgKYEU/o/+kQsqm/hEsleynUh8XQSnqdbdd jpmFgm3ArOFo7n2YwlOh6CpSe7XRIKYdKm4Mo0NquDbDAkXYGcjaB89Ez/d53qlJPiC2 OGHxrXS/pi6195SKGCX25qyhPNg07l5xajakrTyEhvvY1/nyuMWdpjD8wc5E/EH9K333 WCRBo7A/djIOIioALyvxKUOGg5tWBeiS3nEsHcdomzPA6h8D9zlfwmzQ3vm8sna9At9k tBvg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:cc:from:to; bh=37C4bJsqwTYJDhkHJBdMxhyCv+2so2gtmom4EOj9zjo=; b=Ql63bm3PYrXYyDbDe28i9Pfp6rlh4IdPR/7oTHVRGLVvvH9xnkgRnsfQr696tj1VKn Hie6t3gIhIlsgBHV7j4ihOezv7kxXnSf4got3hQLTuj/QLbsYR/SVabZb6fpJWkqm6qS +vUdLI3D+OWbHvYuqpYraLGKMZy88pMjKXsQc94mIqSvox8bu0ySjSY0gWsxVpdLaUba uop1vEk2snppJ2uWkRUXmRocc4ulugLZ/u/OpaJvbp2tQ/Og9sxWmJ0aLUs6wgRgK0+u ImGGNM2QD48f6XWzW6TyBkTJcytcJFIyb5K75g3bvjEYeMGV8zdE7UfdhiMHTCCMWE/5 VjZg== X-Gm-Message-State: APjAAAWwVxJ46/UlXuWwJBodLOK23ctI3DOuY7iCfm969zPhb/AFO9BZ Up1hlUO6UeSicXSyAbJ6RCtsM6ZgTAZ4eQ== X-Google-Smtp-Source: APXvYqx0HXMw+WJ11vbGgtsG9Kubu3dUa5iE8U1RoUZGeEDgjuai8CtjCKDtjbHW8wjaOjeLZLK0mw== X-Received: by 2002:a17:902:347:: with SMTP id 65mr19256786pld.161.1572278317026; Mon, 28 Oct 2019 08:58:37 -0700 (PDT) Received: from localhost ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id s23sm11125289pgh.21.2019.10.28.08.58.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Oct 2019 08:58:36 -0700 (PDT) Subject: [PULL 11/18] riscv/virt: Manually define the machine Date: Mon, 28 Oct 2019 08:48:55 -0700 Message-Id: <20191028154902.32491-12-palmer@sifive.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191028154902.32491-1-palmer@sifive.com> References: <20191028154902.32491-1-palmer@sifive.com> MIME-Version: 1.0 From: Palmer Dabbelt To: Peter Maydell X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::62b X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , Bin Meng , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Palmer Dabbelt Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Alistair Francis Instead of using the DEFINE_MACHINE() macro to define the machine let's do it manually. This allows us to use the machine object to create RISCVVirtState. This is required to add children and aliases to the machine. This patch is no functional change. Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Tested-by: Bin Meng Signed-off-by: Palmer Dabbelt --- hw/riscv/virt.c | 30 ++++++++++++++++++++++++------ include/hw/riscv/virt.h | 7 ++++++- 2 files changed, 30 insertions(+), 7 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 13030619d4..bdbdfadd29 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -360,8 +360,7 @@ static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem, static void riscv_virt_board_init(MachineState *machine) { const struct MemmapEntry *memmap = virt_memmap; - - RISCVVirtState *s = g_new0(RISCVVirtState, 1); + RISCVVirtState *s = RISCV_VIRT_MACHINE(machine); MemoryRegion *system_memory = get_system_memory(); MemoryRegion *main_mem = g_new(MemoryRegion, 1); MemoryRegion *mask_rom = g_new(MemoryRegion, 1); @@ -497,12 +496,31 @@ static void riscv_virt_board_init(MachineState *machine) g_free(plic_hart_config); } -static void riscv_virt_board_machine_init(MachineClass *mc) +static void riscv_virt_machine_instance_init(Object *obj) { - mc->desc = "RISC-V VirtIO Board (Privileged ISA v1.10)"; +} + +static void riscv_virt_machine_class_init(ObjectClass *oc, void *data) +{ + MachineClass *mc = MACHINE_CLASS(oc); + + mc->desc = "RISC-V VirtIO board"; mc->init = riscv_virt_board_init; - mc->max_cpus = 8; /* hardcoded limit in BBL */ + mc->max_cpus = 8; mc->default_cpu_type = VIRT_CPU; } -DEFINE_MACHINE("virt", riscv_virt_board_machine_init) +static const TypeInfo riscv_virt_machine_typeinfo = { + .name = MACHINE_TYPE_NAME("virt"), + .parent = TYPE_MACHINE, + .class_init = riscv_virt_machine_class_init, + .instance_init = riscv_virt_machine_instance_init, + .instance_size = sizeof(RISCVVirtState), +}; + +static void riscv_virt_machine_init_register_types(void) +{ + type_register_static(&riscv_virt_machine_typeinfo); +} + +type_init(riscv_virt_machine_init_register_types) diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h index 68978a13e8..3d875305d3 100644 --- a/include/hw/riscv/virt.h +++ b/include/hw/riscv/virt.h @@ -22,13 +22,18 @@ #include "hw/riscv/riscv_hart.h" #include "hw/sysbus.h" +#define TYPE_RISCV_VIRT_MACHINE MACHINE_TYPE_NAME("virt") +#define RISCV_VIRT_MACHINE(obj) \ + OBJECT_CHECK(RISCVVirtState, (obj), TYPE_RISCV_VIRT_MACHINE) + typedef struct { /*< private >*/ - SysBusDevice parent_obj; + MachineState parent; /*< public >*/ RISCVHartArrayState soc; DeviceState *plic; + void *fdt; int fdt_size; } RISCVVirtState; From patchwork Mon Oct 28 15:48:56 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Palmer Dabbelt X-Patchwork-Id: 1185577 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=sifive.com header.i=@sifive.com header.b="lKcUFegv"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4721NP5LcTz9sP3 for ; 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Mon, 28 Oct 2019 08:58:38 -0700 (PDT) Received: from localhost ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id u36sm13047761pgn.29.2019.10.28.08.58.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Oct 2019 08:58:37 -0700 (PDT) Subject: [PULL 12/18] riscv/virt: Add the PFlash CFI01 device Date: Mon, 28 Oct 2019 08:48:56 -0700 Message-Id: <20191028154902.32491-13-palmer@sifive.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191028154902.32491-1-palmer@sifive.com> References: <20191028154902.32491-1-palmer@sifive.com> MIME-Version: 1.0 From: Palmer Dabbelt To: Peter Maydell X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::544 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , Bin Meng , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Palmer Dabbelt Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Alistair Francis Add the CFI01 PFlash to the RISC-V virt board. This is the same PFlash from the ARM Virt board and the implementation is based on the ARM Virt board. This allows users to specify flash files from the command line. Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Tested-by: Bin Meng Signed-off-by: Palmer Dabbelt --- hw/riscv/Kconfig | 1 + hw/riscv/virt.c | 86 +++++++++++++++++++++++++++++++++++++++++ include/hw/riscv/virt.h | 3 ++ 3 files changed, 90 insertions(+) diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig index fb19b2df3a..b12660b9f8 100644 --- a/hw/riscv/Kconfig +++ b/hw/riscv/Kconfig @@ -36,4 +36,5 @@ config RISCV_VIRT select SERIAL select VIRTIO_MMIO select PCI_EXPRESS_GENERIC_BRIDGE + select PFLASH_CFI01 select SIFIVE diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index bdbdfadd29..b2156abd6c 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -26,6 +26,7 @@ #include "hw/boards.h" #include "hw/loader.h" #include "hw/sysbus.h" +#include "hw/qdev-properties.h" #include "hw/char/serial.h" #include "target/riscv/cpu.h" #include "hw/riscv/riscv_hart.h" @@ -61,12 +62,77 @@ static const struct MemmapEntry { [VIRT_PLIC] = { 0xc000000, 0x4000000 }, [VIRT_UART0] = { 0x10000000, 0x100 }, [VIRT_VIRTIO] = { 0x10001000, 0x1000 }, + [VIRT_FLASH] = { 0x20000000, 0x2000000 }, [VIRT_DRAM] = { 0x80000000, 0x0 }, [VIRT_PCIE_MMIO] = { 0x40000000, 0x40000000 }, [VIRT_PCIE_PIO] = { 0x03000000, 0x00010000 }, [VIRT_PCIE_ECAM] = { 0x30000000, 0x10000000 }, }; +#define VIRT_FLASH_SECTOR_SIZE (256 * KiB) + +static PFlashCFI01 *virt_flash_create1(RISCVVirtState *s, + const char *name, + const char *alias_prop_name) +{ + /* + * Create a single flash device. We use the same parameters as + * the flash devices on the ARM virt board. + */ + DeviceState *dev = qdev_create(NULL, TYPE_PFLASH_CFI01); + + qdev_prop_set_uint64(dev, "sector-length", VIRT_FLASH_SECTOR_SIZE); + qdev_prop_set_uint8(dev, "width", 4); + qdev_prop_set_uint8(dev, "device-width", 2); + qdev_prop_set_bit(dev, "big-endian", false); + qdev_prop_set_uint16(dev, "id0", 0x89); + qdev_prop_set_uint16(dev, "id1", 0x18); + qdev_prop_set_uint16(dev, "id2", 0x00); + qdev_prop_set_uint16(dev, "id3", 0x00); + qdev_prop_set_string(dev, "name", name); + + object_property_add_child(OBJECT(s), name, OBJECT(dev), + &error_abort); + object_property_add_alias(OBJECT(s), alias_prop_name, + OBJECT(dev), "drive", &error_abort); + + return PFLASH_CFI01(dev); +} + +static void virt_flash_create(RISCVVirtState *s) +{ + s->flash[0] = virt_flash_create1(s, "virt.flash0", "pflash0"); + s->flash[1] = virt_flash_create1(s, "virt.flash1", "pflash1"); +} + +static void virt_flash_map1(PFlashCFI01 *flash, + hwaddr base, hwaddr size, + MemoryRegion *sysmem) +{ + DeviceState *dev = DEVICE(flash); + + assert(size % VIRT_FLASH_SECTOR_SIZE == 0); + assert(size / VIRT_FLASH_SECTOR_SIZE <= UINT32_MAX); + qdev_prop_set_uint32(dev, "num-blocks", size / VIRT_FLASH_SECTOR_SIZE); + qdev_init_nofail(dev); + + memory_region_add_subregion(sysmem, base, + sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), + 0)); +} + +static void virt_flash_map(RISCVVirtState *s, + MemoryRegion *sysmem) +{ + hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2; + hwaddr flashbase = virt_memmap[VIRT_FLASH].base; + + virt_flash_map1(s->flash[0], flashbase, flashsize, + sysmem); + virt_flash_map1(s->flash[1], flashbase + flashsize, flashsize, + sysmem); +} + static void create_pcie_irq_map(void *fdt, char *nodename, uint32_t plic_phandle) { @@ -121,6 +187,8 @@ static void create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap, char *nodename; uint32_t plic_phandle, phandle = 1; int i; + hwaddr flashsize = virt_memmap[VIRT_FLASH].size / 2; + hwaddr flashbase = virt_memmap[VIRT_FLASH].base; fdt = s->fdt = create_device_tree(&s->fdt_size); if (!fdt) { @@ -314,6 +382,15 @@ static void create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap, qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline); } g_free(nodename); + + nodename = g_strdup_printf("/flash@%" PRIx64, flashbase); + qemu_fdt_add_subnode(s->fdt, nodename); + qemu_fdt_setprop_string(s->fdt, nodename, "compatible", "cfi-flash"); + qemu_fdt_setprop_sized_cells(s->fdt, nodename, "reg", + 2, flashbase, 2, flashsize, + 2, flashbase + flashsize, 2, flashsize); + qemu_fdt_setprop_cell(s->fdt, nodename, "bank-width", 4); + g_free(nodename); } @@ -493,6 +570,15 @@ static void riscv_virt_board_init(MachineState *machine) 0, qdev_get_gpio_in(DEVICE(s->plic), UART0_IRQ), 399193, serial_hd(0), DEVICE_LITTLE_ENDIAN); + virt_flash_create(s); + + for (i = 0; i < ARRAY_SIZE(s->flash); i++) { + /* Map legacy -drive if=pflash to machine properties */ + pflash_cfi01_legacy_drive(s->flash[i], + drive_get(IF_PFLASH, 0, i)); + } + virt_flash_map(s, system_memory); + g_free(plic_hart_config); } diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h index 3d875305d3..b17048a93a 100644 --- a/include/hw/riscv/virt.h +++ b/include/hw/riscv/virt.h @@ -21,6 +21,7 @@ #include "hw/riscv/riscv_hart.h" #include "hw/sysbus.h" +#include "hw/block/flash.h" #define TYPE_RISCV_VIRT_MACHINE MACHINE_TYPE_NAME("virt") #define RISCV_VIRT_MACHINE(obj) \ @@ -33,6 +34,7 @@ typedef struct { /*< public >*/ RISCVHartArrayState soc; DeviceState *plic; + PFlashCFI01 *flash[2]; void *fdt; int fdt_size; @@ -46,6 +48,7 @@ enum { VIRT_PLIC, VIRT_UART0, VIRT_VIRTIO, + VIRT_FLASH, VIRT_DRAM, VIRT_PCIE_MMIO, VIRT_PCIE_PIO, From patchwork Mon Oct 28 15:48:57 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Palmer Dabbelt X-Patchwork-Id: 1185566 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; 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Mon, 28 Oct 2019 08:58:39 -0700 (PDT) Subject: [PULL 13/18] riscv/virt: Jump to pflash if specified Date: Mon, 28 Oct 2019 08:48:57 -0700 Message-Id: <20191028154902.32491-14-palmer@sifive.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191028154902.32491-1-palmer@sifive.com> References: <20191028154902.32491-1-palmer@sifive.com> MIME-Version: 1.0 From: Palmer Dabbelt To: Peter Maydell X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::543 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, Palmer Dabbelt , qemu-devel@nongnu.org, Alistair Francis , Bin Meng , ilippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Alistair Francis If the user supplied pflash to QEMU then change the reset code to jump to the pflash base address instead of the DRAM base address. Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Reviewed-by: Philippe Mathieu-Daudé Tested-by: Bin Meng Signed-off-by: Palmer Dabbelt --- hw/riscv/virt.c | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index b2156abd6c..cc8f311e6b 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -443,6 +443,7 @@ static void riscv_virt_board_init(MachineState *machine) MemoryRegion *mask_rom = g_new(MemoryRegion, 1); char *plic_hart_config; size_t plic_hart_config_len; + target_ulong start_addr = memmap[VIRT_DRAM].base; int i; unsigned int smp_cpus = machine->smp.cpus; @@ -489,6 +490,14 @@ static void riscv_virt_board_init(MachineState *machine) } } + if (drive_get(IF_PFLASH, 0, 0)) { + /* + * Pflash was supplied, let's overwrite the address we jump to after + * reset to the base of the flash. + */ + start_addr = virt_memmap[VIRT_FLASH].base; + } + /* reset vector */ uint32_t reset_vec[8] = { 0x00000297, /* 1: auipc t0, %pcrel_hi(dtb) */ @@ -501,7 +510,7 @@ static void riscv_virt_board_init(MachineState *machine) #endif 0x00028067, /* jr t0 */ 0x00000000, - memmap[VIRT_DRAM].base, /* start: .dword memmap[VIRT_DRAM].base */ + start_addr, /* start: .dword */ 0x00000000, /* dtb: */ }; From patchwork Mon Oct 28 15:48:58 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Palmer Dabbelt X-Patchwork-Id: 1185520 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=sifive.com header.i=@sifive.com header.b="kTSzec3d"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4720N46G3xz9sPK for ; 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Mon, 28 Oct 2019 08:58:41 -0700 (PDT) Received: from localhost ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id r81sm12836029pgr.17.2019.10.28.08.58.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Oct 2019 08:58:40 -0700 (PDT) Subject: [PULL 14/18] target/riscv: Tell gdbstub the correct number of CSRs Date: Mon, 28 Oct 2019 08:48:58 -0700 Message-Id: <20191028154902.32491-15-palmer@sifive.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191028154902.32491-1-palmer@sifive.com> References: <20191028154902.32491-1-palmer@sifive.com> MIME-Version: 1.0 From: Palmer Dabbelt To: Peter Maydell X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::436 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, Jonathan Behrens , Palmer Dabbelt , qemu-devel@nongnu.org, Alistair Francis , Bin Meng Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Jonathan Behrens If the number of registers reported to the gdbstub code does not match the number in the associated XML file, then the register numbers used by the stub may get out of sync with a remote GDB instance. Signed-off-by: Jonathan Behrens Reviewed-by: Bin Meng Reviewed-by: Alistair Francis Signed-off-by: Palmer Dabbelt --- target/riscv/gdbstub.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index ded140e8d8..cb5bfd3d50 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -384,7 +384,7 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs) } gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr, - 4096, "riscv-32bit-csr.xml", 0); + 240, "riscv-32bit-csr.xml", 0); #elif defined(TARGET_RISCV64) if (env->misa & RVF) { gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu, @@ -392,6 +392,6 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs) } gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr, - 4096, "riscv-64bit-csr.xml", 0); + 240, "riscv-64bit-csr.xml", 0); #endif } From patchwork Mon Oct 28 15:48:59 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Palmer Dabbelt X-Patchwork-Id: 1185576 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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Mon, 28 Oct 2019 08:58:42 -0700 (PDT) Subject: [PULL 15/18] target/riscv: Expose "priv" register for GDB for reads Date: Mon, 28 Oct 2019 08:48:59 -0700 Message-Id: <20191028154902.32491-16-palmer@sifive.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191028154902.32491-1-palmer@sifive.com> References: <20191028154902.32491-1-palmer@sifive.com> MIME-Version: 1.0 From: Palmer Dabbelt To: Peter Maydell X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::432 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, Jonathan Behrens , Palmer Dabbelt , qemu-devel@nongnu.org, Alistair Francis , Bin Meng Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Jonathan Behrens This patch enables a debugger to read the current privilege level via a virtual "priv" register. When compiled with CONFIG_USER_ONLY the register is still visible but always reports the value zero. Signed-off-by: Jonathan Behrens Reviewed-by: Alistair Francis Reviewed-by: Bin Meng Tested-by: Bin Meng Signed-off-by: Palmer Dabbelt --- configure | 4 ++-- gdb-xml/riscv-32bit-virtual.xml | 11 +++++++++++ gdb-xml/riscv-64bit-virtual.xml | 11 +++++++++++ target/riscv/gdbstub.c | 23 +++++++++++++++++++++++ 4 files changed, 47 insertions(+), 2 deletions(-) create mode 100644 gdb-xml/riscv-32bit-virtual.xml create mode 100644 gdb-xml/riscv-64bit-virtual.xml diff --git a/configure b/configure index 145fcabbb3..dc94026a3c 100755 --- a/configure +++ b/configure @@ -7526,13 +7526,13 @@ case "$target_name" in TARGET_BASE_ARCH=riscv TARGET_ABI_DIR=riscv mttcg=yes - gdb_xml_files="riscv-32bit-cpu.xml riscv-32bit-fpu.xml riscv-32bit-csr.xml" + gdb_xml_files="riscv-32bit-cpu.xml riscv-32bit-fpu.xml riscv-32bit-csr.xml riscv-32bit-virtual.xml" ;; riscv64) TARGET_BASE_ARCH=riscv TARGET_ABI_DIR=riscv mttcg=yes - gdb_xml_files="riscv-64bit-cpu.xml riscv-64bit-fpu.xml riscv-64bit-csr.xml" + gdb_xml_files="riscv-64bit-cpu.xml riscv-64bit-fpu.xml riscv-64bit-csr.xml riscv-64bit-virtual.xml" ;; sh4|sh4eb) TARGET_ARCH=sh4 diff --git a/gdb-xml/riscv-32bit-virtual.xml b/gdb-xml/riscv-32bit-virtual.xml new file mode 100644 index 0000000000..905f1c555d --- /dev/null +++ b/gdb-xml/riscv-32bit-virtual.xml @@ -0,0 +1,11 @@ + + + + + + + diff --git a/gdb-xml/riscv-64bit-virtual.xml b/gdb-xml/riscv-64bit-virtual.xml new file mode 100644 index 0000000000..62d86c237b --- /dev/null +++ b/gdb-xml/riscv-64bit-virtual.xml @@ -0,0 +1,11 @@ + + + + + + + diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index cb5bfd3d50..1f71604b78 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -373,6 +373,23 @@ static int riscv_gdb_set_csr(CPURISCVState *env, uint8_t *mem_buf, int n) return 0; } +static int riscv_gdb_get_virtual(CPURISCVState *cs, uint8_t *mem_buf, int n) +{ + if (n == 0) { +#ifdef CONFIG_USER_ONLY + return gdb_get_regl(mem_buf, 0); +#else + return gdb_get_regl(mem_buf, cs->priv); +#endif + } + return 0; +} + +static int riscv_gdb_set_virtual(CPURISCVState *cs, uint8_t *mem_buf, int n) +{ + return 0; +} + void riscv_cpu_register_gdb_regs_for_features(CPUState *cs) { RISCVCPU *cpu = RISCV_CPU(cs); @@ -385,6 +402,9 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs) gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr, 240, "riscv-32bit-csr.xml", 0); + + gdb_register_coprocessor(cs, riscv_gdb_get_virtual, riscv_gdb_set_virtual, + 1, "riscv-32bit-virtual.xml", 0); #elif defined(TARGET_RISCV64) if (env->misa & RVF) { gdb_register_coprocessor(cs, riscv_gdb_get_fpu, riscv_gdb_set_fpu, @@ -393,5 +413,8 @@ void riscv_cpu_register_gdb_regs_for_features(CPUState *cs) gdb_register_coprocessor(cs, riscv_gdb_get_csr, riscv_gdb_set_csr, 240, "riscv-64bit-csr.xml", 0); + + gdb_register_coprocessor(cs, riscv_gdb_get_virtual, riscv_gdb_set_virtual, + 1, "riscv-64bit-virtual.xml", 0); #endif } From patchwork Mon Oct 28 15:49:00 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Palmer Dabbelt X-Patchwork-Id: 1185526 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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Mon, 28 Oct 2019 08:58:44 -0700 (PDT) Subject: [PULL 16/18] target/riscv: Make the priv register writable by GDB Date: Mon, 28 Oct 2019 08:49:00 -0700 Message-Id: <20191028154902.32491-17-palmer@sifive.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191028154902.32491-1-palmer@sifive.com> References: <20191028154902.32491-1-palmer@sifive.com> MIME-Version: 1.0 From: Palmer Dabbelt To: Peter Maydell X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::544 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, Jonathan Behrens , Palmer Dabbelt , qemu-devel@nongnu.org, Alistair Francis , Bin Meng Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Jonathan Behrens Currently only PRV_U, PRV_S and PRV_M are supported, so this patch ensures that the privilege mode is set to one of them. Once support for the H-extension is added, this code will also need to properly update the virtualization status when switching between VU/VS-modes and M-mode. Signed-off-by: Jonathan Behrens Reviewed-by: Bin Meng Tested-by: Bin Meng Reviewed-by: Alistair Francis Signed-off-by: Palmer Dabbelt --- target/riscv/gdbstub.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index 1f71604b78..1a7947e019 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -387,6 +387,15 @@ static int riscv_gdb_get_virtual(CPURISCVState *cs, uint8_t *mem_buf, int n) static int riscv_gdb_set_virtual(CPURISCVState *cs, uint8_t *mem_buf, int n) { + if (n == 0) { +#ifndef CONFIG_USER_ONLY + cs->priv = ldtul_p(mem_buf) & 0x3; + if (cs->priv == PRV_H) { + cs->priv = PRV_S; + } +#endif + return sizeof(target_ulong); + } return 0; } From patchwork Mon Oct 28 15:49:01 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Palmer Dabbelt X-Patchwork-Id: 1185579 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=sifive.com header.i=@sifive.com header.b="REX1WUoN"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4721Vt4YdLz9sPK for ; Tue, 29 Oct 2019 04:12:38 +1100 (AEDT) Received: from localhost ([::1]:33156 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iP8ZH-0004u7-G0 for incoming@patchwork.ozlabs.org; Mon, 28 Oct 2019 13:12:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34978) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iP7Pt-0005pp-81 for qemu-devel@nongnu.org; Mon, 28 Oct 2019 11:58:50 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iP7Pr-000468-Hi for qemu-devel@nongnu.org; Mon, 28 Oct 2019 11:58:48 -0400 Received: from mail-pf1-x441.google.com ([2607:f8b0:4864:20::441]:46416) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iP7Pr-00045Z-CY for qemu-devel@nongnu.org; Mon, 28 Oct 2019 11:58:47 -0400 Received: by mail-pf1-x441.google.com with SMTP id b25so7136501pfi.13 for ; Mon, 28 Oct 2019 08:58:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=sifive.com; s=google; h=subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding:cc:from:to; bh=B4DzWJmRClZnGWtF1qIJV4FygyaOxQSP++ywZKquvFY=; b=REX1WUoNliqFnVDLbWcSAI0HkPLKE7LIwfHXecIbHCYQfPUoGR5mTG1K7ylgS14BWH IsDj/4rjWozlR7PYQL6O+kXEEbo2bLEYXI2geYiJV2XD8gyEBRlgn72aQTEORi9R5Xxm ei67dasHslcUMaAtBd4m+Of77M3iq3iNjVPnEdccmIyrQ0kVfhzyyGuzrMXlDEClJ4+z 4ckEvJtdMKRIQEeiBwdg7PMz6YqyynpGjK/o9xe/UEeX2za5Nixv5dPr7bitLHYmJKGx UrXcOAQVTLeVeL61gvNHnlNGeh/Xnzt2jRyfALT9OtLyAQZF9SWSuELjfTu/lY01h5zi eJbA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding:cc:from:to; bh=B4DzWJmRClZnGWtF1qIJV4FygyaOxQSP++ywZKquvFY=; b=J/bJ7GuoaK1jo6SWjpVTNlnaX5bq9jMQiKdPFs+EEM4NOg0xfmYmNkP377qcriagHO Hi3MsQuI/433SiE8YLZjODBV40q2/zPSyAvfz2SjeTRevfF+rO8K6mGsyfAwAACJubDS tMvSdumFwLo24Ij6KX9Wps1EPqS7rMSiFHbScDNTxsO5+/f2Nb5w7IFHovoHvJb1lqYY +8/zKiUawKYkvF5cHfb5/1LTpamCn/OWrGk2pFZZPaV018M1GatCTk3kI66Y3s6xveul 8HRytp5c9DEeapkNHNePhxd9sERydEDwa7fiy8G1RyM1QA74VyVazahbuXbpuD4QEwm8 pBLw== X-Gm-Message-State: APjAAAWZmioO+tm+ZZ3g5jgyiDhnir4GQqb4NkBiSy/FEkv1f16M/RuA XZzJyD1N6yphOlLcgHdixBLc+wwiVe03Zg== X-Google-Smtp-Source: APXvYqxFFSQWgC+jiM/JRB7o4WqgnTYD7vT75XHmBLnW1lZwqNYX4kdzSjSLnk7gUf2Vo+H1h3qC0Q== X-Received: by 2002:a62:1e06:: with SMTP id e6mr20552435pfe.181.1572278326126; Mon, 28 Oct 2019 08:58:46 -0700 (PDT) Received: from localhost ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id 66sm3855725pgi.49.2019.10.28.08.58.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Oct 2019 08:58:45 -0700 (PDT) Subject: [PULL 17/18] riscv/boot: Fix possible memory leak Date: Mon, 28 Oct 2019 08:49:01 -0700 Message-Id: <20191028154902.32491-18-palmer@sifive.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191028154902.32491-1-palmer@sifive.com> References: <20191028154902.32491-1-palmer@sifive.com> MIME-Version: 1.0 From: Palmer Dabbelt To: Peter Maydell X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::441 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, Palmer Dabbelt , Richard Henderson , qemu-devel@nongnu.org, Alistair Francis , Bin Meng , ilippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Alistair Francis Coverity (CID 1405786) thinks that there is a possible memory leak as we don't guarantee that the memory allocated from riscv_find_firmware() is freed. This is a false positive, but let's tidy up the code to fix the warning. Signed-off-by: Alistair Francis Reviewed-by: Richard Henderson Reviewed-by: Bin Meng Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Palmer Dabbelt --- hw/riscv/boot.c | 11 ++++------- 1 file changed, 4 insertions(+), 7 deletions(-) diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index 2e92fb0680..7fee98d2f8 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -38,7 +38,7 @@ void riscv_find_and_load_firmware(MachineState *machine, const char *default_machine_firmware, hwaddr firmware_load_addr) { - char *firmware_filename; + char *firmware_filename = NULL; if (!machine->firmware) { /* @@ -70,14 +70,11 @@ void riscv_find_and_load_firmware(MachineState *machine, * if no -bios option is set without breaking anything. */ firmware_filename = riscv_find_firmware(default_machine_firmware); - } else { - firmware_filename = machine->firmware; - if (strcmp(firmware_filename, "none")) { - firmware_filename = riscv_find_firmware(firmware_filename); - } + } else if (strcmp(machine->firmware, "none")) { + firmware_filename = riscv_find_firmware(machine->firmware); } - if (strcmp(firmware_filename, "none")) { + if (firmware_filename) { /* If not "none" load the firmware */ riscv_load_firmware(firmware_filename, firmware_load_addr); g_free(firmware_filename); From patchwork Mon Oct 28 15:49:02 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Palmer Dabbelt X-Patchwork-Id: 1185578 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (sender SPF authorized) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=sifive.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=sifive.com header.i=@sifive.com header.b="YURNv/wF"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 4721V22yf5z9sP3 for ; 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Mon, 28 Oct 2019 08:58:47 -0700 (PDT) Received: from localhost ([12.206.222.5]) by smtp.gmail.com with ESMTPSA id g17sm10503611pgn.37.2019.10.28.08.58.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Oct 2019 08:58:47 -0700 (PDT) Subject: [PULL 18/18] target/riscv: PMP violation due to wrong size parameter Date: Mon, 28 Oct 2019 08:49:02 -0700 Message-Id: <20191028154902.32491-19-palmer@sifive.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191028154902.32491-1-palmer@sifive.com> References: <20191028154902.32491-1-palmer@sifive.com> MIME-Version: 1.0 From: Palmer Dabbelt To: Peter Maydell X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::441 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Dayeol Lee , Richard Henderson , Palmer Dabbelt , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Dayeol Lee riscv_cpu_tlb_fill() uses the `size` parameter to check PMP violation using pmp_hart_has_privs(). However, if the size is unknown (=0), the ending address will be `addr - 1` as it is `addr + size - 1` in `pmp_hart_has_privs()`. This always causes a false PMP violation on the starting address of the range, as `addr - 1` is not in the range. In order to fix, we just assume that all bytes from addr to the end of the page will be accessed if the size is unknown. Signed-off-by: Dayeol Lee Reviewed-by: Richard Henderson Signed-off-by: Palmer Dabbelt --- target/riscv/pmp.c | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c index d4f1007109..0e6b640fbd 100644 --- a/target/riscv/pmp.c +++ b/target/riscv/pmp.c @@ -223,6 +223,7 @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr, { int i = 0; int ret = -1; + int pmp_size = 0; target_ulong s = 0; target_ulong e = 0; pmp_priv_t allowed_privs = 0; @@ -232,11 +233,21 @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr, return true; } + /* + * if size is unknown (0), assume that all bytes + * from addr to the end of the page will be accessed. + */ + if (size == 0) { + pmp_size = -(addr | TARGET_PAGE_MASK); + } else { + pmp_size = size; + } + /* 1.10 draft priv spec states there is an implicit order from low to high */ for (i = 0; i < MAX_RISCV_PMPS; i++) { s = pmp_is_in_range(env, i, addr); - e = pmp_is_in_range(env, i, addr + size - 1); + e = pmp_is_in_range(env, i, addr + pmp_size - 1); /* partially inside */ if ((s + e) == 1) {