From patchwork Sat Oct 26 00:26:22 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Walle X-Patchwork-Id: 1184510 X-Patchwork-Delegate: joe.hershberger@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=walle.cc Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=walle.cc header.i=@walle.cc header.b="spyIOOIk"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 470MLH4SzQz9sPc for ; Sat, 26 Oct 2019 11:29:27 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 5ADCCC21ECE; Sat, 26 Oct 2019 00:27:34 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id AF36BC21DD9; Sat, 26 Oct 2019 00:27:15 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 01BA6C21C6A; Sat, 26 Oct 2019 00:27:13 +0000 (UTC) Received: from ssl.serverraum.org (ssl.serverraum.org [176.9.125.105]) by lists.denx.de (Postfix) with ESMTPS id 98C4BC21C6A for ; Sat, 26 Oct 2019 00:27:13 +0000 (UTC) Received: from apollo.fritz.box (unknown [IPv6:2a02:810c:c200:2e91:6257:18ff:fec4:ca34]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by ssl.serverraum.org (Postfix) with ESMTPSA id 4A0F722EE9; Sat, 26 Oct 2019 02:27:13 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=walle.cc; s=mail2016061301; t=1572049633; bh=E9gwEBZIKM+BuqhIOrMJ85sQYbBqQgufhKiqFwdhxzk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=spyIOOIkheOXSCge9KuKDAoCZjcP/CetndUjV5g2s024tvfF7No/850Yz1q29pjxd pv4nszAVyABxokl48YRwKEm5zVAXTTFjTrsq6dCkAxooNkLWtrK7uHrghs94skHUBS PRLiBnFe2UGaSOH72XvmGoXD8eiQ66TWSxwO7TqE= From: Michael Walle To: u-boot@lists.denx.de Date: Sat, 26 Oct 2019 02:26:22 +0200 Message-Id: <20191026002630.25865-2-michael@walle.cc> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191026002630.25865-1-michael@walle.cc> References: <20191026002630.25865-1-michael@walle.cc> MIME-Version: 1.0 X-Virus-Scanned: clamav-milter 0.101.4 at web X-Virus-Status: Clean Subject: [U-Boot] [PATCH 1/9] phy: atheros: introduce debug read and write functions X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Provide functions to read and write the Atheros debug registers. Signed-off-by: Michael Walle Acked-by: Joe Hershberger --- drivers/net/phy/atheros.c | 72 ++++++++++++++++++++++++++++----------- 1 file changed, 53 insertions(+), 19 deletions(-) diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c index 3783d155e7..b25aa02108 100644 --- a/drivers/net/phy/atheros.c +++ b/drivers/net/phy/atheros.c @@ -17,11 +17,52 @@ #define AR803x_DEBUG_REG_0 0x0 #define AR803x_RGMII_RX_CLK_DLY 0x8000 +static int ar803x_debug_reg_read(struct phy_device *phydev, u16 reg) +{ + int ret; + + ret = phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_ADDR_REG, + reg); + if (ret < 0) + return ret; + + return phy_read(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG); +} + +static int ar803x_debug_reg_write(struct phy_device *phydev, u16 reg, u16 val) +{ + int ret; + + ret = phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_ADDR_REG, + reg); + if (ret < 0) + return ret; + + return phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG, + val); +} + +static int ar803x_debug_reg_mask(struct phy_device *phydev, u16 reg, + u16 clear, u16 set) +{ + int val; + + val = ar803x_debug_reg_read(phydev, reg); + if (val < 0) + return val; + + val &= 0xffff; + val &= ~clear; + val |= set; + + return phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG, + val); +} + static int ar8021_config(struct phy_device *phydev) { phy_write(phydev, MDIO_DEVAD_NONE, 0x00, 0x1200); - phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); - phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x3D47); + ar803x_debug_reg_write(phydev, AR803x_DEBUG_REG_5, 0x3D47); phydev->supported = phydev->drv->features; return 0; @@ -31,18 +72,14 @@ static int ar8031_config(struct phy_device *phydev) { if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID || phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) { - phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_ADDR_REG, - AR803x_DEBUG_REG_5); - phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG, - AR803x_RGMII_TX_CLK_DLY); + ar803x_debug_reg_write(phydev, AR803x_DEBUG_REG_5, + AR803x_RGMII_TX_CLK_DLY); } if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID || phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) { - phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_ADDR_REG, - AR803x_DEBUG_REG_0); - phy_write(phydev, MDIO_DEVAD_NONE, AR803x_PHY_DEBUG_DATA_REG, - AR803x_RGMII_RX_CLK_DLY); + ar803x_debug_reg_write(phydev, AR803x_DEBUG_REG_0, + AR803x_RGMII_RX_CLK_DLY); } phydev->supported = phydev->drv->features; @@ -63,24 +100,21 @@ static int ar8035_config(struct phy_device *phydev) regval = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); phy_write(phydev, MDIO_DEVAD_NONE, 0xe, (regval|0x0018)); - phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); - regval = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e); - phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, (regval|0x0100)); + ar803x_debug_reg_mask(phydev, AR803x_DEBUG_REG_5, + 0, AR803x_RGMII_TX_CLK_DLY); if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) || (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)) { - /* select debug reg 5 */ - phy_write(phydev, MDIO_DEVAD_NONE, 0x1D, 0x5); /* enable tx delay */ - phy_write(phydev, MDIO_DEVAD_NONE, 0x1E, 0x0100); + ar803x_debug_reg_write(phydev, AR803x_DEBUG_REG_5, + AR803x_RGMII_TX_CLK_DLY); } if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) || (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)) { - /* select debug reg 0 */ - phy_write(phydev, MDIO_DEVAD_NONE, 0x1D, 0x0); /* enable rx delay */ - phy_write(phydev, MDIO_DEVAD_NONE, 0x1E, 0x8000); + ar803x_debug_reg_write(phydev, AR803x_DEBUG_REG_0, + AR803x_RGMII_RX_CLK_DLY); } phydev->supported = phydev->drv->features; From patchwork Sat Oct 26 00:26:23 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Walle X-Patchwork-Id: 1184509 X-Patchwork-Delegate: joe.hershberger@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=walle.cc Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=walle.cc header.i=@walle.cc header.b="quO/ICiZ"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 470MKZ3Hmlz9sPc for ; Sat, 26 Oct 2019 11:28:50 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 0D08CC21DD9; Sat, 26 Oct 2019 00:27:46 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 2D99CC21E77; Sat, 26 Oct 2019 00:27:16 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 0C066C21DD9; Sat, 26 Oct 2019 00:27:13 +0000 (UTC) Received: from ssl.serverraum.org (ssl.serverraum.org [176.9.125.105]) by lists.denx.de (Postfix) with ESMTPS id C3341C21DD9 for ; Sat, 26 Oct 2019 00:27:13 +0000 (UTC) Received: from apollo.fritz.box (unknown [IPv6:2a02:810c:c200:2e91:6257:18ff:fec4:ca34]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by ssl.serverraum.org (Postfix) with ESMTPSA id 7A65B22EEB; Sat, 26 Oct 2019 02:27:13 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=walle.cc; s=mail2016061301; t=1572049633; bh=jP55Eblf3gdhmrJqysKCkOMyU6WFP7d/R5wi7Yua25A=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=quO/ICiZAtjGVGFUdFI3G5XMWLY02xBLgXiSDI1hzxUH1uPtdJgWrXH+Be1nftSfZ UewfAtdCDaZIvkhvI9XRe5gIlpKyHW5hGF4CfhGNyMxLvb2AFewTUogSVlZELEmUse ujf1hihhiy2zgZkEP5dee6OREKfL21H7dSHwgjA4= From: Michael Walle To: u-boot@lists.denx.de Date: Sat, 26 Oct 2019 02:26:23 +0200 Message-Id: <20191026002630.25865-3-michael@walle.cc> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191026002630.25865-1-michael@walle.cc> References: <20191026002630.25865-1-michael@walle.cc> MIME-Version: 1.0 X-Virus-Scanned: clamav-milter 0.101.4 at web X-Virus-Status: Clean Subject: [U-Boot] [PATCH 2/9] phy: atheros: move delay config to common function X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Signed-off-by: Michael Walle Acked-by: Joe Hershberger --- drivers/net/phy/atheros.c | 44 +++++++++++++++++++++++---------------- 1 file changed, 26 insertions(+), 18 deletions(-) diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c index b25aa02108..402998c8d5 100644 --- a/drivers/net/phy/atheros.c +++ b/drivers/net/phy/atheros.c @@ -68,20 +68,37 @@ static int ar8021_config(struct phy_device *phydev) return 0; } -static int ar8031_config(struct phy_device *phydev) +static int ar803x_delay_config(struct phy_device *phydev) { + int ret; + if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID || phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) { - ar803x_debug_reg_write(phydev, AR803x_DEBUG_REG_5, - AR803x_RGMII_TX_CLK_DLY); + ret = ar803x_debug_reg_write(phydev, AR803x_DEBUG_REG_5, + AR803x_RGMII_TX_CLK_DLY); + if (ret < 0) + return ret; } if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID || phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) { - ar803x_debug_reg_write(phydev, AR803x_DEBUG_REG_0, - AR803x_RGMII_RX_CLK_DLY); + ret = ar803x_debug_reg_write(phydev, AR803x_DEBUG_REG_0, + AR803x_RGMII_RX_CLK_DLY); + if (ret < 0) + return ret; } + return 0; +} + +static int ar8031_config(struct phy_device *phydev) +{ + int ret; + + ret = ar803x_delay_config(phydev); + if (ret < 0) + return ret; + phydev->supported = phydev->drv->features; genphy_config_aneg(phydev); @@ -92,6 +109,7 @@ static int ar8031_config(struct phy_device *phydev) static int ar8035_config(struct phy_device *phydev) { + int ret; int regval; phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x0007); @@ -103,19 +121,9 @@ static int ar8035_config(struct phy_device *phydev) ar803x_debug_reg_mask(phydev, AR803x_DEBUG_REG_5, 0, AR803x_RGMII_TX_CLK_DLY); - if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) || - (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)) { - /* enable tx delay */ - ar803x_debug_reg_write(phydev, AR803x_DEBUG_REG_5, - AR803x_RGMII_TX_CLK_DLY); - } - - if ((phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) || - (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)) { - /* enable rx delay */ - ar803x_debug_reg_write(phydev, AR803x_DEBUG_REG_0, - AR803x_RGMII_RX_CLK_DLY); - } + ret = ar803x_delay_config(phydev); + if (ret < 0) + return ret; phydev->supported = phydev->drv->features; From patchwork Sat Oct 26 00:26:24 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Walle X-Patchwork-Id: 1184508 X-Patchwork-Delegate: joe.hershberger@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=walle.cc Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=walle.cc header.i=@walle.cc header.b="g+Dmu4hw"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 470MKH4sZHz9sPc for ; Sat, 26 Oct 2019 11:28:35 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 58237C21E44; Sat, 26 Oct 2019 00:27:56 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id BB2D5C21EA1; Sat, 26 Oct 2019 00:27:16 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 1F971C21E02; Sat, 26 Oct 2019 00:27:14 +0000 (UTC) Received: from ssl.serverraum.org (ssl.serverraum.org [176.9.125.105]) by lists.denx.de (Postfix) with ESMTPS id F1493C21C51 for ; Sat, 26 Oct 2019 00:27:13 +0000 (UTC) Received: from apollo.fritz.box (unknown [IPv6:2a02:810c:c200:2e91:6257:18ff:fec4:ca34]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by ssl.serverraum.org (Postfix) with ESMTPSA id A6CF522F43; Sat, 26 Oct 2019 02:27:13 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=walle.cc; s=mail2016061301; t=1572049633; bh=+6+enxeILcD363+dk1DeJEUJFDYxtFl8g3wF8fOZNQU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=g+Dmu4hwhhi1d9kYXdqK98t4Boh2fEVtbNQX9iJH2YY3gTcVLKAa2Rtb71x4UhQlG BUXx2NG02fWpFNOplfMeiHnXrBlRx/YgNS+pguENr0/wBZf/1NKVFHst1SGgNtOahv n1oQHu5DN3AJEAXU7OubOOTAe6sfYg++THLyzNuE= From: Michael Walle To: u-boot@lists.denx.de Date: Sat, 26 Oct 2019 02:26:24 +0200 Message-Id: <20191026002630.25865-4-michael@walle.cc> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191026002630.25865-1-michael@walle.cc> References: <20191026002630.25865-1-michael@walle.cc> MIME-Version: 1.0 X-Virus-Scanned: clamav-milter 0.101.4 at web X-Virus-Status: Clean Subject: [U-Boot] [PATCH 3/9] phy: atheros: ar8035: remove extra delay config X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Remove the hard-coded delay configuration. The AR8035 config() always enabled the TX delay mode, although it will be set according to the PHY interface mode, too. If bisecting shows that this commit breaks your board you probably have a wrong PHY interface mode. You probably want the PHY_INTERFACE_MODE_RGMII_TXID or PHY_INTERFACE_MODE_RGMII_ID mode. Signed-off-by: Michael Walle Acked-by: Joe Hershberger --- drivers/net/phy/atheros.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c index 402998c8d5..629c6b192a 100644 --- a/drivers/net/phy/atheros.c +++ b/drivers/net/phy/atheros.c @@ -118,9 +118,6 @@ static int ar8035_config(struct phy_device *phydev) regval = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); phy_write(phydev, MDIO_DEVAD_NONE, 0xe, (regval|0x0018)); - ar803x_debug_reg_mask(phydev, AR803x_DEBUG_REG_5, - 0, AR803x_RGMII_TX_CLK_DLY); - ret = ar803x_delay_config(phydev); if (ret < 0) return ret; From patchwork Sat Oct 26 00:26:25 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Walle X-Patchwork-Id: 1184514 X-Patchwork-Delegate: joe.hershberger@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=walle.cc Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=walle.cc header.i=@walle.cc header.b="WICIjdaA"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 470MP10J0xz9sP4 for ; Sat, 26 Oct 2019 11:31:48 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id A77D7C21F04; Sat, 26 Oct 2019 00:28:05 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 49581C21EA6; Sat, 26 Oct 2019 00:27:17 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 5E18FC21C6A; Sat, 26 Oct 2019 00:27:14 +0000 (UTC) Received: from ssl.serverraum.org (ssl.serverraum.org [176.9.125.105]) by lists.denx.de (Postfix) with ESMTPS id 30EC2C21C51 for ; Sat, 26 Oct 2019 00:27:14 +0000 (UTC) Received: from apollo.fritz.box (unknown [IPv6:2a02:810c:c200:2e91:6257:18ff:fec4:ca34]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by ssl.serverraum.org (Postfix) with ESMTPSA id D62BE22EE9; Sat, 26 Oct 2019 02:27:13 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=walle.cc; s=mail2016061301; t=1572049633; bh=mTHMQJ1LNbUbC4ZkE9kKlHzLBc8l4R9UFYbxC3tdChc=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=WICIjdaATCX6eTbhIcpQmdIvZg/hwx64gfD1gAEKVJhdWdTHnDSA5zbRwgmdU9Kaq KU6GE47PZWJSn7JHuPH3ioCb7sBPkR0QehloFGy34du4XXpLB3+dx0w5XEeeZq1TBW mpKWlx6tDQ0JXd0GzqAsaRzmjFhQCU4LSPsO7DMs= From: Michael Walle To: u-boot@lists.denx.de Date: Sat, 26 Oct 2019 02:26:25 +0200 Message-Id: <20191026002630.25865-5-michael@walle.cc> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191026002630.25865-1-michael@walle.cc> References: <20191026002630.25865-1-michael@walle.cc> MIME-Version: 1.0 X-Virus-Scanned: clamav-milter 0.101.4 at web X-Virus-Status: Clean Subject: [U-Boot] [PATCH 4/9] phy: atheros: ar8035: use phy_{read|write}_mmd() X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Signed-off-by: Michael Walle Acked-by: Joe Hershberger --- drivers/net/phy/atheros.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c index 629c6b192a..113374f03f 100644 --- a/drivers/net/phy/atheros.c +++ b/drivers/net/phy/atheros.c @@ -110,13 +110,12 @@ static int ar8031_config(struct phy_device *phydev) static int ar8035_config(struct phy_device *phydev) { int ret; - int regval; - phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x0007); - phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016); - phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007); - regval = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); - phy_write(phydev, MDIO_DEVAD_NONE, 0xe, (regval|0x0018)); + ret = phy_read_mmd(phydev, 7, 0x8016); + if (ret < 0) + return ret; + ret |= 0x0018; + phy_write_mmd(phydev, 7, 0x8016, ret); ret = ar803x_delay_config(phydev); if (ret < 0) From patchwork Sat Oct 26 00:26:26 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Walle X-Patchwork-Id: 1184512 X-Patchwork-Delegate: joe.hershberger@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=walle.cc Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=walle.cc header.i=@walle.cc header.b="pDbzz69P"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 470MMb4ZJcz9sPc for ; Sat, 26 Oct 2019 11:30:35 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 558A6C21EC9; Sat, 26 Oct 2019 00:28:14 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id CCEBDC21EBF; Sat, 26 Oct 2019 00:27:17 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 949F6C21DDC; Sat, 26 Oct 2019 00:27:14 +0000 (UTC) Received: from ssl.serverraum.org (ssl.serverraum.org [176.9.125.105]) by lists.denx.de (Postfix) with ESMTPS id 60B4CC21C51 for ; Sat, 26 Oct 2019 00:27:14 +0000 (UTC) Received: from apollo.fritz.box (unknown [IPv6:2a02:810c:c200:2e91:6257:18ff:fec4:ca34]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by ssl.serverraum.org (Postfix) with ESMTPSA id 17C0F22EEB; Sat, 26 Oct 2019 02:27:14 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=walle.cc; s=mail2016061301; t=1572049634; bh=PUPOM3HIJLQI0PH7yw4nDDocReMmcGg2eiifw7bd9DU=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=pDbzz69PG21eut08NxhvaC1U85HiA8OvIlasr1EL8T8uFEBbRppT1LH/K0Dm4uUxR jjlQ0U7U/o2IiCSjSUn3mZUX3HKfkMni5eUctUqZBisXRsI0TNBl+P4+gDmg48J7Mu tn+ZN4IG5moh5qexQ0z8j3N43lh7G4QfM9xJNRRU= From: Michael Walle To: u-boot@lists.denx.de Date: Sat, 26 Oct 2019 02:26:26 +0200 Message-Id: <20191026002630.25865-6-michael@walle.cc> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191026002630.25865-1-michael@walle.cc> References: <20191026002630.25865-1-michael@walle.cc> MIME-Version: 1.0 X-Virus-Scanned: clamav-milter 0.101.4 at web X-Virus-Status: Clean Subject: [U-Boot] [PATCH 5/9] phy: atheros: don't overwrite debug register values X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Instead of doing a hard write, do a read-modify-write. Signed-off-by: Michael Walle Acked-by: Joe Hershberger --- drivers/net/phy/atheros.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c index 113374f03f..4b7a1fb9c4 100644 --- a/drivers/net/phy/atheros.c +++ b/drivers/net/phy/atheros.c @@ -12,10 +12,10 @@ #define AR803x_PHY_DEBUG_DATA_REG 0x1e #define AR803x_DEBUG_REG_5 0x5 -#define AR803x_RGMII_TX_CLK_DLY 0x100 +#define AR803x_RGMII_TX_CLK_DLY BIT(8) #define AR803x_DEBUG_REG_0 0x0 -#define AR803x_RGMII_RX_CLK_DLY 0x8000 +#define AR803x_RGMII_RX_CLK_DLY BIT(15) static int ar803x_debug_reg_read(struct phy_device *phydev, u16 reg) { @@ -74,16 +74,16 @@ static int ar803x_delay_config(struct phy_device *phydev) if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID || phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) { - ret = ar803x_debug_reg_write(phydev, AR803x_DEBUG_REG_5, - AR803x_RGMII_TX_CLK_DLY); + ret = ar803x_debug_reg_mask(phydev, AR803x_DEBUG_REG_5, + 0, AR803x_RGMII_TX_CLK_DLY); if (ret < 0) return ret; } if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID || phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) { - ret = ar803x_debug_reg_write(phydev, AR803x_DEBUG_REG_0, - AR803x_RGMII_RX_CLK_DLY); + ret = ar803x_debug_reg_mask(phydev, AR803x_DEBUG_REG_0, + 0, AR803x_RGMII_RX_CLK_DLY); if (ret < 0) return ret; } From patchwork Sat Oct 26 00:26:27 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Walle X-Patchwork-Id: 1184515 X-Patchwork-Delegate: joe.hershberger@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=walle.cc Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=walle.cc header.i=@walle.cc header.b="rRYWVuAM"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 470MP83Gwdz9sP4 for ; Sat, 26 Oct 2019 11:31:56 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 2F10EC21F02; Sat, 26 Oct 2019 00:28:23 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 6F191C21ECA; Sat, 26 Oct 2019 00:27:18 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id C921AC21C6A; Sat, 26 Oct 2019 00:27:14 +0000 (UTC) Received: from ssl.serverraum.org (ssl.serverraum.org [176.9.125.105]) by lists.denx.de (Postfix) with ESMTPS id 8F47DC21DD9 for ; Sat, 26 Oct 2019 00:27:14 +0000 (UTC) Received: from apollo.fritz.box (unknown [IPv6:2a02:810c:c200:2e91:6257:18ff:fec4:ca34]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by ssl.serverraum.org (Postfix) with ESMTPSA id 4622E22F43; Sat, 26 Oct 2019 02:27:14 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=walle.cc; s=mail2016061301; t=1572049634; bh=32tdyxLv6efL64QJuNCSv/hPAHVzSKTY1aI3CdAJ7Tg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=rRYWVuAMPXIQGkhrblntA4Oy57h2D5lOfgOFjgUbm4gFv4HO+OzHwT0Ard3mvIVBL VZhBaDuD7iMLgD5//uz+/fP716BlhayRPSvz+QjrJ1se6e7ci2RGhmKUkRxm0m+EEq DOsOJcjejrD6E+9GvQBHBEWWT4kj1jg6HTSD2Gz4= From: Michael Walle To: u-boot@lists.denx.de Date: Sat, 26 Oct 2019 02:26:27 +0200 Message-Id: <20191026002630.25865-7-michael@walle.cc> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191026002630.25865-1-michael@walle.cc> References: <20191026002630.25865-1-michael@walle.cc> MIME-Version: 1.0 X-Virus-Scanned: clamav-milter 0.101.4 at web X-Virus-Status: Clean Subject: [U-Boot] [PATCH 6/9] phy: atheros: fix delay configuration X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The delay_config() code could only set the delay bit. Thus, it could only enable the delay mode, but not disable it. To make things worse, the RX delay mode is enabled by default after a hardware reset, so it could never be disabled. Fix this, by always setting or clearing the bits. This is also how the linux kernel configures the PHY. If bisecting shows that this commit breaks your board you probably have a wrong PHY interface mode. You probably want the PHY_INTERFACE_MODE_RGMII_RXID or PHY_INTERFACE_MODE_RGMII_ID mode. Signed-off-by: Michael Walle Acked-by: Joe Hershberger --- drivers/net/phy/atheros.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c index 4b7a1fb9c4..8bf26626ff 100644 --- a/drivers/net/phy/atheros.c +++ b/drivers/net/phy/atheros.c @@ -78,6 +78,11 @@ static int ar803x_delay_config(struct phy_device *phydev) 0, AR803x_RGMII_TX_CLK_DLY); if (ret < 0) return ret; + } else { + ret = ar803x_debug_reg_mask(phydev, AR803x_DEBUG_REG_5, + AR803x_RGMII_TX_CLK_DLY, 0); + if (ret < 0) + return ret; } if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID || @@ -86,6 +91,11 @@ static int ar803x_delay_config(struct phy_device *phydev) 0, AR803x_RGMII_RX_CLK_DLY); if (ret < 0) return ret; + } else { + ret = ar803x_debug_reg_mask(phydev, AR803x_DEBUG_REG_0, + AR803x_RGMII_RX_CLK_DLY, 0); + if (ret < 0) + return ret; } return 0; From patchwork Sat Oct 26 00:26:28 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Walle X-Patchwork-Id: 1184516 X-Patchwork-Delegate: joe.hershberger@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=walle.cc Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=walle.cc header.i=@walle.cc header.b="TQ4L7Iya"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 470MPL5DzBz9sP4 for ; Sat, 26 Oct 2019 11:32:06 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 5CACDC21ED6; Sat, 26 Oct 2019 00:28:33 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id F0BA6C21E02; Sat, 26 Oct 2019 00:27:18 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 15CF5C21C6A; Sat, 26 Oct 2019 00:27:15 +0000 (UTC) Received: from ssl.serverraum.org (ssl.serverraum.org [176.9.125.105]) by lists.denx.de (Postfix) with ESMTPS id BDFD8C21C51 for ; Sat, 26 Oct 2019 00:27:14 +0000 (UTC) Received: from apollo.fritz.box (unknown [IPv6:2a02:810c:c200:2e91:6257:18ff:fec4:ca34]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by ssl.serverraum.org (Postfix) with ESMTPSA id 74F4022EE9; Sat, 26 Oct 2019 02:27:14 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=walle.cc; s=mail2016061301; t=1572049634; bh=OFZzQED0Lby/LoL2WM2GbKd855Ljo2pw/I+8k9q70zE=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=TQ4L7Iya12zhTyDsH08zrm5hGLmseBh4epg4AW4wggeMx1yPqoySQbmb+M3wTfCvv 4Gvv97/JRy6mmtcBg3OqqTj0j5FAirQZbIiZ3u/fYgUGt0HdZSc8wJi6g212+aTj8q 2cU9soPqdcNncWanBkooGPEKkxjseSyrDRrYZFpI= From: Michael Walle To: u-boot@lists.denx.de Date: Sat, 26 Oct 2019 02:26:28 +0200 Message-Id: <20191026002630.25865-8-michael@walle.cc> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191026002630.25865-1-michael@walle.cc> References: <20191026002630.25865-1-michael@walle.cc> MIME-Version: 1.0 X-Virus-Scanned: clamav-milter 0.101.4 at web X-Virus-Status: Clean Subject: [U-Boot] [PATCH 7/9] phy: atheros: Add device tree bindings and config X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add support for configuring the CLK_25M pin as well as the RGMII I/O voltage by the device tree. By default the AT803x PHYs outputs the 25MHz clock of the XTAL input. But this output can also be changed by software to other frequencies. This commit introduces a generic way to configure this output. Also the PHY supports different RGMII I/O voltages: 1.5V, 1.8V and 2.5V. An internal LDO is able to provide 1.5V (default) and 1.8V. The 2.5V option needs an external supply voltage. This commit adds support to switch the internal LDO to 1.8V. Signed-off-by: Michael Walle Acked-by: Joe Hershberger --- doc/device-tree-bindings/net/phy/atheros.txt | 22 +++ drivers/net/phy/atheros.c | 160 ++++++++++++++++++- 2 files changed, 180 insertions(+), 2 deletions(-) create mode 100644 doc/device-tree-bindings/net/phy/atheros.txt diff --git a/doc/device-tree-bindings/net/phy/atheros.txt b/doc/device-tree-bindings/net/phy/atheros.txt new file mode 100644 index 0000000000..112250114f --- /dev/null +++ b/doc/device-tree-bindings/net/phy/atheros.txt @@ -0,0 +1,22 @@ +* Atheros PHY Device Tree binding + +Required properties: +- reg: PHY address + +Optional properties: +- atheros,clk-out-frequency: Clock frequency of the CLK_25M pin in Hz. + Either 25000000, 50000000, 62500000 or 125000000. +- atheros,clk-out-strength: Clock output buffer driver strength. + Either "full", "half" or "quarter". +- atheros,keep-pll-enabled: Keep the PLL running if no link is present. + Don't go into hibernation mode. +- atheros,rgmii-io-1v8: Use 1.8V as RGMII I/O voltage, the default is 1.5V. + +Example: + + ethernet-phy@0 { + reg = <0>; + atheros-clk-out-frequency = <125000000>; + atheros,keep-pll-enabled; + atheros,rgmii-io-1v8; + }; diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c index 8bf26626ff..1c8c9b4e75 100644 --- a/drivers/net/phy/atheros.c +++ b/drivers/net/phy/atheros.c @@ -4,6 +4,7 @@ * * Copyright 2011, 2013 Freescale Semiconductor, Inc. * author Andy Fleming + * Copyright (c) 2019 Michael Walle */ #include #include @@ -11,11 +12,41 @@ #define AR803x_PHY_DEBUG_ADDR_REG 0x1d #define AR803x_PHY_DEBUG_DATA_REG 0x1e +/* Debug registers */ +#define AR803x_DEBUG_REG_0 0x0 +#define AR803x_RGMII_RX_CLK_DLY BIT(15) + #define AR803x_DEBUG_REG_5 0x5 #define AR803x_RGMII_TX_CLK_DLY BIT(8) -#define AR803x_DEBUG_REG_0 0x0 -#define AR803x_RGMII_RX_CLK_DLY BIT(15) +#define AR803x_DEBUG_REG_1F 0x1f +#define AR803x_PLL_ON BIT(2) +#define AR803x_RGMII_1V8 BIT(3) + +/* MMD registers */ +#define AR803x_MMD7_CLK25M 0x8016 +#define AR803x_CLK_OUT_25MHZ_XTAL (0 << 2) +#define AR803x_CLK_OUT_25MHZ_DSP (1 << 2) +#define AR803x_CLK_OUT_50MHZ_PLL (2 << 2) +#define AR803x_CLK_OUT_50MHZ_DSP (3 << 2) +#define AR803x_CLK_OUT_62_5MHZ_PLL (4 << 2) +#define AR803x_CLK_OUT_62_5MHZ_DSP (5 << 2) +#define AR803x_CLK_OUT_125MHZ_PLL (6 << 2) +#define AR803x_CLK_OUT_125MHZ_DSP (7 << 2) +#define AR803x_CLK_OUT_MASK (7 << 2) + +#define AR803x_CLK_OUT_STRENGTH_FULL (0 << 6) +#define AR803x_CLK_OUT_STRENGTH_HALF (1 << 6) +#define AR803x_CLK_OUT_STRENGTH_QUARTER (2 << 6) +#define AR803x_CLK_OUT_STRENGTH_MASK (3 << 6) + +struct ar803x_priv { + int flags; +#define AR803x_FLAG_KEEP_PLL_ENABLED BIT(0) /* don't turn off internal PLL */ +#define AR803x_FLAG_RGMII_1V8 BIT(1) /* use 1.8V RGMII I/O voltage */ + u16 clk_25m_reg; + u16 clk_25m_mask; +}; static int ar803x_debug_reg_read(struct phy_device *phydev, u16 reg) { @@ -101,14 +132,131 @@ static int ar803x_delay_config(struct phy_device *phydev) return 0; } +static int ar803x_regs_config(struct phy_device *phydev) +{ + struct ar803x_priv *priv = phydev->priv; + u16 set = 0, clear = 0; + int val; + int ret; + + /* no configuration available */ + if (!priv) + return 0; + + if (priv->flags & AR803x_FLAG_KEEP_PLL_ENABLED) + set |= AR803x_PLL_ON; + else + clear |= AR803x_PLL_ON; + + if (priv->flags & AR803x_FLAG_RGMII_1V8) + set |= AR803x_RGMII_1V8; + else + clear |= AR803x_RGMII_1V8; + + ret = ar803x_debug_reg_mask(phydev, AR803x_DEBUG_REG_1F, clear, set); + if (ret < 0) + return ret; + + /* save the write access if the mask is empty */ + if (priv->clk_25m_mask) { + val = phy_read_mmd(phydev, 7, AR803x_MMD7_CLK25M); + if (val < 0) + return val; + val &= ~priv->clk_25m_mask; + val |= priv->clk_25m_reg; + ret = phy_write_mmd(phydev, 7, AR803x_MMD7_CLK25M, val); + if (ret < 0) + return ret; + } + + return 0; +} + +static int ar803x_of_init(struct phy_device *phydev) +{ +#if defined(CONFIG_DM_ETH) + struct ar803x_priv *priv; + ofnode node; + const char *strength; + u32 freq; + + priv = malloc(sizeof(*priv)); + if (!priv) + return -ENOMEM; + memset(priv, 0, sizeof(*priv)); + + phydev->priv = priv; + + node = phy_get_ofnode(phydev); + if (!ofnode_valid(node)) + return -EINVAL; + + if (ofnode_read_bool(node, "atheros,keep-pll-enabled")) + priv->flags |= AR803x_FLAG_KEEP_PLL_ENABLED; + if (ofnode_read_bool(node, "atheros,rgmii-io-1v8")) + priv->flags |= AR803x_FLAG_RGMII_1V8; + + /* + * Get the CLK_OUT frequency from the device tree. Only XTAL and PLL + * sources are supported right now. There is also the possibilty to use + * the DSP as frequency reference, this is used for synchronous + * ethernet. + */ + freq = ofnode_read_u32_default(node, "atheros,clk-out-frequency", 0); + if (freq) { + priv->clk_25m_mask |= AR803x_CLK_OUT_MASK; + if (freq == 25000000) { + priv->clk_25m_reg |= AR803x_CLK_OUT_25MHZ_XTAL; + } else if (freq == 50000000) { + priv->clk_25m_reg |= AR803x_CLK_OUT_50MHZ_PLL; + } else if (freq == 62500000) { + priv->clk_25m_reg |= AR803x_CLK_OUT_62_5MHZ_PLL; + } else if (freq == 125000000) { + priv->clk_25m_reg |= AR803x_CLK_OUT_125MHZ_PLL; + } else { + dev_err(phydev->dev, + "invalid atheros,clk-out-frequency\n"); + free(priv); + return -EINVAL; + } + } + + strength = ofnode_read_string(node, "atheros,clk-out-strength"); + if (strength) { + priv->clk_25m_mask |= AR803x_CLK_OUT_STRENGTH_MASK; + if (!strcmp(strength, "full")) { + priv->clk_25m_reg |= AR803x_CLK_OUT_STRENGTH_FULL; + } else if (!strcmp(strength, "half")) { + priv->clk_25m_reg |= AR803x_CLK_OUT_STRENGTH_HALF; + } else if (!strcmp(strength, "quarter")) { + priv->clk_25m_reg |= AR803x_CLK_OUT_STRENGTH_QUARTER; + } else { + dev_err(phydev->dev, "invalid atheros,strength\n"); + free(priv); + return -EINVAL; + } + } +#endif + + return 0; +} + static int ar8031_config(struct phy_device *phydev) { int ret; + ret = ar803x_of_init(phydev); + if (ret < 0) + return ret; + ret = ar803x_delay_config(phydev); if (ret < 0) return ret; + ret = ar803x_regs_config(phydev); + if (ret < 0) + return ret; + phydev->supported = phydev->drv->features; genphy_config_aneg(phydev); @@ -121,6 +269,10 @@ static int ar8035_config(struct phy_device *phydev) { int ret; + ret = ar803x_of_init(phydev); + if (ret < 0) + return ret; + ret = phy_read_mmd(phydev, 7, 0x8016); if (ret < 0) return ret; @@ -131,6 +283,10 @@ static int ar8035_config(struct phy_device *phydev) if (ret < 0) return ret; + ret = ar803x_regs_config(phydev); + if (ret < 0) + return ret; + phydev->supported = phydev->drv->features; genphy_config_aneg(phydev); From patchwork Sat Oct 26 00:26:29 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Walle X-Patchwork-Id: 1184513 X-Patchwork-Delegate: joe.hershberger@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=walle.cc Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=walle.cc header.i=@walle.cc header.b="awiE66Uw"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 470MMz12zzz9sPc for ; Sat, 26 Oct 2019 11:30:55 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id D1CA4C21EBA; Sat, 26 Oct 2019 00:28:48 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 80E50C21EE7; Sat, 26 Oct 2019 00:27:19 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 289BEC21E02; Sat, 26 Oct 2019 00:27:15 +0000 (UTC) Received: from ssl.serverraum.org (ssl.serverraum.org [176.9.125.105]) by lists.denx.de (Postfix) with ESMTPS id 01B4CC21DDC for ; Sat, 26 Oct 2019 00:27:14 +0000 (UTC) Received: from apollo.fritz.box (unknown [IPv6:2a02:810c:c200:2e91:6257:18ff:fec4:ca34]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by ssl.serverraum.org (Postfix) with ESMTPSA id A364922EEB; Sat, 26 Oct 2019 02:27:14 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=walle.cc; s=mail2016061301; t=1572049634; bh=eCLWDeYUYg/RQ5GtFidYaA+lbRsU+yzFQYvS/HEZzFA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=awiE66Uw/syFzlL9kWoz/jNcs/xUB9yb9XzfiSAp6eLdTHvFx0XRuvlvQkDY7Bb9L AZvzptAFTM2hvO4n6AyCLoFoJh8yIDL3wK0GggNrAveUNWx1aV+9FfoPVH2L7mfvHn hmcll8iMBrdbfucQcBwfaCy3RZxBtp5n9NVtqOfo= From: Michael Walle To: u-boot@lists.denx.de Date: Sat, 26 Oct 2019 02:26:29 +0200 Message-Id: <20191026002630.25865-9-michael@walle.cc> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191026002630.25865-1-michael@walle.cc> References: <20191026002630.25865-1-michael@walle.cc> MIME-Version: 1.0 X-Virus-Scanned: clamav-milter 0.101.4 at web X-Virus-Status: Clean Subject: [U-Boot] [PATCH 8/9] phy: atheros: ar8035: remove static clock config X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" We can configure the clock output in the device tree. Disable the hardcoded one in here. This is highly board-specific and should have never been enabled in the PHY driver. If bisecting shows that this commit breaks your board it probably depends on the clock output of your Atheros AR8035 PHY. Please have a look at doc/device-tree-bindings/net/phy/atheros.txt. You need to set "clk-out-frequency = <125000000>" because that value was the hardcoded value until this commit. Signed-off-by: Michael Walle Acked-by: Joe Hershberger --- drivers/net/phy/atheros.c | 6 ------ 1 file changed, 6 deletions(-) diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c index 1c8c9b4e75..91fcbf912a 100644 --- a/drivers/net/phy/atheros.c +++ b/drivers/net/phy/atheros.c @@ -273,12 +273,6 @@ static int ar8035_config(struct phy_device *phydev) if (ret < 0) return ret; - ret = phy_read_mmd(phydev, 7, 0x8016); - if (ret < 0) - return ret; - ret |= 0x0018; - phy_write_mmd(phydev, 7, 0x8016, ret); - ret = ar803x_delay_config(phydev); if (ret < 0) return ret; From patchwork Sat Oct 26 00:26:30 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Walle X-Patchwork-Id: 1184511 X-Patchwork-Delegate: joe.hershberger@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=walle.cc Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=walle.cc header.i=@walle.cc header.b="AGDtKCof"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 470MM91x3hz9sPc for ; Sat, 26 Oct 2019 11:30:13 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id F1FDCC21EDC; Sat, 26 Oct 2019 00:28:57 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 23779C21E7D; Sat, 26 Oct 2019 00:27:31 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id CE877C21EA6; Sat, 26 Oct 2019 00:27:16 +0000 (UTC) Received: from ssl.serverraum.org (ssl.serverraum.org [176.9.125.105]) by lists.denx.de (Postfix) with ESMTPS id 2FDA4C21E07 for ; Sat, 26 Oct 2019 00:27:15 +0000 (UTC) Received: from apollo.fritz.box (unknown [IPv6:2a02:810c:c200:2e91:6257:18ff:fec4:ca34]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by ssl.serverraum.org (Postfix) with ESMTPSA id D98DD22F43; Sat, 26 Oct 2019 02:27:14 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=walle.cc; s=mail2016061301; t=1572049634; bh=k6WHwaheCURSZVlgyJ5cV9EQIGQdIY/9PM1g5Z+1yGA=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=AGDtKCofNUM795Jyq48edbOrcgS8fw5bW6qwJnBkl6fgLzu6v+NXbcyQBr+zwYKUI d+YxyhJNSaMwBug2NA3ZU0P5DuZw8sq+lNnK+/vC5lNxEbnYyVyIizbWr5uPDqU/2N nduP0+YS2xizi6cOTvi+27BC9t5dMdsyLVVGxOlU= From: Michael Walle To: u-boot@lists.denx.de Date: Sat, 26 Oct 2019 02:26:30 +0200 Message-Id: <20191026002630.25865-10-michael@walle.cc> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20191026002630.25865-1-michael@walle.cc> References: <20191026002630.25865-1-michael@walle.cc> MIME-Version: 1.0 X-Virus-Scanned: clamav-milter 0.101.4 at web X-Virus-Status: Clean Subject: [U-Boot] [PATCH 9/9] phy: atheros: consolidate {ar8031|ar8035}_config() X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The two functions are now exactly the same, remove one of them. Signed-off-by: Michael Walle Acked-by: Joe Hershberger --- drivers/net/phy/atheros.c | 30 +++--------------------------- 1 file changed, 3 insertions(+), 27 deletions(-) diff --git a/drivers/net/phy/atheros.c b/drivers/net/phy/atheros.c index 91fcbf912a..922dc91835 100644 --- a/drivers/net/phy/atheros.c +++ b/drivers/net/phy/atheros.c @@ -241,31 +241,7 @@ static int ar803x_of_init(struct phy_device *phydev) return 0; } -static int ar8031_config(struct phy_device *phydev) -{ - int ret; - - ret = ar803x_of_init(phydev); - if (ret < 0) - return ret; - - ret = ar803x_delay_config(phydev); - if (ret < 0) - return ret; - - ret = ar803x_regs_config(phydev); - if (ret < 0) - return ret; - - phydev->supported = phydev->drv->features; - - genphy_config_aneg(phydev); - genphy_restart_aneg(phydev); - - return 0; -} - -static int ar8035_config(struct phy_device *phydev) +static int ar803x_config(struct phy_device *phydev) { int ret; @@ -304,7 +280,7 @@ static struct phy_driver AR8031_driver = { .uid = 0x4dd074, .mask = 0xffffffef, .features = PHY_GBIT_FEATURES, - .config = ar8031_config, + .config = ar803x_config, .startup = genphy_startup, .shutdown = genphy_shutdown, }; @@ -314,7 +290,7 @@ static struct phy_driver AR8035_driver = { .uid = 0x4dd072, .mask = 0xffffffef, .features = PHY_GBIT_FEATURES, - .config = ar8035_config, + .config = ar803x_config, .startup = genphy_startup, .shutdown = genphy_shutdown, };