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Thu, 16 Nov 2017 12:34:15 +0000 From: Alan Hayward To: "gcc-patches@gcc.gnu.org" CC: nd Subject: [PATCH 1/7]: SVE: Add CLOBBER_HIGH expression Date: Thu, 16 Nov 2017 12:34:15 +0000 Message-ID: authentication-results: spf=none (sender IP is ) smtp.mailfrom=Alan.Hayward@arm.com; x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; AM3PR08MB0103; 6:RX7A/HPQ9+UwvgFEkPGFi7rgPpWo1ae/GElpYn2XlsEFvmG98WCtsR2kQHaR3BHZsLes4/nNzFUrs5Qwj1s0gYNAvkboitVgxeFzBWDsUArcZFCs15RrAL84g854jy0ASLlam3t81HsRinUBUEB4jj004kGqnU8s/2v+oLJQaE6f69MTnaLdiY/90Y6vhLxuul6Bs87i1gY+W0gU6gqjfH6hCEA5D6pcWpD+6bSdl/f1xBybtSZeSEp0Z9A2CYpEjmENvHLHmJGvHIQzed6HexuJnYrcgZJ/tm3ZsWK7J0rPpoRiqJdzLTo2VhI0Bdi/V9uHIu1zQGJSW/xrnTdcXKK1nsjnlUCqe3kjIbZzmG0=; 5:+BGNHFCnezS1qmmuRxLvb5iMkR4nrYbmJ7KnnTltDoUyPa/MfN4xmUahITfTic5lSHyOLnMfe9TE/JBpgUAZZCAA3UzHoEB8C/hfNGFKwxsLF3Ejo/JqLeCe4ReIdK529zECuizUQV77N1xwF9tfh6HjyOSMT29nOLPXtId3v78=; 24:WFwdTL8YFsyM2qCOEg4KiViwgLCoplAb85R1wGPXTma+RNHLxdZ/4crKsC1xdubAJZ+igDAhQedSFIWcNiEtaR7oObA8CA2xxH/IfQ/wZMk=; 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received-spf: None (protection.outlook.com: arm.com does not designate permitted sender hosts) spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM Content-ID: MIME-Version: 1.0 X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-Network-Message-Id: bbf22358-33b0-4847-849d-08d52cee5984 X-MS-Exchange-CrossTenant-originalarrivaltime: 16 Nov 2017 12:34:15.6926 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM3PR08MB0103 This is a set of patches aimed at supporting aarch64 SVE register preservation around TLS calls. Across a TLS call, Aarch64 SVE does not explicitly preserve the SVE vector registers. However, the Neon vector registers are preserved. Due to overlapping of registers, this means the lower 128bits of all SVE vector registers will be preserved. The existing GCC code will currently incorrectly assume preservation of all of the SVE registers. This patch introduces a CLOBBER_HIGH expression. This behaves a bit like a CLOBBER expression. CLOBBER_HIGH can only refer to a single register. The mode of the expression indicates the size of the lower bits which will be preserved. If the register contains a value bigger than this mode then the code will treat the register as clobbered. The means in order to evaluate if a clobber high is relevant, we need to ensure the mode of the existing value in a register is tracked. The following patches in this series add support for the CLOBBER_HIGH, with the final patch adding CLOBBER_HIGHs around TLS_DESC calls for aarch64. The testing performed on these patches is also detailed in the final patch. These patches are based on top of the linaro-dev/sve branch. A simpler alternative to this patch would be to assume all Neon and SVE registers are clobbered across TLS calls, however this would be a performance regression against all Aarch64 targets. Alan. 2017-11-16 Alan Hayward * doc/rtl.texi (clobber_high): Add. (parallel): Add in clobber high * rtl.c (rtl_check_failed_code3): Add function. * rtl.def (CLOBBER_HIGH): Add expression. * rtl.h (RTL_CHECKC3): Add macro. (rtl_check_failed_code3): Add declaration. (XC3EXP): Add macro. /* Methods of rtx_expr_list. */ @@ -2551,7 +2565,7 @@ do { \ /* For a SET rtx, SET_DEST is the place that is set and SET_SRC is the value it is set to. */ -#define SET_DEST(RTX) XC2EXP (RTX, 0, SET, CLOBBER) +#define SET_DEST(RTX) XC3EXP (RTX, 0, SET, CLOBBER, CLOBBER_HIGH) #define SET_SRC(RTX) XCEXP (RTX, 1, SET) #define SET_IS_RETURN_P(RTX) \ (RTL_FLAG_CHECK1 ("SET_IS_RETURN_P", (RTX), SET)->jump) diff --git a/gcc/doc/rtl.texi b/gcc/doc/rtl.texi index f583940b9441b2111c8d65a00a064e89bdd2ffaf..951322258ddbb57900225bd501bd23a8a9970ead 100644 --- a/gcc/doc/rtl.texi +++ b/gcc/doc/rtl.texi @@ -3209,6 +3209,18 @@ There is one other known use for clobbering a pseudo register in a clobbered by the insn. In this case, using the same pseudo register in the clobber and elsewhere in the insn produces the expected results. +@findex clobber_high +@item (clobber_high @var{x}) +Represents the storing or possible storing of an unpredictable, +undescribed value into the upper parts of @var{x}. The mode of the expression +represents the lower parts of the register which will not be overwritten. +@code{reg} must be a reg expression. + +One place this is used is when calling into functions where the registers are +preserved, but only up to a given number of bits. For example when using +Aarch64 SVE, calling a TLS descriptor will cause only the lower 128 bits of +each of the vector registers to be preserved. + @findex use @item (use @var{x}) Represents the use of the value of @var{x}. It indicates that the @@ -3262,7 +3274,8 @@ Represents several side effects performed in parallel. The square brackets stand for a vector; the operand of @code{parallel} is a vector of expressions. @var{x0}, @var{x1} and so on are individual side effect expressions---expressions of code @code{set}, @code{call}, -@code{return}, @code{simple_return}, @code{clobber} or @code{use}. +@code{return}, @code{simple_return}, @code{clobber} @code{use} or +@code{clobber_high}. ``In parallel'' means that first all the values used in the individual side-effects are computed, and second all the actual side-effects are diff --git a/gcc/rtl.c b/gcc/rtl.c index 3b2728be8b506fb3c14a20297cf92368caa5ca3b..6db84f99627bb8617c6e227892ca44076f4e729b 100644 --- a/gcc/rtl.c +++ b/gcc/rtl.c @@ -860,6 +860,17 @@ rtl_check_failed_code2 (const_rtx r, enum rtx_code code1, enum rtx_code code2, } void +rtl_check_failed_code3 (const_rtx r, enum rtx_code code1, enum rtx_code code2, + enum rtx_code code3, const char *file, int line, + const char *func) +{ + internal_error + ("RTL check: expected code '%s', '%s' or '%s', have '%s' in %s, at %s:%d", + GET_RTX_NAME (code1), GET_RTX_NAME (code2), GET_RTX_NAME (code3), + GET_RTX_NAME (GET_CODE (r)), func, trim_filename (file), line); +} + +void rtl_check_failed_code_mode (const_rtx r, enum rtx_code code, machine_mode mode, bool not_mode, const char *file, int line, const char *func) diff --git a/gcc/rtl.def b/gcc/rtl.def index 83bcfcaadcacc45cce352bf7fba33fbbc87ccd58..a6c4d4a46c4eb4f6cb0eca66a3f6a558f94acc8a 100644 --- a/gcc/rtl.def +++ b/gcc/rtl.def @@ -312,6 +312,16 @@ DEF_RTL_EXPR(USE, "use", "e", RTX_EXTRA) is considered undeletable before reload. */ DEF_RTL_EXPR(CLOBBER, "clobber", "e", RTX_EXTRA) +/* Indicate that the upper parts of something are clobbered in a way that we + don't want to explain. The MODE references the lower bits that will be + preserved. Anything above that size will be clobbered. + + CLOBBER_HIGH only occurs as the operand of a PARALLEL rtx. It cannot appear + in other contexts, and unlike CLOBBER, it cannot appear on its own. + CLOBBER_HIGH can only be used with fixed register rtxes. */ + +DEF_RTL_EXPR(CLOBBER_HIGH, "clobber_high", "e", RTX_EXTRA) + /* Call a subroutine. Operand 1 is the address to call. Operand 2 is the number of arguments. */ diff --git a/gcc/rtl.h b/gcc/rtl.h index ec5cf314a9e516e7e855e5d897a9a26c4ce36c20..71621bdfd67c4ce3dcccc5279456cae841371f97 100644 --- a/gcc/rtl.h +++ b/gcc/rtl.h @@ -1083,6 +1083,14 @@ is_a_helper ::test (rtx_insn *insn) __FUNCTION__); \ &_rtx->u.fld[_n]; })) +#define RTL_CHECKC3(RTX, N, C1, C2, C3) __extension__ \ +(*({ __typeof (RTX) const _rtx = (RTX); const int _n = (N); \ + const enum rtx_code _code = GET_CODE (_rtx); \ + if (_code != (C1) && _code != (C2) && _code != (C3)) \ + rtl_check_failed_code3 (_rtx, (C1), (C2), (C3), __FILE__, \ + __LINE__, __FUNCTION__); \ + &_rtx->u.fld[_n]; })) + #define RTVEC_ELT(RTVEC, I) __extension__ \ (*({ __typeof (RTVEC) const _rtvec = (RTVEC); const int _i = (I); \ if (_i < 0 || _i >= GET_NUM_ELEM (_rtvec)) \ @@ -1173,6 +1181,10 @@ extern void rtl_check_failed_code1 (const_rtx, enum rtx_code, const char *, extern void rtl_check_failed_code2 (const_rtx, enum rtx_code, enum rtx_code, const char *, int, const char *) ATTRIBUTE_NORETURN ATTRIBUTE_COLD; +extern void rtl_check_failed_code3 (const_rtx, enum rtx_code, enum rtx_code, + enum rtx_code, const char *, int, + const char *) + ATTRIBUTE_NORETURN ATTRIBUTE_COLD; extern void rtl_check_failed_code_mode (const_rtx, enum rtx_code, machine_mode, bool, const char *, int, const char *) ATTRIBUTE_NORETURN ATTRIBUTE_COLD; @@ -1191,6 +1203,7 @@ extern void rtvec_check_failed_bounds (const_rtvec, int, const char *, int, #define RTL_CHECK2(RTX, N, C1, C2) ((RTX)->u.fld[N]) #define RTL_CHECKC1(RTX, N, C) ((RTX)->u.fld[N]) #define RTL_CHECKC2(RTX, N, C1, C2) ((RTX)->u.fld[N]) +#define RTL_CHECKC3(RTX, N, C1, C2, C3) ((RTX)->u.fld[N]) #define RTVEC_ELT(RTVEC, I) ((RTVEC)->elem[I]) #define XWINT(RTX, N) ((RTX)->u.hwint[N]) #define CWI_ELT(RTX, I) ((RTX)->u.hwiv.elem[I]) @@ -1345,6 +1358,7 @@ extern void rtl_check_failed_flag (const char *, const_rtx, const char *, #define XCVECLEN(RTX, N, C) GET_NUM_ELEM (XCVEC (RTX, N, C)) #define XC2EXP(RTX, N, C1, C2) (RTL_CHECKC2 (RTX, N, C1, C2).rt_rtx) +#define XC3EXP(RTX, N, C1, C2, C3) (RTL_CHECKC3 (RTX, N, C1, C2, C3).rt_rtx) From patchwork Thu Nov 16 12:34:37 2017 Content-Type: text/plain; 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Thu, 16 Nov 2017 12:34:38 +0000 From: Alan Hayward To: "gcc-patches@gcc.gnu.org" CC: nd Subject: [PATCH 2/7] Support >26 operands in generation code. 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An aarch64 will require 31 clobber high expressions, plus two clobbers. The exisiting gen code restricts to 26 vector operands by virtue of using the operators [a-z]. This patch extends this to 52 by supporting [a-zA-Z]. Alan. 2017-11-16 Alan Hayward * emit-rtl.c (verify_rtx_sharing): Check CLOBBER_HIGH. (copy_insn_1): Likewise. (gen_hard_reg_clobber_high): Add function. * genconfig.c (walk_insn_part): Check CLOBBER_HIGH. * genemit.c (gen_exp): Likewise. (gen_emit_seq): Pass thru info. (gen_insn): Check CLOBBER_HIGH. (gen_expand): Pass thru info. (gen_split): Likewise. (output_add_clobbers): Likewise. * genextract.c (push_pathstr_operand): New function to support [a-zA-Z]. (walk_rtx): Call push_pathstr_operand. (print_path): Support [a-zA-Z]. * genrecog.c (validate_pattern): Check CLOBBER_HIGH. (remove_clobbers): Likewise. * rtl.h (gen_hard_reg_clobber_high): Add declaration. diff --git a/gcc/emit-rtl.c b/gcc/emit-rtl.c index af4a038d75acf17c7b04ad58ab7467f7bd7cd129..64159a82e3f79b792d58166d4307db8751c88980 100644 --- a/gcc/emit-rtl.c +++ b/gcc/emit-rtl.c @@ -2895,6 +2895,7 @@ verify_rtx_sharing (rtx orig, rtx insn) /* SCRATCH must be shared because they represent distinct values. */ return; case CLOBBER: + case CLOBBER_HIGH: /* Share clobbers of hard registers (like cc0), but do not share pseudo reg clobbers or clobbers of hard registers that originated as pseudos. This is needed to allow safe register renaming. */ @@ -3148,6 +3149,7 @@ repeat: /* SCRATCH must be shared because they represent distinct values. */ return; case CLOBBER: + case CLOBBER_HIGH: /* Share clobbers of hard registers (like cc0), but do not share pseudo reg clobbers or clobbers of hard registers that originated as pseudos. This is needed to allow safe register renaming. */ @@ -5707,6 +5709,7 @@ copy_insn_1 (rtx orig) case SIMPLE_RETURN: return orig; case CLOBBER: + case CLOBBER_HIGH: /* Share clobbers of hard registers (like cc0), but do not share pseudo reg clobbers or clobbers of hard registers that originated as pseudos. This is needed to allow safe register renaming. */ @@ -6529,6 +6532,19 @@ gen_hard_reg_clobber (machine_mode mode, unsigned int regno) gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (mode, regno))); } +static GTY((deletable)) rtx +hard_reg_clobbers_high[NUM_MACHINE_MODES][FIRST_PSEUDO_REGISTER]; + +rtx +gen_hard_reg_clobber_high (machine_mode mode, unsigned int regno) +{ + if (hard_reg_clobbers_high[mode][regno]) + return hard_reg_clobbers_high[mode][regno]; + else + return (hard_reg_clobbers_high[mode][regno] + = gen_rtx_CLOBBER_HIGH (VOIDmode, gen_rtx_REG (mode, regno))); +} + location_t prologue_location; location_t epilogue_location; diff --git a/gcc/genconfig.c b/gcc/genconfig.c index 4ff36cb019d427f410d9f251777b9b05217fac36..4108e9c457fce5529ec9a3284d37f933736776ad 100644 --- a/gcc/genconfig.c +++ b/gcc/genconfig.c @@ -72,6 +72,7 @@ walk_insn_part (rtx part, int recog_p, int non_pc_set_src) switch (code) { case CLOBBER: + case CLOBBER_HIGH: clobbers_seen_this_insn++; break; diff --git a/gcc/genemit.c b/gcc/genemit.c index 708da27221546c406030e88a4b07a51fb9df4a14..4e93b6b9831c65fc829fed6367881233b8eddcac 100644 --- a/gcc/genemit.c +++ b/gcc/genemit.c @@ -79,7 +79,7 @@ gen_rtx_scratch (rtx x, enum rtx_code subroutine_type) substituting any operand references appearing within. */ static void -gen_exp (rtx x, enum rtx_code subroutine_type, char *used) +gen_exp (rtx x, enum rtx_code subroutine_type, char *used, md_rtx_info *info) { RTX_CODE code; int i; @@ -123,7 +123,7 @@ gen_exp (rtx x, enum rtx_code subroutine_type, char *used) for (i = 0; i < XVECLEN (x, 1); i++) { printf (",\n\t\t"); - gen_exp (XVECEXP (x, 1, i), subroutine_type, used); + gen_exp (XVECEXP (x, 1, i), subroutine_type, used, info); } printf (")"); return; @@ -137,7 +137,7 @@ gen_exp (rtx x, enum rtx_code subroutine_type, char *used) for (i = 0; i < XVECLEN (x, 2); i++) { printf (",\n\t\t"); - gen_exp (XVECEXP (x, 2, i), subroutine_type, used); + gen_exp (XVECEXP (x, 2, i), subroutine_type, used, info); } printf (")"); return; @@ -163,12 +163,21 @@ gen_exp (rtx x, enum rtx_code subroutine_type, char *used) case CLOBBER: if (REG_P (XEXP (x, 0))) { - printf ("gen_hard_reg_clobber (%smode, %i)", GET_MODE_NAME (GET_MODE (XEXP (x, 0))), - REGNO (XEXP (x, 0))); + printf ("gen_hard_reg_clobber (%smode, %i)", + GET_MODE_NAME (GET_MODE (XEXP (x, 0))), + REGNO (XEXP (x, 0))); return; } break; - + case CLOBBER_HIGH: + if (!REG_P (XEXP (x, 0))) + error ("CLOBBER_HIGH argument is not a register expr, at %s:%d", + info->loc.filename, info->loc.lineno); + printf ("gen_hard_reg_clobber_high (%smode, %i)", + GET_MODE_NAME (GET_MODE (XEXP (x, 0))), + REGNO (XEXP (x, 0))); + return; + break; case CC0: printf ("cc0_rtx"); return; @@ -224,7 +233,7 @@ gen_exp (rtx x, enum rtx_code subroutine_type, char *used) switch (fmt[i]) { case 'e': case 'u': - gen_exp (XEXP (x, i), subroutine_type, used); + gen_exp (XEXP (x, i), subroutine_type, used, info); break; case 'i': @@ -252,7 +261,7 @@ gen_exp (rtx x, enum rtx_code subroutine_type, char *used) for (j = 0; j < XVECLEN (x, i); j++) { printf (",\n\t\t"); - gen_exp (XVECEXP (x, i, j), subroutine_type, used); + gen_exp (XVECEXP (x, i, j), subroutine_type, used, info); } printf (")"); break; @@ -270,7 +279,7 @@ gen_exp (rtx x, enum rtx_code subroutine_type, char *used) becoming a separate instruction. USED is as for gen_exp. */ static void -gen_emit_seq (rtvec vec, char *used) +gen_emit_seq (rtvec vec, char *used, md_rtx_info *info) { for (int i = 0, len = GET_NUM_ELEM (vec); i < len; ++i) { @@ -279,7 +288,7 @@ gen_emit_seq (rtvec vec, char *used) if (const char *name = get_emit_function (next)) { printf (" %s (", name); - gen_exp (next, DEFINE_EXPAND, used); + gen_exp (next, DEFINE_EXPAND, used, info); printf (");\n"); if (!last_p && needs_barrier_p (next)) printf (" emit_barrier ();"); @@ -287,7 +296,7 @@ gen_emit_seq (rtvec vec, char *used) else { printf (" emit ("); - gen_exp (next, DEFINE_EXPAND, used); + gen_exp (next, DEFINE_EXPAND, used, info); printf (", %s);\n", last_p ? "false" : "true"); } } @@ -334,7 +343,8 @@ gen_insn (md_rtx_info *info) for (i = XVECLEN (insn, 1) - 1; i > 0; i--) { - if (GET_CODE (XVECEXP (insn, 1, i)) != CLOBBER) + if (GET_CODE (XVECEXP (insn, 1, i)) != CLOBBER + && GET_CODE (XVECEXP (insn, 1, i)) != CLOBBER_HIGH) break; if (REG_P (XEXP (XVECEXP (insn, 1, i), 0))) @@ -368,7 +378,8 @@ gen_insn (md_rtx_info *info) /* OLD and NEW_INSN are the same if both are to be a SCRATCH of the same mode, or if both are registers of the same mode and number. */ - if (! (GET_MODE (old_rtx) == GET_MODE (new_rtx) + if (! (GET_CODE (old_rtx) == GET_CODE (new_rtx) + && GET_MODE (old_rtx) == GET_MODE (new_rtx) && ((GET_CODE (old_rtx) == MATCH_SCRATCH && GET_CODE (new_rtx) == MATCH_SCRATCH) || (REG_P (old_rtx) && REG_P (new_rtx) @@ -431,7 +442,7 @@ gen_insn (md_rtx_info *info) ? NULL : XCNEWVEC (char, stats.num_generator_args)); printf (" return "); - gen_exp (pattern, DEFINE_INSN, used); + gen_exp (pattern, DEFINE_INSN, used, info); printf (";\n}\n\n"); XDELETEVEC (used); } @@ -480,7 +491,7 @@ gen_expand (md_rtx_info *info) && XVECLEN (expand, 1) == 1) { printf (" return "); - gen_exp (XVECEXP (expand, 1, 0), DEFINE_EXPAND, NULL); + gen_exp (XVECEXP (expand, 1, 0), DEFINE_EXPAND, NULL, info); printf (";\n}\n\n"); return; } @@ -534,7 +545,7 @@ gen_expand (md_rtx_info *info) } used = XCNEWVEC (char, stats.num_operand_vars); - gen_emit_seq (XVEC (expand, 1), used); + gen_emit_seq (XVEC (expand, 1), used, info); XDELETEVEC (used); /* Call `get_insns' to extract the list of all the @@ -617,7 +628,7 @@ gen_split (md_rtx_info *info) printf (" (void) operand%d;\n", i); } - gen_emit_seq (XVEC (split, 2), used); + gen_emit_seq (XVEC (split, 2), used, info); /* Call `get_insns' to make a list of all the insns emitted within this gen_... function. */ @@ -634,7 +645,7 @@ gen_split (md_rtx_info *info) the end of the vector. */ static void -output_add_clobbers (void) +output_add_clobbers (md_rtx_info *info) { struct clobber_pat *clobber; struct clobber_ent *ent; @@ -654,7 +665,7 @@ output_add_clobbers (void) { printf (" XVECEXP (pattern, 0, %d) = ", i); gen_exp (XVECEXP (clobber->pattern, 1, i), - GET_CODE (clobber->pattern), NULL); + GET_CODE (clobber->pattern), NULL, info); printf (";\n"); } @@ -837,7 +848,7 @@ from the machine description file `md'. */\n\n"); /* Write out the routines to add CLOBBERs to a pattern and say whether they clobber a hard reg. */ - output_add_clobbers (); + output_add_clobbers (&info); output_added_clobbers_hard_reg_p (); fflush (stdout); diff --git a/gcc/genextract.c b/gcc/genextract.c index 258d234d2729bf16b152b90bb1833a37a6eb0bdc..e1fb716e459b9bd219e89cf36c30556d520305a2 100644 --- a/gcc/genextract.c +++ b/gcc/genextract.c @@ -33,9 +33,10 @@ along with GCC; see the file COPYING3. If not see The string for each operand describes that path to the operand and contains `0' through `9' when going into an expression and `a' through - `z' when going into a vector. We assume here that only the first operand - of an rtl expression is a vector. genrecog.c makes the same assumption - (and uses the same representation) and it is currently true. */ + `z' then 'A' through to 'Z' when going into a vector. We assume here that + only the first operand of an rtl expression is a vector. genrecog.c makes + the same assumption (and uses the same representation) and it is currently + true. */ typedef char *locstr; @@ -80,6 +81,22 @@ struct accum_extract /* Forward declarations. */ static void walk_rtx (md_rtx_info *, rtx, struct accum_extract *); +#define UPPER_OFFSET ('A' - ('z' - 'a' + 1)) + +/* Convert OPERAND into a character - either into [a-zA-Z] for vector operands + or [0-9] for integer operands - and push onto the end of the path ACC. */ +static void +push_pathstr_operand (int operand, bool is_vector, + struct accum_extract *acc) +{ + if (is_vector && 'a' + operand > 'z') + acc->pathstr.safe_push (operand + UPPER_OFFSET); + else if (is_vector) + acc->pathstr.safe_push (operand + 'a'); + else + acc->pathstr.safe_push (operand + '0'); +} + static void gen_insn (md_rtx_info *info) { @@ -98,7 +115,7 @@ gen_insn (md_rtx_info *info) else for (i = XVECLEN (insn, 1) - 1; i >= 0; i--) { - acc.pathstr.safe_push ('a' + i); + push_pathstr_operand (i, true, &acc); walk_rtx (info, XVECEXP (insn, 1, i), &acc); acc.pathstr.pop (); } @@ -208,7 +225,7 @@ static void walk_rtx (md_rtx_info *info, rtx x, struct accum_extract *acc) { RTX_CODE code; - int i, len, base; + int i, len; const char *fmt; if (x == 0) @@ -234,10 +251,9 @@ walk_rtx (md_rtx_info *info, rtx x, struct accum_extract *acc) VEC_safe_set_locstr (info, &acc->oplocs, XINT (x, 0), VEC_char_to_string (acc->pathstr)); - base = (code == MATCH_OPERATOR ? '0' : 'a'); for (i = XVECLEN (x, 2) - 1; i >= 0; i--) { - acc->pathstr.safe_push (base + i); + push_pathstr_operand (i, code != MATCH_OPERATOR, acc); walk_rtx (info, XVECEXP (x, 2, i), acc); acc->pathstr.pop (); } @@ -252,10 +268,9 @@ walk_rtx (md_rtx_info *info, rtx x, struct accum_extract *acc) if (code == MATCH_DUP) break; - base = (code == MATCH_OP_DUP ? '0' : 'a'); for (i = XVECLEN (x, 1) - 1; i >= 0; i--) { - acc->pathstr.safe_push (base + i); + push_pathstr_operand (i, code != MATCH_OP_DUP, acc); walk_rtx (info, XVECEXP (x, 1, i), acc); acc->pathstr.pop (); } @@ -271,7 +286,7 @@ walk_rtx (md_rtx_info *info, rtx x, struct accum_extract *acc) { if (fmt[i] == 'e' || fmt[i] == 'u') { - acc->pathstr.safe_push ('0' + i); + push_pathstr_operand (i, false, acc); walk_rtx (info, XEXP (x, i), acc); acc->pathstr.pop (); } @@ -280,7 +295,7 @@ walk_rtx (md_rtx_info *info, rtx x, struct accum_extract *acc) int j; for (j = XVECLEN (x, i) - 1; j >= 0; j--) { - acc->pathstr.safe_push ('a' + j); + push_pathstr_operand (j, true, acc); walk_rtx (info, XVECEXP (x, i, j), acc); acc->pathstr.pop (); } @@ -311,7 +326,7 @@ print_path (const char *path) for (i = len - 1; i >= 0 ; i--) { - if (ISLOWER (path[i])) + if (ISLOWER (path[i]) || ISUPPER (path[i])) fputs ("XVECEXP (", stdout); else if (ISDIGIT (path[i])) fputs ("XEXP (", stdout); @@ -323,7 +338,9 @@ print_path (const char *path) for (i = 0; i < len; i++) { - if (ISLOWER (path[i])) + if (ISUPPER (path[i])) + printf (", 0, %d)", path[i] - UPPER_OFFSET); + else if (ISLOWER (path[i])) printf (", 0, %d)", path[i] - 'a'); else if (ISDIGIT (path[i])) printf (", %d)", path[i] - '0'); diff --git a/gcc/genrecog.c b/gcc/genrecog.c index 695383badab47f8492df380caad0ce371207bce4..cdbe575938367a6e3387e17d45e4fafa21d30fa4 100644 --- a/gcc/genrecog.c +++ b/gcc/genrecog.c @@ -718,6 +718,7 @@ validate_pattern (rtx pattern, md_rtx_info *info, rtx set, int set_code) } case CLOBBER: + case CLOBBER_HIGH: validate_pattern (SET_DEST (pattern), info, pattern, '='); return; @@ -5294,7 +5295,7 @@ remove_clobbers (acceptance_type *acceptance_ptr, rtx *pattern_ptr) for (i = XVECLEN (pattern, 0); i > 0; i--) { rtx x = XVECEXP (pattern, 0, i - 1); - if (GET_CODE (x) != CLOBBER + if ((GET_CODE (x) != CLOBBER && GET_CODE (x) != CLOBBER_HIGH) || (!REG_P (XEXP (x, 0)) && GET_CODE (XEXP (x, 0)) != MATCH_SCRATCH)) break; diff --git a/gcc/rtl.h b/gcc/rtl.h index 71621bdfd67c4ce3dcccc5279456cae841371f97..bdb05d00120e7fadeb7f2d29bd67afc7a77262c1 100644 --- a/gcc/rtl.h +++ b/gcc/rtl.h @@ -4193,6 +4193,7 @@ extern void vt_equate_reg_base_value (const_rtx, const_rtx); extern bool memory_modified_in_insn_p (const_rtx, const_rtx); extern bool may_be_sp_based_p (rtx); extern rtx gen_hard_reg_clobber (machine_mode, unsigned int); +extern rtx gen_hard_reg_clobber_high (machine_mode, unsigned int); extern rtx get_reg_known_value (unsigned int); extern bool get_reg_known_equiv_p (unsigned int); extern rtx get_reg_base_value (unsigned int); From patchwork Thu Nov 16 12:34:50 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alan Hayward X-Patchwork-Id: 838535 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-466986-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="JXxtO46Y"; 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DIR:OUT; SFP:1101; SCL:1; SRVR:AM3PR08MB0103; H:AM3PR08MB0101.eurprd08.prod.outlook.com; FPR:; SPF:None; PTR:InfoNoRecords; A:1; MX:1; LANG:en; received-spf: None (protection.outlook.com: arm.com does not designate permitted sender hosts) spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM Content-ID: MIME-Version: 1.0 X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-Network-Message-Id: b1c5db48-72fb-443d-af97-08d52cee6e52 X-MS-Exchange-CrossTenant-originalarrivaltime: 16 Nov 2017 12:34:50.6294 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM3PR08MB0103 This patch adds the function reg_is_clobbered_by_clobber_high. Given a CLOBBER_HIGH expression and a register, it checks if the register will be clobbered. A second version exists for the cases where the expressions are not available. The function will be used throughout the following patches. Alan. 2017-11-16 Alan Hayward * rtl.h (reg_is_clobbered_by_clobber_high): Add declarations. * rtlanal.c (reg_is_clobbered_by_clobber_high): Add function. diff --git a/gcc/rtl.h b/gcc/rtl.h index bdb05d00120e7fadeb7f2d29bd67afc7a77262c1..5a85eb42ea4455cf3a975b3adbdb9d0415441d3b 100644 --- a/gcc/rtl.h +++ b/gcc/rtl.h @@ -3417,6 +3417,16 @@ extern bool tablejump_p (const rtx_insn *, rtx_insn **, rtx_jump_table_data **); extern int computed_jump_p (const rtx_insn *); extern bool tls_referenced_p (const_rtx); extern bool contains_mem_rtx_p (rtx x); +extern bool reg_is_clobbered_by_clobber_high (unsigned int, machine_mode, + const_rtx); + +/* Convenient wrapper for reg_is_clobbered_by_clobber_high. */ +inline bool +reg_is_clobbered_by_clobber_high (const_rtx x, const_rtx clobber_high_op) +{ + return reg_is_clobbered_by_clobber_high (REGNO (x), GET_MODE (x), + clobber_high_op); +} /* Overload for refers_to_regno_p for checking a single register. */ inline bool diff --git a/gcc/rtlanal.c b/gcc/rtlanal.c index 79a5ae197c14ba338240123f2fc912f2ea60e178..923e3314d25c05f9055907c61b4a24186701cc23 100644 --- a/gcc/rtlanal.c +++ b/gcc/rtlanal.c @@ -6519,3 +6519,32 @@ tls_referenced_p (const_rtx x) return true; return false; } + +/* Return true if reg REGNO with mode REG_MODE would be clobbered by the + clobber_high operand in CLOBBER_HIGH_OP. */ + +bool +reg_is_clobbered_by_clobber_high (unsigned int regno, machine_mode reg_mode, + const_rtx clobber_high_op) +{ + unsigned int clobber_regno = REGNO (clobber_high_op); + machine_mode clobber_mode = GET_MODE (clobber_high_op); + unsigned char regno_nregs = hard_regno_nregs (regno, reg_mode); + + /* Clobber high should always span exactly one register. */ + gcc_assert (REG_NREGS (clobber_high_op) == 1); + + /* Clobber high needs to match with one of the registers in X. */ + if (clobber_regno < regno || clobber_regno >= regno + regno_nregs) + return false; + + gcc_assert (reg_mode != BLKmode && clobber_mode != BLKmode); + + if (reg_mode == VOIDmode) + return clobber_mode != VOIDmode; + + /* Clobber high will clobber if its size might be greater than the size of + register regno. */ + return may_gt (exact_div (GET_MODE_SIZE (reg_mode), regno_nregs), + GET_MODE_SIZE (clobber_mode)); +} From patchwork Thu Nov 16 12:35:00 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alan Hayward X-Patchwork-Id: 838536 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-466987-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="Ptq8SaO+"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3yd11N2c4Tz9ryT for ; Thu, 16 Nov 2017 23:35:36 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; 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Thu, 16 Nov 2017 12:35:01 +0000 From: Alan Hayward To: "gcc-patches@gcc.gnu.org" CC: nd Subject: [PATCH 4/7]: lra support for clobber_high Date: Thu, 16 Nov 2017 12:35:00 +0000 Message-ID: <143B2962-4720-42FC-9176-17786E5C0524@arm.com> authentication-results: spf=none (sender IP is ) smtp.mailfrom=Alan.Hayward@arm.com; x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; AM3PR08MB0103; 6:FI/RVJlqxwVH7pH90xhaZrJtL/xqiqm7IYZ2uG+ejmb2Mybt7RP5h5f59z7S40IjkAR+3vk869nrdJE9hdlmy7zXlhZqd5PuOB9LCut5KPv37P8AEgHp01x9IrtiCvqlOJEbmtn1mSbnA5KpJYRUoLKA5IO8mpwN9fZL+TQyjIazbjPLze9ikUbAgDAf84TmkPsfxVd/u/G01xOztUgyDHedMYrvBtiV5fX3p9Qbi8Xy3MjGSm+g9GyzjCD9Hul4KT11Rnk4lx6A8mSYtucIblYI1DYvOu0MoBG38WT/GDN+ohC0KDpwQhm9RWyH81JK5RCOlJsNYKhqYU9ku8o/tu76Oq0QwHwz2rBsyQyt+lw=; 5:N6+089JDIz2cgqgL7i+uNhTP2INJpnN6WDEZyfVg/5jhUWe0irttoK9r8BHqpq0O3qycZ8i2JqAa1O8qcdvQa3IhLskWgssJltrSv1zhyy124lkYmAfaPPIIG9ToL0hKF9waMqG6F1o6SO8XUJKjw8B/EwGkEAmN8XPoIGw1A4U=; 24:7WAZ4MBiLuARjTANGym09VsvNck5pnqRf7/Fr5BeEDOOWt8VLR7Ll+s81VxEML9qk28MUMsI+7OgTM0DdhuYat3C5VPZKp2WCs8kP1QwU/8=; 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received-spf: None (protection.outlook.com: arm.com does not designate permitted sender hosts) spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM Content-ID: <56C0FC2A0494CF438E4F59F1BA84B4E3@eurprd08.prod.outlook.com> MIME-Version: 1.0 X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-Network-Message-Id: 907f3398-0967-42da-d576-08d52cee7475 X-MS-Exchange-CrossTenant-originalarrivaltime: 16 Nov 2017 12:35:00.9104 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM3PR08MB0103 This patch simply adds the lra specific changes for clobber_high. Alan. 2017-11-16 Alan Hayward * lra-eliminations.c (lra_eliminate_regs_1): Check for clobber high. (mark_not_eliminable): Likewise. * lra-int.h (struct lra_insn_reg): Add clobber high marker. * lra-lives.c (process_bb_lives): Check for clobber high. * lra.c (new_insn_reg): Remember clobber highs. (collect_non_operand_hard_regs): Check for clobber high. (lra_set_insn_recog_data): Likewise. (add_regs_to_insn_regno_info): Likewise. (lra_update_insn_regno_info): Likewise. diff --git a/gcc/lra-eliminations.c b/gcc/lra-eliminations.c index bea8b023b7cb7a512f7482a2f014647c30462870..251e539530456722e3f4231b928c2124f9d602b6 100644 --- a/gcc/lra-eliminations.c +++ b/gcc/lra-eliminations.c @@ -654,6 +654,7 @@ lra_eliminate_regs_1 (rtx_insn *insn, rtx x, machine_mode mem_mode, return x; case CLOBBER: + case CLOBBER_HIGH: case SET: gcc_unreachable (); @@ -806,6 +807,16 @@ mark_not_eliminable (rtx x, machine_mode mem_mode) setup_can_eliminate (ep, false); return; + case CLOBBER_HIGH: + gcc_assert (REG_P (XEXP (x, 0))); + gcc_assert (REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER); + for (ep = reg_eliminate; + ep < ®_eliminate[NUM_ELIMINABLE_REGS]; + ep++) + if (reg_is_clobbered_by_clobber_high (ep->to_rtx, XEXP (x, 0))) + setup_can_eliminate (ep, false); + return; + case SET: if (SET_DEST (x) == stack_pointer_rtx && GET_CODE (SET_SRC (x)) == PLUS diff --git a/gcc/lra-int.h b/gcc/lra-int.h index 6c219eacee3940054ed480a44cda1ed07993ad16..be439b95e9cedb358e9ba6c63f8a9490af5c816d 100644 --- a/gcc/lra-int.h +++ b/gcc/lra-int.h @@ -166,6 +166,8 @@ struct lra_insn_reg /* True if there is an early clobber alternative for this operand. */ unsigned int early_clobber : 1; + /* True if the reg is clobber highed by the operand. */ + unsigned int clobber_high : 1; /* The corresponding regno of the register. */ int regno; /* Next reg info of the same insn. */ diff --git a/gcc/lra-lives.c b/gcc/lra-lives.c index df7e2537dd09a4abd5ce517f4bb556cc32000fa0..82a1811f837b425a326753c0d956149382d752cb 100644 --- a/gcc/lra-lives.c +++ b/gcc/lra-lives.c @@ -655,7 +655,7 @@ process_bb_lives (basic_block bb, int &curr_point, bool dead_insn_p) bool call_p; int n_alt, dst_regno, src_regno; rtx set; - struct lra_insn_reg *reg; + struct lra_insn_reg *reg, *hr; if (!NONDEBUG_INSN_P (curr_insn)) continue; @@ -687,11 +687,12 @@ process_bb_lives (basic_block bb, int &curr_point, bool dead_insn_p) break; } for (reg = curr_static_id->hard_regs; reg != NULL; reg = reg->next) - if (reg->type != OP_IN) + if (reg->type != OP_IN && !reg->clobber_high) { remove_p = false; break; } + if (remove_p && ! volatile_refs_p (PATTERN (curr_insn))) { dst_regno = REGNO (SET_DEST (set)); @@ -809,14 +810,24 @@ process_bb_lives (basic_block bb, int &curr_point, bool dead_insn_p) unused values because they still conflict with quantities that are live at the time of the definition. */ for (reg = curr_id->regs; reg != NULL; reg = reg->next) - if (reg->type != OP_IN) - { - need_curr_point_incr - |= mark_regno_live (reg->regno, reg->biggest_mode, - curr_point); - check_pseudos_live_through_calls (reg->regno, - last_call_used_reg_set); - } + { + if (reg->type != OP_IN) + { + need_curr_point_incr + |= mark_regno_live (reg->regno, reg->biggest_mode, + curr_point); + check_pseudos_live_through_calls (reg->regno, + last_call_used_reg_set); + } + + if (reg->regno >= FIRST_PSEUDO_REGISTER) + for (hr = curr_static_id->hard_regs; hr != NULL; hr = hr->next) + if (hr->clobber_high + && may_gt (GET_MODE_SIZE (PSEUDO_REGNO_MODE (reg->regno)), + GET_MODE_SIZE (hr->biggest_mode))) + SET_HARD_REG_BIT (lra_reg_info[reg->regno].conflict_hard_regs, + hr->regno); + } for (reg = curr_static_id->hard_regs; reg != NULL; reg = reg->next) if (reg->type != OP_IN) diff --git a/gcc/lra.c b/gcc/lra.c index 8d44c75b0b4f89ff9fe94d0b8dfb2e77d43fee26..d6775d629655700484760ab85f78b9fd16189ca0 100644 --- a/gcc/lra.c +++ b/gcc/lra.c @@ -535,13 +535,14 @@ object_allocator lra_insn_reg_pool ("insn regs"); clobbered in the insn (EARLY_CLOBBER), and reference to the next insn reg info (NEXT). If REGNO can be early clobbered, alternatives in which it can be early clobbered are given by - EARLY_CLOBBER_ALTS. */ + EARLY_CLOBBER_ALTS. CLOBBER_HIGH marks if reference is a clobber + high. */ static struct lra_insn_reg * new_insn_reg (rtx_insn *insn, int regno, enum op_type type, machine_mode mode, bool subreg_p, bool early_clobber, alternative_mask early_clobber_alts, - struct lra_insn_reg *next) + struct lra_insn_reg *next, bool clobber_high) { lra_insn_reg *ir = lra_insn_reg_pool.allocate (); ir->type = type; @@ -552,6 +553,7 @@ new_insn_reg (rtx_insn *insn, int regno, enum op_type type, ir->subreg_p = subreg_p; ir->early_clobber = early_clobber; ir->early_clobber_alts = early_clobber_alts; + ir->clobber_high = clobber_high; ir->regno = regno; ir->next = next; return ir; @@ -805,11 +807,12 @@ setup_operand_alternative (lra_insn_recog_data_t data, not the insn operands, in X with TYPE (in/out/inout) and flag that it is early clobbered in the insn (EARLY_CLOBBER) and add the info to LIST. X is a part of insn given by DATA. Return the result - list. */ + list. CLOBBER_HIGH marks if X is a clobber high. */ static struct lra_insn_reg * collect_non_operand_hard_regs (rtx *x, lra_insn_recog_data_t data, struct lra_insn_reg *list, - enum op_type type, bool early_clobber) + enum op_type type, bool early_clobber, + bool clobber_high) { int i, j, regno, last; bool subreg_p; @@ -873,7 +876,8 @@ collect_non_operand_hard_regs (rtx *x, lra_insn_recog_data_t data, #endif list = new_insn_reg (data->insn, regno, type, mode, subreg_p, early_clobber, - early_clobber ? ALL_ALTERNATIVES : 0, list); + early_clobber ? ALL_ALTERNATIVES : 0, list, + clobber_high); } } return list; @@ -882,25 +886,32 @@ collect_non_operand_hard_regs (rtx *x, lra_insn_recog_data_t data, { case SET: list = collect_non_operand_hard_regs (&SET_DEST (op), data, - list, OP_OUT, false); + list, OP_OUT, false, false); list = collect_non_operand_hard_regs (&SET_SRC (op), data, - list, OP_IN, false); + list, OP_IN, false, false); break; case CLOBBER: /* We treat clobber of non-operand hard registers as early clobber (the behavior is expected from asm). */ list = collect_non_operand_hard_regs (&XEXP (op, 0), data, - list, OP_OUT, true); + list, OP_OUT, true, false); + break; + case CLOBBER_HIGH: + /* Clobber high should always span exactly one register. */ + gcc_assert (REG_NREGS (XEXP (op, 0)) == 1); + /* We treat clobber of non-operand hard registers as early clobber. */ + list = collect_non_operand_hard_regs (&XEXP (op, 0), data, + list, OP_OUT, true, true); break; case PRE_INC: case PRE_DEC: case POST_INC: case POST_DEC: list = collect_non_operand_hard_regs (&XEXP (op, 0), data, - list, OP_INOUT, false); + list, OP_INOUT, false, false); break; case PRE_MODIFY: case POST_MODIFY: list = collect_non_operand_hard_regs (&XEXP (op, 0), data, - list, OP_INOUT, false); + list, OP_INOUT, false, false); list = collect_non_operand_hard_regs (&XEXP (op, 1), data, - list, OP_IN, false); + list, OP_IN, false, false); break; default: fmt = GET_RTX_FORMAT (code); @@ -908,11 +919,11 @@ collect_non_operand_hard_regs (rtx *x, lra_insn_recog_data_t data, { if (fmt[i] == 'e') list = collect_non_operand_hard_regs (&XEXP (op, i), data, - list, OP_IN, false); + list, OP_IN, false, false); else if (fmt[i] == 'E') for (j = XVECLEN (op, i) - 1; j >= 0; j--) list = collect_non_operand_hard_regs (&XVECEXP (op, i, j), data, - list, OP_IN, false); + list, OP_IN, false, false); } } return list; @@ -1056,7 +1067,7 @@ lra_set_insn_recog_data (rtx_insn *insn) else insn_static_data->hard_regs = collect_non_operand_hard_regs (&PATTERN (insn), data, - NULL, OP_IN, false); + NULL, OP_IN, false, false); data->arg_hard_regs = NULL; if (CALL_P (insn)) { @@ -1082,6 +1093,11 @@ lra_set_insn_recog_data (rtx_insn *insn) arg_hard_regs[n_hard_regs++] = regno + i + (use_p ? 0 : FIRST_PSEUDO_REGISTER); } + else if (GET_CODE (XEXP (link, 0)) == CLOBBER_HIGH) + /* We could support CLOBBER_HIGH and treat it in the same way as + HARD_REGNO_CALL_PART_CLOBBERED, but no port needs that yet. */ + gcc_unreachable (); + if (n_hard_regs != 0) { arg_hard_regs[n_hard_regs++] = -1; @@ -1440,7 +1456,7 @@ add_regs_to_insn_regno_info (lra_insn_recog_data_t data, rtx x, int uid, { data->regs = new_insn_reg (data->insn, regno, type, mode, subreg_p, early_clobber, early_clobber_alts, - data->regs); + data->regs, false); return; } else @@ -1453,7 +1469,8 @@ add_regs_to_insn_regno_info (lra_insn_recog_data_t data, rtx x, int uid, structure. */ data->regs = new_insn_reg (data->insn, regno, type, mode, subreg_p, early_clobber, - early_clobber_alts, data->regs); + early_clobber_alts, data->regs, + false); else { if (curr->type != type) @@ -1479,6 +1496,8 @@ add_regs_to_insn_regno_info (lra_insn_recog_data_t data, rtx x, int uid, clobber (the behavior is expected from asm). */ add_regs_to_insn_regno_info (data, XEXP (x, 0), uid, OP_OUT, true, ALL_ALTERNATIVES); break; + case CLOBBER_HIGH: + gcc_unreachable (); case PRE_INC: case PRE_DEC: case POST_INC: case POST_DEC: add_regs_to_insn_regno_info (data, XEXP (x, 0), uid, OP_INOUT, false, 0); break; @@ -1614,10 +1633,16 @@ lra_update_insn_regno_info (rtx_insn *insn) for (link = CALL_INSN_FUNCTION_USAGE (insn); link != NULL_RTX; link = XEXP (link, 1)) - if (((code = GET_CODE (XEXP (link, 0))) == USE || code == CLOBBER) + { + code = GET_CODE (XEXP (link, 0)); + /* We could support CLOBBER_HIGH and treat it in the same way as + HARD_REGNO_CALL_PART_CLOBBERED, but no port needs that yet. */ + gcc_assert (code != CLOBBER_HIGH); + if ((code == USE || code == CLOBBER) && MEM_P (XEXP (XEXP (link, 0), 0))) - add_regs_to_insn_regno_info (data, XEXP (XEXP (link, 0), 0), uid, - code == USE ? OP_IN : OP_OUT, false, 0); + add_regs_to_insn_regno_info (data, XEXP (XEXP (link, 0), 0), uid, + code == USE ? OP_IN : OP_OUT, false, 0); + } if (NONDEBUG_INSN_P (insn)) setup_insn_reg_info (data, freq); } From patchwork Thu Nov 16 12:35:25 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alan Hayward X-Patchwork-Id: 838537 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-466988-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="DzN3GY02"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3yd11j0bBBz9ryT for ; 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received-spf: None (protection.outlook.com: arm.com does not designate permitted sender hosts) spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM Content-ID: <8739D4B29C1F4F4C9C6B89A93B1C37B0@eurprd08.prod.outlook.com> MIME-Version: 1.0 X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-Network-Message-Id: 993aa1c2-87b2-45a0-031a-08d52cee8309 X-MS-Exchange-CrossTenant-originalarrivaltime: 16 Nov 2017 12:35:25.3944 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM3PR08MB0103 This patch simply adds the cse specific changes for clobber_high. Alan. 2017-11-16 Alan Hayward * cse.c (invalidate_reg): New function extracted from... (invalidate): ...here. (canonicalize_insn): Check for clobber high. (invalidate_from_clobbers): invalidate clobber highs. (invalidate_from_sets_and_clobbers): Likewise. (count_reg_usage): Check for clobber high. (insn_live_p): Likewise. * cselib.c (cselib_expand_value_rtx_1):Likewise. (cselib_invalidate_regno): Check for clobber in setter. (cselib_invalidate_rtx): Pass through setter. (cselib_invalidate_rtx_note_stores): (cselib_process_insn): Check for clobber high. * cselib.h (cselib_invalidate_rtx): Add operand. diff --git a/gcc/cse.c b/gcc/cse.c index e3c0710215df0acca924ce74ffa54582125d0136..f15ae8693fbb243323dd049e21648a49546a4608 100644 --- a/gcc/cse.c +++ b/gcc/cse.c @@ -559,6 +559,7 @@ static struct table_elt *insert_with_costs (rtx, struct table_elt *, unsigned, static struct table_elt *insert (rtx, struct table_elt *, unsigned, machine_mode); static void merge_equiv_classes (struct table_elt *, struct table_elt *); +static void invalidate_reg (rtx, bool); static void invalidate (rtx, machine_mode); static void remove_invalid_refs (unsigned int); static void remove_invalid_subreg_refs (unsigned int, poly_uint64, @@ -1818,7 +1819,85 @@ check_dependence (const_rtx x, rtx exp, machine_mode mode, rtx addr) } return false; } - + +/* Remove from the hash table, or mark as invalid, all expressions whose + values could be altered by storing in register X. + + CLOBBER_HIGH is set if X was part of a CLOBBER_HIGH expression. */ + +static void +invalidate_reg (rtx x, bool clobber_high) +{ + gcc_assert (GET_CODE (x) == REG); + + /* If X is a register, dependencies on its contents are recorded + through the qty number mechanism. Just change the qty number of + the register, mark it as invalid for expressions that refer to it, + and remove it itself. */ + unsigned int regno = REGNO (x); + unsigned int hash = HASH (x, GET_MODE (x)); + + /* Remove REGNO from any quantity list it might be on and indicate + that its value might have changed. If it is a pseudo, remove its + entry from the hash table. + + For a hard register, we do the first two actions above for any + additional hard registers corresponding to X. Then, if any of these + registers are in the table, we must remove any REG entries that + overlap these registers. */ + + delete_reg_equiv (regno); + REG_TICK (regno)++; + SUBREG_TICKED (regno) = -1; + + if (regno >= FIRST_PSEUDO_REGISTER) + { + gcc_assert (!clobber_high); + remove_pseudo_from_table (x, hash); + } + else + { + HOST_WIDE_INT in_table = TEST_HARD_REG_BIT (hard_regs_in_table, regno); + unsigned int endregno = END_REGNO (x); + unsigned int rn; + struct table_elt *p, *next; + + CLEAR_HARD_REG_BIT (hard_regs_in_table, regno); + + for (rn = regno + 1; rn < endregno; rn++) + { + in_table |= TEST_HARD_REG_BIT (hard_regs_in_table, rn); + CLEAR_HARD_REG_BIT (hard_regs_in_table, rn); + delete_reg_equiv (rn); + REG_TICK (rn)++; + SUBREG_TICKED (rn) = -1; + } + + if (in_table) + for (hash = 0; hash < HASH_SIZE; hash++) + for (p = table[hash]; p; p = next) + { + next = p->next_same_hash; + + if (!REG_P (p->exp) || REGNO (p->exp) >= FIRST_PSEUDO_REGISTER) + continue; + + if (clobber_high) + { + if (reg_is_clobbered_by_clobber_high (p->exp, x)) + remove_from_table (p, hash); + } + else + { + unsigned int tregno = REGNO (p->exp); + unsigned int tendregno = END_REGNO (p->exp); + if (tendregno > regno && tregno < endregno) + remove_from_table (p, hash); + } + } + } +} + /* Remove from the hash table, or mark as invalid, all expressions whose values could be altered by storing in X. X is a register, a subreg, or a memory reference with nonvarying address (because, when a memory @@ -1841,65 +1920,7 @@ invalidate (rtx x, machine_mode full_mode) switch (GET_CODE (x)) { case REG: - { - /* If X is a register, dependencies on its contents are recorded - through the qty number mechanism. Just change the qty number of - the register, mark it as invalid for expressions that refer to it, - and remove it itself. */ - unsigned int regno = REGNO (x); - unsigned int hash = HASH (x, GET_MODE (x)); - - /* Remove REGNO from any quantity list it might be on and indicate - that its value might have changed. If it is a pseudo, remove its - entry from the hash table. - - For a hard register, we do the first two actions above for any - additional hard registers corresponding to X. Then, if any of these - registers are in the table, we must remove any REG entries that - overlap these registers. */ - - delete_reg_equiv (regno); - REG_TICK (regno)++; - SUBREG_TICKED (regno) = -1; - - if (regno >= FIRST_PSEUDO_REGISTER) - remove_pseudo_from_table (x, hash); - else - { - HOST_WIDE_INT in_table - = TEST_HARD_REG_BIT (hard_regs_in_table, regno); - unsigned int endregno = END_REGNO (x); - unsigned int tregno, tendregno, rn; - struct table_elt *p, *next; - - CLEAR_HARD_REG_BIT (hard_regs_in_table, regno); - - for (rn = regno + 1; rn < endregno; rn++) - { - in_table |= TEST_HARD_REG_BIT (hard_regs_in_table, rn); - CLEAR_HARD_REG_BIT (hard_regs_in_table, rn); - delete_reg_equiv (rn); - REG_TICK (rn)++; - SUBREG_TICKED (rn) = -1; - } - - if (in_table) - for (hash = 0; hash < HASH_SIZE; hash++) - for (p = table[hash]; p; p = next) - { - next = p->next_same_hash; - - if (!REG_P (p->exp) - || REGNO (p->exp) >= FIRST_PSEUDO_REGISTER) - continue; - - tregno = REGNO (p->exp); - tendregno = END_REGNO (p->exp); - if (tendregno > regno && tregno < endregno) - remove_from_table (p, hash); - } - } - } + invalidate_reg (x, false); return; case SUBREG: @@ -4391,6 +4412,8 @@ canonicalize_insn (rtx_insn *insn, struct set **psets, int n_sets) if (MEM_P (XEXP (x, 0))) canon_reg (XEXP (x, 0), insn); } + else if (GET_CODE (x) == CLOBBER_HIGH) + gcc_assert (REG_P (XEXP (x, 0))); else if (GET_CODE (x) == USE && ! (REG_P (XEXP (x, 0)) && REGNO (XEXP (x, 0)) < FIRST_PSEUDO_REGISTER)) @@ -4422,6 +4445,8 @@ canonicalize_insn (rtx_insn *insn, struct set **psets, int n_sets) if (MEM_P (XEXP (y, 0))) canon_reg (XEXP (y, 0), insn); } + else if (GET_CODE (y) == CLOBBER_HIGH) + gcc_assert (REG_P (XEXP (y, 0))); else if (GET_CODE (y) == USE && ! (REG_P (XEXP (y, 0)) && REGNO (XEXP (y, 0)) < FIRST_PSEUDO_REGISTER)) @@ -6122,6 +6147,12 @@ invalidate_from_clobbers (rtx_insn *insn) invalidate (XEXP (ref, 0), GET_MODE (ref)); } } + if (GET_CODE (x) == CLOBBER_HIGH) + { + rtx ref = XEXP (x, 0); + gcc_assert (REG_P (ref)); + invalidate_reg (ref, true); + } else if (GET_CODE (x) == PARALLEL) { int i; @@ -6138,6 +6169,12 @@ invalidate_from_clobbers (rtx_insn *insn) || GET_CODE (ref) == ZERO_EXTRACT) invalidate (XEXP (ref, 0), GET_MODE (ref)); } + else if (GET_CODE (y) == CLOBBER_HIGH) + { + rtx ref = XEXP (y, 0); + gcc_assert (REG_P (ref)); + invalidate_reg (ref, true); + } } } } @@ -6155,8 +6192,17 @@ invalidate_from_sets_and_clobbers (rtx_insn *insn) if (CALL_P (insn)) { for (tem = CALL_INSN_FUNCTION_USAGE (insn); tem; tem = XEXP (tem, 1)) - if (GET_CODE (XEXP (tem, 0)) == CLOBBER) - invalidate (SET_DEST (XEXP (tem, 0)), VOIDmode); + { + rtx temx = XEXP (tem, 0); + if (GET_CODE (temx) == CLOBBER) + invalidate (SET_DEST (temx), VOIDmode); + else if (GET_CODE (temx) == CLOBBER_HIGH) + { + rtx temref = XEXP (temx, 0); + gcc_assert (REG_P (temref)); + invalidate_reg (temref, true); + } + } } /* Ensure we invalidate the destination register of a CALL insn. @@ -6183,6 +6229,12 @@ invalidate_from_sets_and_clobbers (rtx_insn *insn) || GET_CODE (clobbered) == ZERO_EXTRACT) invalidate (XEXP (clobbered, 0), GET_MODE (clobbered)); } + else if (GET_CODE (y) == CLOBBER_HIGH) + { + rtx ref = XEXP (y, 0); + gcc_assert (REG_P (ref)); + invalidate_reg (ref, true); + } else if (GET_CODE (y) == SET && GET_CODE (SET_SRC (y)) == CALL) invalidate (SET_DEST (y), VOIDmode); } @@ -6842,6 +6894,10 @@ count_reg_usage (rtx x, int *counts, rtx dest, int incr) count_reg_usage (XEXP (XEXP (x, 0), 0), counts, NULL_RTX, incr); return; + case CLOBBER_HIGH: + gcc_assert (REG_P ((XEXP (x, 0)))); + return; + case SET: /* Unless we are setting a REG, count everything in SET_DEST. */ if (!REG_P (SET_DEST (x))) @@ -6894,7 +6950,8 @@ count_reg_usage (rtx x, int *counts, rtx dest, int incr) || (REG_NOTE_KIND (x) != REG_NONNEG && GET_CODE (XEXP (x,0)) == USE) /* FUNCTION_USAGE expression lists may include (CLOBBER (mem /u)), involving registers in the address. */ - || GET_CODE (XEXP (x, 0)) == CLOBBER) + || GET_CODE (XEXP (x, 0)) == CLOBBER + || GET_CODE (XEXP (x, 0)) == CLOBBER_HIGH) count_reg_usage (XEXP (x, 0), counts, NULL_RTX, incr); count_reg_usage (XEXP (x, 1), counts, NULL_RTX, incr); @@ -6978,7 +7035,9 @@ insn_live_p (rtx_insn *insn, int *counts) if (set_live_p (elt, insn, counts)) return true; } - else if (GET_CODE (elt) != CLOBBER && GET_CODE (elt) != USE) + else if (GET_CODE (elt) != CLOBBER + && GET_CODE (elt) != CLOBBER_HIGH + && GET_CODE (elt) != USE) return true; } return false; diff --git a/gcc/cselib.h b/gcc/cselib.h index dd949196b7d4a46f2b157ae3874241ee116d022d..ad4cce4ebbda1556124259be4d84edf410fb14cd 100644 --- a/gcc/cselib.h +++ b/gcc/cselib.h @@ -92,7 +92,7 @@ extern bool cselib_dummy_expand_value_rtx_cb (rtx, bitmap, int, cselib_expand_callback, void *); extern rtx cselib_subst_to_values (rtx, machine_mode); extern rtx cselib_subst_to_values_from_insn (rtx, machine_mode, rtx_insn *); -extern void cselib_invalidate_rtx (rtx); +extern void cselib_invalidate_rtx (rtx, const_rtx = NULL); extern void cselib_reset_table (unsigned int); extern unsigned int cselib_get_next_uid (void); diff --git a/gcc/cselib.c b/gcc/cselib.c index 9c8f206c909925c58f0ab1a14853caf738bbfc4f..92f91a463f2519b09545d0b050de5521427d4929 100644 --- a/gcc/cselib.c +++ b/gcc/cselib.c @@ -54,7 +54,8 @@ static unsigned int cselib_hash_rtx (rtx, int, machine_mode); static cselib_val *new_cselib_val (unsigned int, machine_mode, rtx); static void add_mem_for_addr (cselib_val *, cselib_val *, rtx); static cselib_val *cselib_lookup_mem (rtx, int); -static void cselib_invalidate_regno (unsigned int, machine_mode); +static void cselib_invalidate_regno (unsigned int, machine_mode, + const_rtx = NULL); static void cselib_invalidate_mem (rtx); static void cselib_record_set (rtx, cselib_val *, cselib_val *); static void cselib_record_sets (rtx_insn *); @@ -1661,6 +1662,7 @@ cselib_expand_value_rtx_1 (rtx orig, struct expand_value_data *evd, /* SCRATCH must be shared because they represent distinct values. */ return orig; case CLOBBER: + case CLOBBER_HIGH: if (REG_P (XEXP (orig, 0)) && HARD_REGISTER_NUM_P (REGNO (XEXP (orig, 0)))) return orig; break; @@ -2163,7 +2165,8 @@ cselib_lookup (rtx x, machine_mode mode, invalidating call clobbered registers across a call. */ static void -cselib_invalidate_regno (unsigned int regno, machine_mode mode) +cselib_invalidate_regno (unsigned int regno, machine_mode mode, + const_rtx setter) { unsigned int endregno; unsigned int i; @@ -2186,6 +2189,9 @@ cselib_invalidate_regno (unsigned int regno, machine_mode mode) i = regno - max_value_regs; endregno = end_hard_regno (mode, regno); + + if (setter && GET_CODE (setter) == CLOBBER_HIGH) + gcc_assert (endregno == regno + 1); } else { @@ -2218,6 +2224,19 @@ cselib_invalidate_regno (unsigned int regno, machine_mode mode) continue; } + /* Ignore if clobber high and the register isn't clobbered. */ + if (setter && GET_CODE (setter) == CLOBBER_HIGH) + { + gcc_assert (endregno == regno + 1); + const_rtx x = XEXP (setter, 0); + if (!reg_is_clobbered_by_clobber_high (i, GET_MODE (v->val_rtx), + x)) + { + l = &(*l)->next; + continue; + } + } + /* We have an overlap. */ if (*l == REG_VALUES (i)) { @@ -2352,10 +2371,10 @@ cselib_invalidate_mem (rtx mem_rtx) *vp = &dummy_val; } -/* Invalidate DEST, which is being assigned to or clobbered. */ +/* Invalidate DEST, which is being assigned to or clobbered by SETTER. */ void -cselib_invalidate_rtx (rtx dest) +cselib_invalidate_rtx (rtx dest, const_rtx setter) { while (GET_CODE (dest) == SUBREG || GET_CODE (dest) == ZERO_EXTRACT @@ -2363,7 +2382,7 @@ cselib_invalidate_rtx (rtx dest) dest = XEXP (dest, 0); if (REG_P (dest)) - cselib_invalidate_regno (REGNO (dest), GET_MODE (dest)); + cselib_invalidate_regno (REGNO (dest), GET_MODE (dest), setter); else if (MEM_P (dest)) cselib_invalidate_mem (dest); } @@ -2371,10 +2390,10 @@ cselib_invalidate_rtx (rtx dest) /* A wrapper for cselib_invalidate_rtx to be called via note_stores. */ static void -cselib_invalidate_rtx_note_stores (rtx dest, const_rtx ignore ATTRIBUTE_UNUSED, +cselib_invalidate_rtx_note_stores (rtx dest, const_rtx setter, void *data ATTRIBUTE_UNUSED) { - cselib_invalidate_rtx (dest); + cselib_invalidate_rtx (dest, setter); } /* Record the result of a SET instruction. DEST is being set; the source @@ -2710,9 +2729,12 @@ cselib_process_insn (rtx_insn *insn) if (CALL_P (insn)) { for (x = CALL_INSN_FUNCTION_USAGE (insn); x; x = XEXP (x, 1)) - if (GET_CODE (XEXP (x, 0)) == CLOBBER) - cselib_invalidate_rtx (XEXP (XEXP (x, 0), 0)); - /* Flush evertything on setjmp. */ + { + gcc_assert (GET_CODE (XEXP (x, 0)) != CLOBBER_HIGH); + if (GET_CODE (XEXP (x, 0)) == CLOBBER) + cselib_invalidate_rtx (XEXP (XEXP (x, 0), 0)); + } + /* Flush everything on setjmp. */ if (cselib_preserve_constants && find_reg_note (insn, REG_SETJMP, NULL)) { From patchwork Thu Nov 16 12:35:36 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alan Hayward X-Patchwork-Id: 838538 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-466989-incoming=patchwork.ozlabs.org@gcc.gnu.org; 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Thu, 16 Nov 2017 12:35:44 +0000 Received: from AM3PR08MB0101.eurprd08.prod.outlook.com (10.160.211.19) by AM3PR08MB0103.eurprd08.prod.outlook.com (10.160.211.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.20.239.5; Thu, 16 Nov 2017 12:35:36 +0000 Received: from AM3PR08MB0101.eurprd08.prod.outlook.com ([fe80::2891:52f2:59:8e54]) by AM3PR08MB0101.eurprd08.prod.outlook.com ([fe80::2891:52f2:59:8e54%16]) with mapi id 15.20.0218.015; Thu, 16 Nov 2017 12:35:36 +0000 From: Alan Hayward To: "gcc-patches@gcc.gnu.org" CC: nd Subject: [PATCH 6/7]: Remaining support for clobber high Date: Thu, 16 Nov 2017 12:35:36 +0000 Message-ID: <03CBD65C-26DF-4538-AEDF-27C8169282DC@arm.com> authentication-results: spf=none (sender IP is ) smtp.mailfrom=Alan.Hayward@arm.com; x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1; AM3PR08MB0103; 6:doAanOXA/v+RRllkm/+TArV2QvtxixXI4DO1i/cfgU/iZDWiMoTuWRe21qdpDGoITU9uI53DoHsXHkqP5tholk7qMocrSrzwTSdLS3YkX9ZOUoWPuTwyFcFxtMdctGTd0HBd8nRdZVii7eOUEvPqdej4lET8YN+DtvMCXAlMQwk04BPgY/q6h7AnoogjfJAnYp0y7oBPWMKhq1HBaAx0bg2ztmxPKdzFO3qA6sAH9WJYt4pfRCasKg1XTirgI0GDvJquAV5q/tqa6FUPdPxPW+nXKxOzwm9zJ6wUbfDmFtGSUS+J47nZddFimUC5p3sYXVsP0TA7wkp70XJImnA/NAienwqycNEFfbuCb0MD5Bo=; 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DIR:OUT; SFP:1101; SCL:1; SRVR:AM3PR08MB0103; H:AM3PR08MB0101.eurprd08.prod.outlook.com; FPR:; SPF:None; PTR:InfoNoRecords; A:1; MX:1; LANG:en; received-spf: None (protection.outlook.com: arm.com does not designate permitted sender hosts) spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM Content-ID: MIME-Version: 1.0 X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-Network-Message-Id: b488ffd9-cbce-416f-4cdc-08d52cee8971 X-MS-Exchange-CrossTenant-originalarrivaltime: 16 Nov 2017 12:35:36.1129 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM3PR08MB0103 This patch simply adds the remainder of clobber high checks. Happy to split this into smaller patches if required (there didn't seem anything obvious to split into). Alan. 2017-11-16 Alan Hayward * alias.c (record_set): Check for clobber high. * cfgexpand.c (expand_gimple_stmt): Likewise. * combine-stack-adj.c (single_set_for_csa): Likewise. * combine.c (find_single_use_1): Likewise. (set_nonzero_bits_and_sign_copies): Likewise. (get_combine_src_dest): Likewise. (is_parallel_of_n_reg_sets): Likewise. (try_combine): Likewise. (record_dead_and_set_regs_1): Likewise. (reg_dead_at_p_1): Likewise. (reg_dead_at_p): Likewise. * dce.c (deletable_insn_p): Likewise. (mark_nonreg_stores_1): Likewise. (mark_nonreg_stores_2): Likewise. * df-scan.c (df_find_hard_reg_defs): Likewise. (df_uses_record): Likewise. (df_get_call_refs): Likewise. * dwarf2out.c (mem_loc_descriptor): Likewise. * haifa-sched.c (haifa_classify_rtx): Likewise. * ira-build.c (create_insn_allocnos): Likewise. * ira-costs.c (scan_one_insn): Likewise. * ira.c (equiv_init_movable_p): Likewise. (rtx_moveable_p): Likewise. (interesting_dest_for_shprep): Likewise. * jump.c (mark_jump_label_1): Likewise. * postreload-gcse.c (record_opr_changes): Likewise. * postreload.c (reload_cse_simplify): Likewise. (struct reg_use): Add source expr. (reload_combine): Check for clobber high. (reload_combine_note_use): Likewise. (reload_cse_move2add): Likewise. (move2add_note_store): Likewise. * print-rtl.c (print_pattern): Likewise. * recog.c (decode_asm_operands): Likewise. (store_data_bypass_p): Likewise. (if_test_bypass_p): Likewise. * regcprop.c (kill_clobbered_value): Likewise. (kill_set_value): Likewise. * reginfo.c (reg_scan_mark_refs): Likewise. * reload1.c (maybe_fix_stack_asms): Likewise. (eliminate_regs_1): Likewise. (elimination_effects): Likewise. (mark_not_eliminable): Likewise. (scan_paradoxical_subregs): Likewise. (forget_old_reloads_1): Likewise. * reorg.c (find_end_label): Likewise. (try_merge_delay_insns): Likewise. (redundant_insn): Likewise. (own_thread_p): Likewise. (fill_simple_delay_slots): Likewise. (fill_slots_from_thread): Likewise. (dbr_schedule): Likewise. * resource.c (update_live_status): Likewise. (mark_referenced_resources): Likewise. (mark_set_resources): Likewise. * rtl.c (copy_rtx): Likewise. * rtlanal.c (reg_referenced_p): Likewise. (single_set_2): Likewise. (noop_move_p): Likewise. (note_stores): Likewise. * sched-deps.c (sched_analyze_reg): Likewise. (sched_analyze_insn): Likewise. diff --git a/gcc/alias.c b/gcc/alias.c index c69ef410edac2ab0ab93e8ec9fe4c89a7078c001..6a6734bd7d5732c255c009be47e68aa073a9ebb1 100644 --- a/gcc/alias.c +++ b/gcc/alias.c @@ -1554,6 +1554,17 @@ record_set (rtx dest, const_rtx set, void *data ATTRIBUTE_UNUSED) new_reg_base_value[regno] = 0; return; } + /* A CLOBBER_HIGH only wipes out the old value if the mode of the old + value is greater than that of the clobber. */ + else if (GET_CODE (set) == CLOBBER_HIGH) + { + if (new_reg_base_value[regno] != 0 + && reg_is_clobbered_by_clobber_high ( + regno, GET_MODE (new_reg_base_value[regno]), XEXP (set, 0))) + new_reg_base_value[regno] = 0; + return; + } + src = SET_SRC (set); } else diff --git a/gcc/cfgexpand.c b/gcc/cfgexpand.c index 06a8af8a1663c9e518a8169650a0c9969990df1f..ea6fc265f757543cff635a805fd4045a10add23e 100644 --- a/gcc/cfgexpand.c +++ b/gcc/cfgexpand.c @@ -3803,6 +3803,7 @@ expand_gimple_stmt (gimple *stmt) /* If we want exceptions for non-call insns, any may_trap_p instruction may throw. */ && GET_CODE (PATTERN (insn)) != CLOBBER + && GET_CODE (PATTERN (insn)) != CLOBBER_HIGH && GET_CODE (PATTERN (insn)) != USE && insn_could_throw_p (insn)) make_reg_eh_region_note (insn, 0, lp_nr); diff --git a/gcc/combine-stack-adj.c b/gcc/combine-stack-adj.c index 09f0be814f98922b6926a929401894809a890f61..595e83c73760a97e0f8ebd99e12b1853d1d52b92 100644 --- a/gcc/combine-stack-adj.c +++ b/gcc/combine-stack-adj.c @@ -133,6 +133,7 @@ single_set_for_csa (rtx_insn *insn) && SET_SRC (this_rtx) == SET_DEST (this_rtx)) ; else if (GET_CODE (this_rtx) != CLOBBER + && GET_CODE (this_rtx) != CLOBBER_HIGH && GET_CODE (this_rtx) != USE) return NULL_RTX; } diff --git a/gcc/combine.c b/gcc/combine.c index 99cc343192ec4e2f8bdca0667858fbdf11baaffb..8b17349c240bea7a752cfd58f392f5a9dbfd53d6 100644 --- a/gcc/combine.c +++ b/gcc/combine.c @@ -573,6 +573,7 @@ find_single_use_1 (rtx dest, rtx *loc) case SYMBOL_REF: CASE_CONST_ANY: case CLOBBER: + case CLOBBER_HIGH: return 0; case SET: @@ -1755,6 +1756,9 @@ set_nonzero_bits_and_sign_copies (rtx x, const_rtx set, void *data) return; } + /* Should not happen as we only using pseduo registers. */ + gcc_assert (GET_CODE (set) != CLOBBER_HIGH); + /* If this register is being initialized using itself, and the register is uninitialized in this basic block, and there are no LOG_LINKS which set the register, then part of the @@ -1853,6 +1857,7 @@ get_combine_src_dest (combine_insn *insnc, rtx *pdest, rtx *psrc) /* We can ignore CLOBBERs. */ case CLOBBER: + case CLOBBER_HIGH: break; case SET: @@ -2715,10 +2720,17 @@ is_parallel_of_n_reg_sets (rtx pat, int n) || !REG_P (SET_DEST (XVECEXP (pat, 0, i)))) return false; for ( ; i < len; i++) - if (GET_CODE (XVECEXP (pat, 0, i)) != CLOBBER - || XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx) - return false; - + switch (GET_CODE (XVECEXP (pat, 0, i))) + { + case CLOBBER: + if (XEXP (XVECEXP (pat, 0, i), 0) == const0_rtx) + return false; + break; + case CLOBBER_HIGH: + break; + default: + return false; + } return true; } @@ -3099,7 +3111,8 @@ try_combine (rtx_insn *i3, rtx_insn *i2, rtx_insn *i1, rtx_insn *i0, for (i = 0; ok && i < XVECLEN (p2, 0); i++) { if ((GET_CODE (XVECEXP (p2, 0, i)) == SET - || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER) + || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER + || GET_CODE (XVECEXP (p2, 0, i)) == CLOBBER_HIGH) && reg_overlap_mentioned_p (SET_DEST (PATTERN (i3)), SET_DEST (XVECEXP (p2, 0, i)))) ok = false; @@ -13553,6 +13566,15 @@ record_dead_and_set_regs_1 (rtx dest, const_rtx setter, void *data) record_value_for_reg (dest, record_dead_insn, gen_lowpart (GET_MODE (dest), SET_SRC (setter))); + else if (GET_CODE (setter) == CLOBBER_HIGH) + { + reg_stat_type *rsp = ®_stat[REGNO (dest)]; + if (rsp->last_set_value + && reg_is_clobbered_by_clobber_high + (REGNO (dest), GET_MODE (rsp->last_set_value), + XEXP (setter, 0))) + record_value_for_reg (dest, NULL, NULL_RTX); + } else record_value_for_reg (dest, record_dead_insn, NULL_RTX); } @@ -14030,6 +14052,7 @@ use_crosses_set_p (const_rtx x, rtx_insn *from, rtx_insn *to) static unsigned int reg_dead_regno, reg_dead_endregno; static int reg_dead_flag; +rtx reg_dead_reg; /* Function called via note_stores from reg_dead_at_p. @@ -14044,6 +14067,10 @@ reg_dead_at_p_1 (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED) if (!REG_P (dest)) return; + if (GET_CODE (x) == CLOBBER_HIGH + && !reg_is_clobbered_by_clobber_high (reg_dead_reg, x)) + return; + regno = REGNO (dest); endregno = END_REGNO (dest); if (reg_dead_endregno > regno && reg_dead_regno < endregno) @@ -14067,6 +14094,7 @@ reg_dead_at_p (rtx reg, rtx_insn *insn) /* Set variables for reg_dead_at_p_1. */ reg_dead_regno = REGNO (reg); reg_dead_endregno = END_REGNO (reg); + reg_dead_reg = reg; reg_dead_flag = 0; diff --git a/gcc/dce.c b/gcc/dce.c index 9f3021f13fe5171e0eaa26918eaee6bb690a3eb0..b0518a7d23d677e7192c173375473e03e68812cd 100644 --- a/gcc/dce.c +++ b/gcc/dce.c @@ -139,6 +139,7 @@ deletable_insn_p (rtx_insn *insn, bool fast, bitmap arg_stores) return false; case CLOBBER: + case CLOBBER_HIGH: if (fast) { /* A CLOBBER of a dead pseudo register serves no purpose. @@ -207,7 +208,10 @@ static void mark_nonreg_stores_1 (rtx dest, const_rtx pattern, void *data) { if (GET_CODE (pattern) != CLOBBER && !REG_P (dest)) - mark_insn ((rtx_insn *) data, true); + { + gcc_checking_assert (GET_CODE (pattern) != CLOBBER_HIGH); + mark_insn ((rtx_insn *) data, true); + } } @@ -218,7 +222,10 @@ static void mark_nonreg_stores_2 (rtx dest, const_rtx pattern, void *data) { if (GET_CODE (pattern) != CLOBBER && !REG_P (dest)) - mark_insn ((rtx_insn *) data, false); + { + gcc_checking_assert (GET_CODE (pattern) != CLOBBER_HIGH); + mark_insn ((rtx_insn *) data, false); + } } diff --git a/gcc/df-scan.c b/gcc/df-scan.c index 8ab3d716ea2975ed687e1e3cf61ab3233e378f63..3962d5ab49cf321a4d8e866ec84f3867c0f34248 100644 --- a/gcc/df-scan.c +++ b/gcc/df-scan.c @@ -2777,6 +2777,7 @@ df_find_hard_reg_defs (rtx x, HARD_REG_SET *defs) break; case CLOBBER: + case CLOBBER_HIGH: df_find_hard_reg_defs_1 (XEXP (x, 0), defs); break; @@ -2836,6 +2837,10 @@ df_uses_record (struct df_collection_rec *collection_rec, /* If we're clobbering a REG then we have a def so ignore. */ return; + case CLOBBER_HIGH: + gcc_assert (REG_P (XEXP (x, 0))); + return; + case MEM: df_uses_record (collection_rec, &XEXP (x, 0), DF_REF_REG_MEM_LOAD, @@ -3132,6 +3137,7 @@ df_get_call_refs (struct df_collection_rec *collection_rec, for (note = CALL_INSN_FUNCTION_USAGE (insn_info->insn); note; note = XEXP (note, 1)) { + gcc_assert (GET_CODE (XEXP (note, 0)) != CLOBBER_HIGH); if (GET_CODE (XEXP (note, 0)) == USE) df_uses_record (collection_rec, &XEXP (XEXP (note, 0), 0), DF_REF_REG_USE, bb, insn_info, flags); diff --git a/gcc/dwarf2out.c b/gcc/dwarf2out.c index c0f93d763f5163cff5db2241df383c48777803ac..78811a6861e6100ebaaeb7ed4b143da55657d6e1 100644 --- a/gcc/dwarf2out.c +++ b/gcc/dwarf2out.c @@ -15663,6 +15663,7 @@ mem_loc_descriptor (rtx rtl, machine_mode mode, case CONST_FIXED: case CLRSB: case CLOBBER: + case CLOBBER_HIGH: /* If delegitimize_address couldn't do anything with the UNSPEC, we can't express it in the debug info. This can happen e.g. with some TLS UNSPECs. */ diff --git a/gcc/haifa-sched.c b/gcc/haifa-sched.c index f5c06a95bb6742475bf7d1f2c5ea16456fa21efe..81c9ae378333079e99372153b64e5ffb1a088fc5 100644 --- a/gcc/haifa-sched.c +++ b/gcc/haifa-sched.c @@ -529,6 +529,9 @@ haifa_classify_rtx (const_rtx x) /* Test if it is a 'store'. */ tmp_class = may_trap_exp (XEXP (x, 0), 1); break; + case CLOBBER_HIGH: + gcc_assert (REG_P (XEXP (x, 0))); + break; case SET: /* Test if it is a store. */ tmp_class = may_trap_exp (SET_DEST (x), 1); diff --git a/gcc/ira-build.c b/gcc/ira-build.c index 67c0305a1685d432904e93d2057b38daf7fac315..8a1f2bac04600bc18cc0e3d6b45fb75c0be2ad97 100644 --- a/gcc/ira-build.c +++ b/gcc/ira-build.c @@ -1876,6 +1876,11 @@ create_insn_allocnos (rtx x, rtx outer, bool output_p) create_insn_allocnos (XEXP (x, 0), NULL, true); return; } + else if (code == CLOBBER_HIGH) + { + gcc_assert (REG_P (XEXP (x, 0)) && HARD_REGISTER_P (XEXP (x, 0))); + return; + } else if (code == MEM) { create_insn_allocnos (XEXP (x, 0), NULL, false); diff --git a/gcc/ira-costs.c b/gcc/ira-costs.c index e24dbc2e01be3048dbec379c0823c90271d7e768..9f03036e18b1abc03dc043c8deee023fa7a82fd4 100644 --- a/gcc/ira-costs.c +++ b/gcc/ira-costs.c @@ -1444,6 +1444,13 @@ scan_one_insn (rtx_insn *insn) return insn; } + if (pat_code == CLOBBER_HIGH) + { + gcc_assert (REG_P (XEXP (PATTERN (insn), 0)) + && HARD_REGISTER_P (XEXP (PATTERN (insn), 0))); + return insn; + } + counted_mem = false; set = single_set (insn); extract_insn (insn); diff --git a/gcc/ira.c b/gcc/ira.c index 93d02093757c2db1e0133db2a2f388cea81e497a..bb6421853a7a7a049a79f0c6e82ef82f667f8321 100644 --- a/gcc/ira.c +++ b/gcc/ira.c @@ -3086,6 +3086,7 @@ equiv_init_movable_p (rtx x, int regno) case CC0: case CLOBBER: + case CLOBBER_HIGH: return 0; case PRE_INC: @@ -4411,6 +4412,7 @@ rtx_moveable_p (rtx *loc, enum op_type type) && rtx_moveable_p (&XEXP (x, 2), OP_IN)); case CLOBBER: + case CLOBBER_HIGH: return rtx_moveable_p (&SET_DEST (x), OP_OUT); case UNSPEC_VOLATILE: @@ -4863,7 +4865,9 @@ interesting_dest_for_shprep (rtx_insn *insn, basic_block call_dom) for (int i = 0; i < XVECLEN (pat, 0); i++) { rtx sub = XVECEXP (pat, 0, i); - if (GET_CODE (sub) == USE || GET_CODE (sub) == CLOBBER) + if (GET_CODE (sub) == USE + || GET_CODE (sub) == CLOBBER + || GET_CODE (sub) == CLOBBER_HIGH) continue; if (GET_CODE (sub) != SET || side_effects_p (sub)) diff --git a/gcc/jump.c b/gcc/jump.c index b5392011b533e83ae7094e0f5870b281e35c2bea..03fc1c20840832c65d65711151c47dbde7c2acef 100644 --- a/gcc/jump.c +++ b/gcc/jump.c @@ -1105,6 +1105,7 @@ mark_jump_label_1 (rtx x, rtx_insn *insn, bool in_mem, bool is_target) case CC0: case REG: case CLOBBER: + case CLOBBER_HIGH: case CALL: return; diff --git a/gcc/postreload-gcse.c b/gcc/postreload-gcse.c index 15fdb7e0cfe7767e559cd9ef6d5f66d3501ffd90..f4f6af75ea56d79a7579a971a3019c586fc9bfc1 100644 --- a/gcc/postreload-gcse.c +++ b/gcc/postreload-gcse.c @@ -791,15 +791,18 @@ record_opr_changes (rtx_insn *insn) record_last_reg_set_info_regno (insn, regno); for (link = CALL_INSN_FUNCTION_USAGE (insn); link; link = XEXP (link, 1)) - if (GET_CODE (XEXP (link, 0)) == CLOBBER) - { - x = XEXP (XEXP (link, 0), 0); - if (REG_P (x)) - { - gcc_assert (HARD_REGISTER_P (x)); - record_last_reg_set_info (insn, x); - } - } + { + gcc_assert (GET_CODE (XEXP (link, 0)) != CLOBBER_HIGH); + if (GET_CODE (XEXP (link, 0)) == CLOBBER) + { + x = XEXP (XEXP (link, 0), 0); + if (REG_P (x)) + { + gcc_assert (HARD_REGISTER_P (x)); + record_last_reg_set_info (insn, x); + } + } + } if (! RTL_CONST_OR_PURE_CALL_P (insn)) record_last_mem_set_info (insn); diff --git a/gcc/postreload.c b/gcc/postreload.c index a70d11a6c878871fea86a1afe0caec4507c0d394..6bdb4a4f3217b1d263f1cedf0234500f20b1516e 100644 --- a/gcc/postreload.c +++ b/gcc/postreload.c @@ -133,6 +133,8 @@ reload_cse_simplify (rtx_insn *insn, rtx testreg) for (i = XVECLEN (body, 0) - 1; i >= 0; --i) { rtx part = XVECEXP (body, 0, i); + /* asms can only have full clobbers, not clobber_highs. */ + gcc_assert (GET_CODE (part) != CLOBBER_HIGH); if (GET_CODE (part) == CLOBBER && REG_P (XEXP (part, 0))) cselib_invalidate_rtx (XEXP (part, 0)); } @@ -156,6 +158,7 @@ reload_cse_simplify (rtx_insn *insn, rtx testreg) } } else if (GET_CODE (part) != CLOBBER + && GET_CODE (part) != CLOBBER_HIGH && GET_CODE (part) != USE) break; } @@ -667,7 +670,8 @@ struct reg_use STORE_RUID is always meaningful if we only want to use a value in a register in a different place: it denotes the next insn in the insn stream (i.e. the last encountered) that sets or clobbers the register. - REAL_STORE_RUID is similar, but clobbers are ignored when updating it. */ + REAL_STORE_RUID is similar, but clobbers are ignored when updating it. + EXPR is the expression used when storing the register. */ static struct { struct reg_use reg_use[RELOAD_COMBINE_MAX_USES]; @@ -677,6 +681,7 @@ static struct int real_store_ruid; int use_ruid; bool all_offsets_match; + rtx expr; } reg_state[FIRST_PSEUDO_REGISTER]; /* Reverse linear uid. This is increased in reload_combine while scanning @@ -1339,6 +1344,10 @@ reload_combine (void) { rtx setuse = XEXP (link, 0); rtx usage_rtx = XEXP (setuse, 0); + /* We could support CLOBBER_HIGH and treat it in the same way as + HARD_REGNO_CALL_PART_CLOBBERED, but no port needs that yet. */ + gcc_assert (GET_CODE (setuse) != CLOBBER_HIGH); + if ((GET_CODE (setuse) == USE || GET_CODE (setuse) == CLOBBER) && REG_P (usage_rtx)) { @@ -1514,6 +1523,10 @@ reload_combine_note_use (rtx *xp, rtx_insn *insn, int ruid, rtx containing_mem) } break; + case CLOBBER_HIGH: + gcc_assert (REG_P (SET_DEST (x))); + return; + case PLUS: /* We are interested in (plus (reg) (const_int)) . */ if (!REG_P (XEXP (x, 0)) @@ -2133,6 +2146,9 @@ reload_cse_move2add (rtx_insn *first) { rtx setuse = XEXP (link, 0); rtx usage_rtx = XEXP (setuse, 0); + /* CALL_INSN_FUNCTION_USAGEs can only have full clobbers, not + clobber_highs. */ + gcc_assert (GET_CODE (setuse) != CLOBBER_HIGH); if (GET_CODE (setuse) == CLOBBER && REG_P (usage_rtx)) { @@ -2295,6 +2311,13 @@ move2add_note_store (rtx dst, const_rtx set, void *data) move2add_record_mode (dst); } + else if (GET_CODE (set) == CLOBBER_HIGH) + { + /* Only invalidate if actually clobbered. */ + if (reg_mode[regno] == BLKmode + || reg_is_clobbered_by_clobber_high (regno, reg_mode[regno], dst)) + goto invalidate; + } else { invalidate: diff --git a/gcc/print-rtl.c b/gcc/print-rtl.c index 2ecdbb4299e2c64e8eea76a4534fe264fce613c4..5920165ceb416e7eec370e6863ffe887161f4b92 100644 --- a/gcc/print-rtl.c +++ b/gcc/print-rtl.c @@ -1715,6 +1715,7 @@ print_pattern (pretty_printer *pp, const_rtx x, int verbose) print_exp (pp, x, verbose); break; case CLOBBER: + case CLOBBER_HIGH: case USE: pp_printf (pp, "%s ", GET_RTX_NAME (GET_CODE (x))); print_value (pp, XEXP (x, 0), verbose); diff --git a/gcc/recog.c b/gcc/recog.c index 05e69134236c2266b966744a54b7ca7e9ed26fa1..769f462d0407673781a2634218c5c62579fb4ac1 100644 --- a/gcc/recog.c +++ b/gcc/recog.c @@ -1600,6 +1600,7 @@ decode_asm_operands (rtx body, rtx *operands, rtx **operand_locs, { if (GET_CODE (XVECEXP (body, 0, i)) == CLOBBER) break; /* Past last SET */ + gcc_assert (GET_CODE (XVECEXP (body, 0, i)) == SET); if (operands) operands[i] = SET_DEST (XVECEXP (body, 0, i)); if (operand_locs) @@ -3690,7 +3691,8 @@ store_data_bypass_p (rtx_insn *out_insn, rtx_insn *in_insn) { out_exp = XVECEXP (out_pat, 0, i); - if (GET_CODE (out_exp) == CLOBBER) + if (GET_CODE (out_exp) == CLOBBER + || GET_CODE (out_exp) == CLOBBER_HIGH) continue; gcc_assert (GET_CODE (out_exp) == SET); @@ -3709,7 +3711,8 @@ store_data_bypass_p (rtx_insn *out_insn, rtx_insn *in_insn) { in_exp = XVECEXP (in_pat, 0, i); - if (GET_CODE (in_exp) == CLOBBER) + if (GET_CODE (in_exp) == CLOBBER + || GET_CODE (in_exp) == CLOBBER_HIGH) continue; gcc_assert (GET_CODE (in_exp) == SET); @@ -3732,7 +3735,8 @@ store_data_bypass_p (rtx_insn *out_insn, rtx_insn *in_insn) { out_exp = XVECEXP (out_pat, 0, j); - if (GET_CODE (out_exp) == CLOBBER) + if (GET_CODE (out_exp) == CLOBBER + || GET_CODE (out_exp) == CLOBBER_HIGH) continue; gcc_assert (GET_CODE (out_exp) == SET); @@ -3787,7 +3791,7 @@ if_test_bypass_p (rtx_insn *out_insn, rtx_insn *in_insn) { rtx exp = XVECEXP (out_pat, 0, i); - if (GET_CODE (exp) == CLOBBER) + if (GET_CODE (exp) == CLOBBER || GET_CODE (exp) == CLOBBER_HIGH) continue; gcc_assert (GET_CODE (exp) == SET); diff --git a/gcc/regcprop.c b/gcc/regcprop.c index 4ca10f58a58aa4c7605b001ec851c79a25fd6a8c..85b474544b22c915af9ea55230443186563dd624 100644 --- a/gcc/regcprop.c +++ b/gcc/regcprop.c @@ -237,7 +237,11 @@ static void kill_clobbered_value (rtx x, const_rtx set, void *data) { struct value_data *const vd = (struct value_data *) data; - if (GET_CODE (set) == CLOBBER) + gcc_assert (GET_CODE (set) != CLOBBER_HIGH || REG_P (x)); + + if (GET_CODE (set) == CLOBBER + || (GET_CODE (set) == CLOBBER_HIGH + && reg_is_clobbered_by_clobber_high (x, XEXP (set, 0)))) kill_value (x, vd); } @@ -257,7 +261,9 @@ kill_set_value (rtx x, const_rtx set, void *data) struct kill_set_value_data *ksvd = (struct kill_set_value_data *) data; if (rtx_equal_p (x, ksvd->ignore_set_reg)) return; - if (GET_CODE (set) != CLOBBER) + + gcc_assert (GET_CODE (set) != CLOBBER_HIGH || REG_P (x)); + if (GET_CODE (set) != CLOBBER && GET_CODE (set) != CLOBBER_HIGH) { kill_value (x, ksvd->vd); if (REG_P (x)) diff --git a/gcc/reginfo.c b/gcc/reginfo.c index 847305ebe61fd3cd0cf02c01a02c537ad8b22c4a..bd9dd05e53404490b795b86b473e3b252bde1b50 100644 --- a/gcc/reginfo.c +++ b/gcc/reginfo.c @@ -1100,6 +1100,10 @@ reg_scan_mark_refs (rtx x, rtx_insn *insn) reg_scan_mark_refs (XEXP (XEXP (x, 0), 0), insn); break; + case CLOBBER_HIGH: + gcc_assert (!(MEM_P (XEXP (x, 0)))); + break; + case SET: /* Count a set of the destination if it is a register. */ for (dest = SET_DEST (x); diff --git a/gcc/reload1.c b/gcc/reload1.c index 902d940245dfcb73c10de8670adb22375fbfe098..68b16ca8bd747511589a74529c1ac922acf04215 100644 --- a/gcc/reload1.c +++ b/gcc/reload1.c @@ -1339,6 +1339,8 @@ maybe_fix_stack_asms (void) rtx t = XVECEXP (pat, 0, i); if (GET_CODE (t) == CLOBBER && STACK_REG_P (XEXP (t, 0))) SET_HARD_REG_BIT (clobbered, REGNO (XEXP (t, 0))); + /* CLOBBER_HIGH is only supported for LRA. */ + gcc_assert (GET_CODE (t) != CLOBBER_HIGH); } /* Get the operand values and constraints out of the insn. */ @@ -2879,6 +2881,7 @@ eliminate_regs_1 (rtx x, machine_mode mem_mode, rtx insn, return x; case CLOBBER: + case CLOBBER_HIGH: case ASM_OPERANDS: gcc_assert (insn && DEBUG_INSN_P (insn)); break; @@ -3089,6 +3092,10 @@ elimination_effects (rtx x, machine_mode mem_mode) elimination_effects (XEXP (x, 0), mem_mode); return; + case CLOBBER_HIGH: + /* CLOBBER_HIGH is only supported for LRA. */ + return; + case SET: /* Check for setting a register that we know about. */ if (REG_P (SET_DEST (x))) @@ -3810,6 +3817,9 @@ mark_not_eliminable (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED) if (dest == hard_frame_pointer_rtx) return; + /* CLOBBER_HIGH is only supported for LRA. */ + gcc_assert (GET_CODE (x) != CLOBBER_HIGH); + for (i = 0; i < NUM_ELIMINABLE_REGS; i++) if (reg_eliminate[i].can_eliminate && dest == reg_eliminate[i].to_rtx && (GET_CODE (x) != SET @@ -4445,6 +4455,7 @@ scan_paradoxical_subregs (rtx x) case PC: case USE: case CLOBBER: + case CLOBBER_HIGH: return; case SUBREG: @@ -4899,7 +4910,7 @@ reload_as_needed (int live_known) to be forgotten later. */ static void -forget_old_reloads_1 (rtx x, const_rtx ignored ATTRIBUTE_UNUSED, +forget_old_reloads_1 (rtx x, const_rtx setter, void *data) { unsigned int regno; @@ -4919,6 +4930,9 @@ forget_old_reloads_1 (rtx x, const_rtx ignored ATTRIBUTE_UNUSED, if (!REG_P (x)) return; + /* CLOBBER_HIGH is only supported for LRA. */ + gcc_assert (GET_CODE (setter) != CLOBBER_HIGH); + regno = REGNO (x); if (regno >= FIRST_PSEUDO_REGISTER) diff --git a/gcc/reorg.c b/gcc/reorg.c index 5914af655b6bbbddc98f23f53c0d1e6e496dc2eb..4f97e78b2a3c03db89a1bd2fa10bf8e83c374ae7 100644 --- a/gcc/reorg.c +++ b/gcc/reorg.c @@ -396,7 +396,8 @@ find_end_label (rtx kind) while (NOTE_P (insn) || (NONJUMP_INSN_P (insn) && (GET_CODE (PATTERN (insn)) == USE - || GET_CODE (PATTERN (insn)) == CLOBBER))) + || GET_CODE (PATTERN (insn)) == CLOBBER + || GET_CODE (PATTERN (insn)) == CLOBBER_HIGH))) insn = PREV_INSN (insn); /* When a target threads its epilogue we might already have a @@ -1290,7 +1291,8 @@ try_merge_delay_insns (rtx_insn *insn, rtx_insn *thread) /* TRIAL must be a CALL_INSN or INSN. Skip USE and CLOBBER. */ if (NONJUMP_INSN_P (trial) - && (GET_CODE (pat) == USE || GET_CODE (pat) == CLOBBER)) + && (GET_CODE (pat) == USE || GET_CODE (pat) == CLOBBER + || GET_CODE (pat) == CLOBBER_HIGH)) continue; if (GET_CODE (next_to_match) == GET_CODE (trial) @@ -1484,7 +1486,8 @@ redundant_insn (rtx insn, rtx_insn *target, const vec &delay_list) --insns_to_search; pat = PATTERN (trial); - if (GET_CODE (pat) == USE || GET_CODE (pat) == CLOBBER) + if (GET_CODE (pat) == USE || GET_CODE (pat) == CLOBBER + || GET_CODE (pat) == CLOBBER_HIGH) continue; if (rtx_sequence *seq = dyn_cast (pat)) @@ -1579,7 +1582,8 @@ redundant_insn (rtx insn, rtx_insn *target, const vec &delay_list) --insns_to_search; pat = PATTERN (trial); - if (GET_CODE (pat) == USE || GET_CODE (pat) == CLOBBER) + if (GET_CODE (pat) == USE || GET_CODE (pat) == CLOBBER + || GET_CODE (pat) == CLOBBER_HIGH) continue; if (rtx_sequence *seq = dyn_cast (pat)) @@ -1688,7 +1692,8 @@ own_thread_p (rtx thread, rtx label, int allow_fallthrough) || LABEL_P (insn) || (NONJUMP_INSN_P (insn) && GET_CODE (PATTERN (insn)) != USE - && GET_CODE (PATTERN (insn)) != CLOBBER)) + && GET_CODE (PATTERN (insn)) != CLOBBER + && GET_CODE (PATTERN (insn)) != CLOBBER_HIGH)) return 0; return 1; @@ -2013,7 +2018,8 @@ fill_simple_delay_slots (int non_jumps_p) pat = PATTERN (trial); /* Stand-alone USE and CLOBBER are just for flow. */ - if (GET_CODE (pat) == USE || GET_CODE (pat) == CLOBBER) + if (GET_CODE (pat) == USE || GET_CODE (pat) == CLOBBER + || GET_CODE (pat) == CLOBBER_HIGH) continue; /* Check for resource conflict first, to avoid unnecessary @@ -2135,7 +2141,8 @@ fill_simple_delay_slots (int non_jumps_p) pat = PATTERN (trial); /* Stand-alone USE and CLOBBER are just for flow. */ - if (GET_CODE (pat) == USE || GET_CODE (pat) == CLOBBER) + if (GET_CODE (pat) == USE || GET_CODE (pat) == CLOBBER + || GET_CODE (pat) == CLOBBER_HIGH) continue; /* If this already has filled delay slots, get the insn needing @@ -2400,7 +2407,8 @@ fill_slots_from_thread (rtx_jump_insn *insn, rtx condition, } pat = PATTERN (trial); - if (GET_CODE (pat) == USE || GET_CODE (pat) == CLOBBER) + if (GET_CODE (pat) == USE || GET_CODE (pat) == CLOBBER + || GET_CODE (pat) == CLOBBER_HIGH) continue; /* If TRIAL conflicts with the insns ahead of it, we lose. Also, @@ -3790,7 +3798,8 @@ dbr_schedule (rtx_insn *first) if (! insn->deleted () && NONJUMP_INSN_P (insn) && GET_CODE (PATTERN (insn)) != USE - && GET_CODE (PATTERN (insn)) != CLOBBER) + && GET_CODE (PATTERN (insn)) != CLOBBER + && GET_CODE (PATTERN (insn)) != CLOBBER_HIGH) { if (GET_CODE (PATTERN (insn)) == SEQUENCE) { diff --git a/gcc/resource.c b/gcc/resource.c index 95911c5c718f8ae79a401c782624ec8a01a9e8ab..463e370b2d8610787ba21b4be3925aa1ae86e71e 100644 --- a/gcc/resource.c +++ b/gcc/resource.c @@ -108,6 +108,11 @@ update_live_status (rtx dest, const_rtx x, void *data ATTRIBUTE_UNUSED) if (GET_CODE (x) == CLOBBER) for (i = first_regno; i < last_regno; i++) CLEAR_HARD_REG_BIT (current_live_regs, i); + else if (GET_CODE (x) == CLOBBER_HIGH) + /* No current target supports both branch delay slots and CLOBBER_HIGH. + We'd need more elaborate liveness tracking to handle that + combination. */ + gcc_unreachable (); else for (i = first_regno; i < last_regno; i++) { @@ -292,6 +297,7 @@ mark_referenced_resources (rtx x, struct resources *res, return; case CLOBBER: + case CLOBBER_HIGH: return; case CALL_INSN: @@ -665,9 +671,15 @@ mark_set_resources (rtx x, struct resources *res, int in_dest, for (link = CALL_INSN_FUNCTION_USAGE (call_insn); link; link = XEXP (link, 1)) - if (GET_CODE (XEXP (link, 0)) == CLOBBER) - mark_set_resources (SET_DEST (XEXP (link, 0)), res, 1, - MARK_SRC_DEST); + { + /* We could support CLOBBER_HIGH and treat it in the same way as + HARD_REGNO_CALL_PART_CLOBBERED, but no port needs that + yet. */ + gcc_assert (GET_CODE (XEXP (link, 0)) != CLOBBER_HIGH); + if (GET_CODE (XEXP (link, 0)) == CLOBBER) + mark_set_resources (SET_DEST (XEXP (link, 0)), res, 1, + MARK_SRC_DEST); + } /* Check for a REG_SETJMP. If it exists, then we must assume that this call can clobber any register. */ @@ -710,6 +722,12 @@ mark_set_resources (rtx x, struct resources *res, int in_dest, mark_set_resources (XEXP (x, 0), res, 1, MARK_SRC_DEST); return; + case CLOBBER_HIGH: + /* No current target supports both branch delay slots and CLOBBER_HIGH. + We'd need more elaborate liveness tracking to handle that + combination. */ + gcc_unreachable (); + case SEQUENCE: { rtx_sequence *seq = as_a (x); diff --git a/gcc/rtl.c b/gcc/rtl.c index 6db84f99627bb8617c6e227892ca44076f4e729b..12a01e8ed1f9005e5c0dfeb0f86c762069520284 100644 --- a/gcc/rtl.c +++ b/gcc/rtl.c @@ -307,6 +307,10 @@ copy_rtx (rtx orig) return orig; break; + case CLOBBER_HIGH: + gcc_assert (REG_P (XEXP (orig, 0))); + return orig; + case CONST: if (shared_const_p (orig)) return orig; diff --git a/gcc/rtlanal.c b/gcc/rtlanal.c index 923e3314d25c05f9055907c61b4a24186701cc23..d907d636ed5f22d9cdc7237d66fdb05da9922f60 100644 --- a/gcc/rtlanal.c +++ b/gcc/rtlanal.c @@ -1196,6 +1196,10 @@ reg_referenced_p (const_rtx x, const_rtx body) return 1; return 0; + case CLOBBER_HIGH: + gcc_assert (REG_P (XEXP (body, 0))); + return 0; + case COND_EXEC: if (reg_overlap_mentioned_p (x, COND_EXEC_TEST (body))) return 1; @@ -1507,6 +1511,7 @@ single_set_2 (const rtx_insn *insn, const_rtx pat) { case USE: case CLOBBER: + case CLOBBER_HIGH: break; case SET: @@ -1660,7 +1665,8 @@ noop_move_p (const rtx_insn *insn) rtx tem = XVECEXP (pat, 0, i); if (GET_CODE (tem) == USE - || GET_CODE (tem) == CLOBBER) + || GET_CODE (tem) == CLOBBER + || GET_CODE (tem) == CLOBBER_HIGH) continue; if (GET_CODE (tem) != SET || ! set_noop_p (tem)) @@ -1892,7 +1898,9 @@ note_stores (const_rtx x, void (*fun) (rtx, const_rtx, void *), void *data) if (GET_CODE (x) == COND_EXEC) x = COND_EXEC_CODE (x); - if (GET_CODE (x) == SET || GET_CODE (x) == CLOBBER) + if (GET_CODE (x) == SET + || GET_CODE (x) == CLOBBER + || GET_CODE (x) == CLOBBER_HIGH) { rtx dest = SET_DEST (x); diff --git a/gcc/sched-deps.c b/gcc/sched-deps.c index a64e4e17bbc8115982d253d041032243e9506802..8eb0ed350557d3c0af87bbba674cefd4478d97aa 100644 --- a/gcc/sched-deps.c +++ b/gcc/sched-deps.c @@ -2319,6 +2319,13 @@ sched_analyze_reg (struct deps_desc *deps, int regno, machine_mode mode, while (--i >= 0) note_reg_use (regno + i); } + else if (ref == CLOBBER_HIGH) + { + gcc_assert (i == 1); + /* We don't know the current state of the register, so have to treat + the clobber high as a full clobber. */ + note_reg_clobber (regno); + } else { while (--i >= 0) @@ -2342,6 +2349,8 @@ sched_analyze_reg (struct deps_desc *deps, int regno, machine_mode mode, else if (ref == USE) note_reg_use (regno); else + /* For CLOBBER_HIGH, we don't know the current state of the register, + so have to treat it as a full clobber. */ note_reg_clobber (regno); /* Pseudos that are REG_EQUIV to something may be replaced @@ -2953,7 +2962,7 @@ sched_analyze_insn (struct deps_desc *deps, rtx x, rtx_insn *insn) sub = COND_EXEC_CODE (sub); code = GET_CODE (sub); } - if (code == SET || code == CLOBBER) + else if (code == SET || code == CLOBBER || code == CLOBBER_HIGH) sched_analyze_1 (deps, sub, insn); else sched_analyze_2 (deps, sub, insn); @@ -2969,6 +2978,10 @@ sched_analyze_insn (struct deps_desc *deps, rtx x, rtx_insn *insn) { if (GET_CODE (XEXP (link, 0)) == CLOBBER) sched_analyze_1 (deps, XEXP (link, 0), insn); + else if (GET_CODE (XEXP (link, 0)) == CLOBBER_HIGH) + /* We could support CLOBBER_HIGH and treat it in the same way as + HARD_REGNO_CALL_PART_CLOBBERED, but no port needs that yet. */ + gcc_unreachable (); else if (GET_CODE (XEXP (link, 0)) != SET) sched_analyze_2 (deps, XEXP (link, 0), insn); } From patchwork Thu Nov 16 12:35:58 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alan Hayward X-Patchwork-Id: 838539 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-466990-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="jW8slKua"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3yd12T0rm7z9ryT for ; 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DIR:OUT; SFP:1101; SCL:1; SRVR:AM3PR08MB0103; H:AM3PR08MB0101.eurprd08.prod.outlook.com; FPR:; SPF:None; PTR:InfoNoRecords; A:1; MX:1; LANG:en; received-spf: None (protection.outlook.com: arm.com does not designate permitted sender hosts) spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM Content-ID: MIME-Version: 1.0 X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-Network-Message-Id: aada55d5-cc38-439d-2b32-08d52cee968e X-MS-Exchange-CrossTenant-originalarrivaltime: 16 Nov 2017 12:35:58.1125 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM3PR08MB0103 This final patch adds the clobber high expressions to tls_desc for aarch64. It also adds three tests. In addition I also tested by taking the gcc torture test suite and making all global variables __thread. Then emended the suite to compile with -fpic, save the .s file and only for one given O level. I ran this before and after the patch and compared the resulting .s files, ensuring that there were no ASM changes. I discarded the 10% of tests that failed to compile (due to the code in the test now being invalid C). I did this for O0,O2,O3 on both x86 and aarch64 and observed no difference between ASM files before and after the patch. Alan. 2017-11-16 Alan Hayward gcc/ * config/aarch64/aarch64.md: Add clobber highs to tls_desc. gcc/testsuite/ * gcc.target/aarch64/sve_tls_preserve_1.c: New test. * gcc.target/aarch64/sve_tls_preserve_2.c: New test. * gcc.target/aarch64/sve_tls_preserve_3.c: New test. diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index 6a15ff0b61d775cf30189b8503cfa45987701228..1f332b254fe0e37954efbe92982f214100d7046f 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -57,7 +57,36 @@ (LR_REGNUM 30) (SP_REGNUM 31) (V0_REGNUM 32) + (V1_REGNUM 33) + (V2_REGNUM 34) + (V3_REGNUM 35) + (V4_REGNUM 36) + (V5_REGNUM 37) + (V6_REGNUM 38) + (V7_REGNUM 39) + (V8_REGNUM 40) + (V9_REGNUM 41) + (V10_REGNUM 42) + (V11_REGNUM 43) + (V12_REGNUM 44) + (V13_REGNUM 45) + (V14_REGNUM 46) (V15_REGNUM 47) + (V16_REGNUM 48) + (V17_REGNUM 49) + (V18_REGNUM 50) + (V19_REGNUM 51) + (V20_REGNUM 52) + (V21_REGNUM 53) + (V22_REGNUM 54) + (V23_REGNUM 55) + (V24_REGNUM 56) + (V25_REGNUM 57) + (V26_REGNUM 58) + (V27_REGNUM 59) + (V28_REGNUM 60) + (V29_REGNUM 61) + (V30_REGNUM 62) (V31_REGNUM 63) (LAST_SAVED_REGNUM 63) (SFP_REGNUM 64) @@ -5745,6 +5774,38 @@ UNSPEC_TLSDESC)) (clobber (reg:DI LR_REGNUM)) (clobber (reg:CC CC_REGNUM)) + (clobber_high (reg:TI V0_REGNUM)) + (clobber_high (reg:TI V1_REGNUM)) + (clobber_high (reg:TI V2_REGNUM)) + (clobber_high (reg:TI V3_REGNUM)) + (clobber_high (reg:TI V4_REGNUM)) + (clobber_high (reg:TI V5_REGNUM)) + (clobber_high (reg:TI V6_REGNUM)) + (clobber_high (reg:TI V7_REGNUM)) + (clobber_high (reg:TI V8_REGNUM)) + (clobber_high (reg:TI V9_REGNUM)) + (clobber_high (reg:TI V10_REGNUM)) + (clobber_high (reg:TI V11_REGNUM)) + (clobber_high (reg:TI V12_REGNUM)) + (clobber_high (reg:TI V13_REGNUM)) + (clobber_high (reg:TI V14_REGNUM)) + (clobber_high (reg:TI V15_REGNUM)) + (clobber_high (reg:TI V16_REGNUM)) + (clobber_high (reg:TI V17_REGNUM)) + (clobber_high (reg:TI V18_REGNUM)) + (clobber_high (reg:TI V19_REGNUM)) + (clobber_high (reg:TI V20_REGNUM)) + (clobber_high (reg:TI V21_REGNUM)) + (clobber_high (reg:TI V22_REGNUM)) + (clobber_high (reg:TI V23_REGNUM)) + (clobber_high (reg:TI V24_REGNUM)) + (clobber_high (reg:TI V25_REGNUM)) + (clobber_high (reg:TI V26_REGNUM)) + (clobber_high (reg:TI V27_REGNUM)) + (clobber_high (reg:TI V28_REGNUM)) + (clobber_high (reg:TI V29_REGNUM)) + (clobber_high (reg:TI V30_REGNUM)) + (clobber_high (reg:TI V31_REGNUM)) (clobber (match_scratch:DI 1 "=r"))] "TARGET_TLS_DESC" "adrp\\tx0, %A0\;ldr\\t%1, [x0, #%L0]\;add\\t0, 0, %L0\;.tlsdesccall\\t%0\;blr\\t%1" diff --git a/gcc/testsuite/gcc.target/aarch64/sve_tls_preserve_1.c b/gcc/testsuite/gcc.target/aarch64/sve_tls_preserve_1.c new file mode 100644 index 0000000000000000000000000000000000000000..5bad829568130181ef1ab386545bd3ee164c322e --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve_tls_preserve_1.c @@ -0,0 +1,20 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -fpic -march=armv8-a+sve" } */ + +/* Clobber highs do not need to be spilled around tls usage. */ + +typedef float v4si __attribute__ ((vector_size (16))); + +__thread v4si tx; + +v4si foo (v4si a, v4si b, v4si c) +{ + v4si y; + + y = a + tx + b + c; + + return y + 7; +} + +/* { dg-final { scan-assembler-not {\tstr\t} } } */ + diff --git a/gcc/testsuite/gcc.target/aarch64/sve_tls_preserve_2.c b/gcc/testsuite/gcc.target/aarch64/sve_tls_preserve_2.c new file mode 100644 index 0000000000000000000000000000000000000000..69e8829287b8418c28f8c227391c4f8d2186ea63 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve_tls_preserve_2.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -fpic -march=armv8-a+sve -msve-vector-bits=256 -fno-schedule-insns" } */ + +/* Clobber highs must be spilled around tls usage. */ + +typedef float v8si __attribute__ ((vector_size (32))); + +__thread v8si tx; + +v8si foo (v8si a, v8si b, v8si c) +{ + v8si y; + + /* There is nothing stopping the compiler from making the tls call before + loading the input variables off the stack. However, there appears to + be no way in C of enforcing this. Thankfully the compiler doesn't + do this reordering. */ + + y = a + tx + b + c; + + return y + 7; +} + +/* { dg-final { scan-assembler-times {\tstr\tz[0-9]+,} 3 } } */ \ No newline at end of file diff --git a/gcc/testsuite/gcc.target/aarch64/sve_tls_preserve_3.c b/gcc/testsuite/gcc.target/aarch64/sve_tls_preserve_3.c new file mode 100644 index 0000000000000000000000000000000000000000..b6aa59a3c7393d7e9ca419167d13b624a9ffafcc --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/sve_tls_preserve_3.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -fpic -march=armv8-a+sve -msve-vector-bits=512 -fno-schedule-insns" } */ + +/* Clobber highs must be spilled around tls usage. */ + +typedef float v16si __attribute__ ((vector_size (64))); + +__thread v16si tx; + +v16si foo (v16si a, v16si b, v16si c) +{ + v16si y; + + /* There is nothing stopping the compiler from making the tls call before + loading the input variables off the stack. However, there appears to + be no way in C of enforcing this. Thankfully the compiler doesn't + do this reordering. */ + + y = a + tx + b + c; + + return y + 7; +} + +/* { dg-final { scan-assembler-times {\tstr\tz[0-9]+,} 3 } } */