From patchwork Thu Nov 16 03:19:35 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akshay Adiga X-Patchwork-Id: 838382 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [103.22.144.68]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3ycmhG5Jh4z9s7v for ; Thu, 16 Nov 2017 14:19:58 +1100 (AEDT) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3ycmhG3FrgzDqr8 for ; Thu, 16 Nov 2017 14:19:58 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=linux.vnet.ibm.com (client-ip=148.163.156.1; helo=mx0a-001b2d01.pphosted.com; envelope-from=akshay.adiga@linux.vnet.ibm.com; receiver=) Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3ycmh50SMZzDqpp for ; Thu, 16 Nov 2017 14:19:48 +1100 (AEDT) Received: from pps.filterd (m0098409.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id vAG3JJeF029568 for ; Wed, 15 Nov 2017 22:19:46 -0500 Received: from e06smtp11.uk.ibm.com (e06smtp11.uk.ibm.com [195.75.94.107]) by mx0a-001b2d01.pphosted.com with ESMTP id 2e91rkj880-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Wed, 15 Nov 2017 22:19:46 -0500 Received: from localhost by e06smtp11.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Thu, 16 Nov 2017 03:19:42 -0000 Received: from d06av21.portsmouth.uk.ibm.com (d06av21.portsmouth.uk.ibm.com [9.149.105.232]) by b06cxnps4075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id vAG3JgPO40304646; Thu, 16 Nov 2017 03:19:42 GMT Received: from d06av21.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 9182E52045; Thu, 16 Nov 2017 02:13:22 +0000 (GMT) Received: from aksadiga.ibm (unknown [9.77.94.253]) by d06av21.portsmouth.uk.ibm.com (Postfix) with ESMTP id DF1DE52043; Thu, 16 Nov 2017 02:13:20 +0000 (GMT) From: Akshay Adiga To: skiboot@lists.ozlabs.org Date: Thu, 16 Nov 2017 08:49:35 +0530 X-Mailer: git-send-email 2.5.5 X-TM-AS-GCONF: 00 x-cbid: 17111603-0040-0000-0000-0000040EDD66 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 17111603-0041-0000-0000-000020B196AC Message-Id: <1510802376-15005-1-git-send-email-akshay.adiga@linux.vnet.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-11-16_01:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=1 phishscore=0 bulkscore=0 spamscore=0 clxscore=1011 lowpriorityscore=0 impostorscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1709140000 definitions=main-1711160044 Subject: [Skiboot] [PATCH 1/2] SLW: Disable deep state on p9_stop_api failure X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.24 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ego@linux.vnet.ibm.com, mikey@neuling.org MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Adds a per chip flag that needs to be set on stop api failure, at any point before device-tree is created. If this flag is set, deeper states (which use p9_stop_api) will not appear in device-tree. Signed-off-by: Akshay Adiga --- hw/slw.c | 11 ++++++++++- include/chip.h | 1 + 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/hw/slw.c b/hw/slw.c index c2c755d..02e938f 100644 --- a/hw/slw.c +++ b/hw/slw.c @@ -912,8 +912,14 @@ void add_cpu_idle_state_properties(void) * P9 : homer_base is set */ if (!(proc_chip_quirks & QUIRK_MAMBO_CALLOUTS)) { - if (proc_gen == proc_gen_p9) + if (proc_gen == proc_gen_p9) { + struct proc_chip *c; has_wakeup_engine = !!(chip->homer_base); + /* disable if p9_stop_api fails at any previous case */ + for_each_chip(c) { + has_wakeup_engine &= ~(c->wakeup_engine_error); + } + } else /* (proc_gen == proc_gen_p8) */ has_wakeup_engine = (chip->slw_base && chip->slw_bar_size && chip->slw_image_size); @@ -1298,6 +1304,9 @@ static void slw_init_chip_p9(struct proc_chip *chip) log_simple_error(&e_info(OPAL_RC_SLW_REG), "SLW: Failed to set HRMOR for CPU %x,RC=0x%x\n", c->pir, rc); + prlog(PR_ERR, "Disabling deep stop states\n"); + chip->wakeup_engine_error = true; + } } } diff --git a/include/chip.h b/include/chip.h index 566edc5..9a2f8bf 100644 --- a/include/chip.h +++ b/include/chip.h @@ -186,6 +186,7 @@ struct proc_chip { uint64_t slw_base; uint64_t slw_bar_size; uint64_t slw_image_size; + bool wakeup_engine_error; /* Used by hw/homer.c */ uint64_t homer_base; From patchwork Thu Nov 16 03:19:36 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Akshay Adiga X-Patchwork-Id: 838383 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3ycmhg2lYMz9s4s for ; Thu, 16 Nov 2017 14:20:19 +1100 (AEDT) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3ycmhg1cmLzDqyQ for ; Thu, 16 Nov 2017 14:20:19 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=linux.vnet.ibm.com (client-ip=148.163.158.5; helo=mx0a-001b2d01.pphosted.com; envelope-from=akshay.adiga@linux.vnet.ibm.com; receiver=) Received: from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3ycmhB4CNdzDqpp for ; Thu, 16 Nov 2017 14:19:54 +1100 (AEDT) Received: from pps.filterd (m0098420.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id vAG3JKac071355 for ; Wed, 15 Nov 2017 22:19:52 -0500 Received: from e06smtp13.uk.ibm.com (e06smtp13.uk.ibm.com [195.75.94.109]) by mx0b-001b2d01.pphosted.com with ESMTP id 2e925nhayr-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Wed, 15 Nov 2017 22:19:51 -0500 Received: from localhost by e06smtp13.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Thu, 16 Nov 2017 03:19:48 -0000 Received: from d06av21.portsmouth.uk.ibm.com (d06av21.portsmouth.uk.ibm.com [9.149.105.232]) by b06cxnps4076.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id vAG3JmJg38142086; Thu, 16 Nov 2017 03:19:48 GMT Received: from d06av21.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id B985C5204E; Thu, 16 Nov 2017 02:13:28 +0000 (GMT) Received: from aksadiga.ibm (unknown [9.77.94.253]) by d06av21.portsmouth.uk.ibm.com (Postfix) with ESMTP id F0A6152045; Thu, 16 Nov 2017 02:13:23 +0000 (GMT) From: Akshay Adiga To: skiboot@lists.ozlabs.org Date: Thu, 16 Nov 2017 08:49:36 +0530 X-Mailer: git-send-email 2.5.5 In-Reply-To: <1510802376-15005-1-git-send-email-akshay.adiga@linux.vnet.ibm.com> References: <1510802376-15005-1-git-send-email-akshay.adiga@linux.vnet.ibm.com> X-TM-AS-GCONF: 00 x-cbid: 17111603-0012-0000-0000-0000058DDE7F X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 17111603-0013-0000-0000-000019089E87 Message-Id: <1510802376-15005-2-git-send-email-akshay.adiga@linux.vnet.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-11-16_01:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=1 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 impostorscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1709140000 definitions=main-1711160044 Subject: [Skiboot] [PATCH 2/2] SCOM restore for DARN and XIVE X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.24 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ego@linux.vnet.ibm.com, mikey@neuling.org MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" While waking up from stop11, we want NCU_DARN_BAR to have enable bit set. Without this stop_api call, the value restored is without enable bit set. We loose NCU_SPEC_BAR when the quad goes into stop11, stop_api will restore while waking up from stop11. Signed-off-by: Akshay Adiga --- Changes from initial posting * Changed flag P9_STOP_SECTION_CORE_SCOM to P9_STOP_SECTION_EQ_SCOM for P9X_EX_NCU_DARN_BAR * Added error handling hw/nx.c | 15 ++++++++++++++- hw/xive.c | 10 ++++++++++ 2 files changed, 24 insertions(+), 1 deletion(-) diff --git a/hw/nx.c b/hw/nx.c index 64ac793..e130317 100644 --- a/hw/nx.c +++ b/hw/nx.c @@ -24,6 +24,7 @@ #include #include #include +#include extern void nx_p9_rng_init(void); @@ -31,7 +32,7 @@ void nx_p9_rng_init(void) { struct proc_chip *chip; struct cpu_thread *c; - uint64_t bar, tmp; + uint64_t bar, tmp, rc; if (proc_gen != proc_gen_p9) return; @@ -65,6 +66,18 @@ void nx_p9_rng_init(void) P9X_EX_NCU_DARN_BAR); xscom_write(chip->id, addr, bar | P9X_EX_NCU_DARN_BAR_EN); + rc = p9_stop_save_scom((void *)chip->homer_base, + addr, bar | P9X_EX_NCU_DARN_BAR_EN, + P9_STOP_SCOM_REPLACE, + P9_STOP_SECTION_EQ_SCOM); + if (rc) { + prlog(PR_ERR, + "p9_stop_api for DARN_BAR failed rc= %lld", + rc); + prlog(PR_ERR, "Disabling deep stop states\n"); + chip->wakeup_engine_error = true; + } + } } } diff --git a/hw/xive.c b/hw/xive.c index df38074..14363b0 100644 --- a/hw/xive.c +++ b/hw/xive.c @@ -24,6 +24,7 @@ #include #include #include +#include /* Use Block group mode to move chip_id into block .... */ #define USE_BLOCK_GROUP_MODE @@ -3136,6 +3137,7 @@ static void xive_configure_ex_special_bar(struct xive *x, struct cpu_thread *c) { uint64_t xa, val; int64_t rc; + struct proc_chip *chip = get_chip(c->chip_id); xive_cpu_dbg(c, "Setting up special BAR\n"); xa = XSCOM_ADDR_P9_EX(pir_to_core_id(c->pir), P9X_EX_NCU_SPEC_BAR); @@ -3148,6 +3150,14 @@ static void xive_configure_ex_special_bar(struct xive *x, struct cpu_thread *c) xive_cpu_err(c, "Failed to setup NCU_SPEC_BAR\n"); /* XXXX what do do now ? */ } + rc = p9_stop_save_scom((void *)chip->homer_base, xa, val, + P9_STOP_SCOM_REPLACE, P9_STOP_SECTION_EQ_SCOM); + if (rc) { + xive_cpu_err(c, "p9_stop_api failed for NCU_SPEC_BAR rc=%lld\n", + rc); + xive_cpu_err(c, "Disabling deep idle states\n"); + chip->wakeup_engine_error = true; + } } static void xive_provision_cpu(struct xive_cpu_state *xs, struct cpu_thread *c)