From patchwork Mon Oct 21 23:10:57 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Walle X-Patchwork-Id: 1180920 X-Patchwork-Delegate: priyanka.jain@nxp.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (no SPF record) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=walle.cc Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (1024-bit key; unprotected) header.d=walle.cc header.i=@walle.cc header.b="K6y6FVhH"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 46xsp368Wbz9sCJ for ; Tue, 22 Oct 2019 10:11:23 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 4D2B6C21D8A; Mon, 21 Oct 2019 23:11:17 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 206CEC21C29; Mon, 21 Oct 2019 23:11:16 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 2E682C21C29; Mon, 21 Oct 2019 23:11:14 +0000 (UTC) Received: from ssl.serverraum.org (ssl.serverraum.org [176.9.125.105]) by lists.denx.de (Postfix) with ESMTPS id DCB4AC21BE5 for ; Mon, 21 Oct 2019 23:11:13 +0000 (UTC) Received: from apollo.fritz.box (unknown [IPv6:2a02:810c:c200:2e91:6257:18ff:fec4:ca34]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by ssl.serverraum.org (Postfix) with ESMTPSA id 27EF422433; Tue, 22 Oct 2019 01:11:13 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=walle.cc; s=mail2016061301; t=1571699473; bh=jTx4NVWxszjhEBD0GhS2pmLi0dUXA3TiW4ZgIcH82PY=; h=From:To:Cc:Subject:Date:From; b=K6y6FVhHJLqJYCRvRVHY3o6phyWATrZLqTfIXYM36kirjLtnZPraDB2p6VgiuoXYN pD/E5wLI4Lr6DxkaaO184zebJDcw/vEO/Yms0XGtqXWchq21WRFS3axcsG/6ZgVNTT yxRXp5X329OIECqr0lGXRnFoa8CQ42gMrHT/e+ws= From: Michael Walle To: u-boot@lists.denx.de Date: Tue, 22 Oct 2019 01:10:57 +0200 Message-Id: <20191021231057.13250-1-michael@walle.cc> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 X-Virus-Scanned: clamav-milter 0.101.4 at web X-Virus-Status: Clean Cc: Yinbo Zhu Subject: [U-Boot] [PATCH] armv8: fsl-lsch3: convert CONFIG_TARGET_x to CONFIG_ARCH_x X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The clocks are not dependent on the target but only on the SoC. Therefore, convert the CONFIG_TARGET_x macros to the corresponding CONFIG_ARCH_x. This will allow other targets to automatically use the common code. Otherwise every new target would have to add itself to the "#if defined(CONFIG_TARGET_x) || .." macros. Signed-off-by: Michael Walle --- arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c index b3e67321b4..bbd550b036 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c @@ -64,7 +64,7 @@ void get_sys_info(struct sys_info *sys_info) }; uint i, cluster; -#if defined(CONFIG_TARGET_LS1028ARDB) || defined(CONFIG_TARGET_LS1088ARDB) +#if defined(CONFIG_ARCH_LS1028A) || defined(CONFIG_ARCH_LS1088A) uint rcw_tmp; #endif uint freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS]; @@ -131,7 +131,7 @@ void get_sys_info(struct sys_info *sys_info) CONFIG_SYS_FSL_IFC_CLK_DIV; #endif -#if defined(CONFIG_TARGET_LS1028ARDB) || defined(CONFIG_TARGET_LS1088ARDB) +#if defined(CONFIG_ARCH_LS1028A) || defined(CONFIG_ARCH_LS1088A) #define HWA_CGA_M2_CLK_SEL 0x00380000 #define HWA_CGA_M2_CLK_SHIFT 19 rcw_tmp = in_le32(&gur->rcwsr[5]); @@ -159,7 +159,7 @@ void get_sys_info(struct sys_info *sys_info) break; } #endif -#if defined(CONFIG_TARGET_LX2160ARDB) || defined(CONFIG_TARGET_LS2080ARDB) +#if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LS2080A) sys_info->freq_cga_m2 = sys_info->freq_systembus; #endif } @@ -176,10 +176,10 @@ int get_clocks(void) #endif #if defined(CONFIG_FSL_ESDHC) #if defined(CONFIG_FSL_ESDHC_USE_PERIPHERAL_CLK) -#if defined(CONFIG_TARGET_LS1028ARDB) || defined(CONFIG_TARGET_LX2160ARDB) +#if defined(CONFIG_ARCH_LS1028A) || defined(CONFIG_ARCH_LX2160A) gd->arch.sdhc_clk = sys_info.freq_cga_m2 / 2; #endif -#if defined(CONFIG_TARGET_LS2080ARDB) || defined(CONFIG_TARGET_LS1088ARDB) +#if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) gd->arch.sdhc_clk = sys_info.freq_cga_m2; #endif #else