From patchwork Thu Nov 16 00:36:05 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Herrenschmidt X-Patchwork-Id: 838364 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3ycj3v271Kz9s7v for ; Thu, 16 Nov 2017 11:36:43 +1100 (AEDT) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3ycj3v0Y4szDqpj for ; Thu, 16 Nov 2017 11:36:43 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: ozlabs.org; spf=permerror (mailfrom) smtp.mailfrom=kernel.crashing.org (client-ip=63.228.1.57; helo=gate.crashing.org; envelope-from=benh@kernel.crashing.org; receiver=) Received: from gate.crashing.org (gate.crashing.org [63.228.1.57]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3ycj3p1XMtzDqpR for ; Thu, 16 Nov 2017 11:36:37 +1100 (AEDT) Received: from pasglop.ozlabs.ibm.com (localhost.localdomain [127.0.0.1]) by gate.crashing.org (8.14.1/8.14.1) with ESMTP id vAG0aB6e004806; Wed, 15 Nov 2017 18:36:14 -0600 From: Benjamin Herrenschmidt To: skiboot@lists.ozlabs.org Date: Thu, 16 Nov 2017 11:36:05 +1100 Message-Id: <20171116003606.25488-1-benh@kernel.crashing.org> X-Mailer: git-send-email 2.13.6 Subject: [Skiboot] [PATCH 1/2] phb4: Fix lost bit in PE number on config accesses X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.24 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" A PE number can be up to 9 bits, using a uint8_t won't fly.. That was causing error on config accesses to freeze the wrong PE. Signed-off-by: Benjamin Herrenschmidt --- hw/phb4.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/hw/phb4.c b/hw/phb4.c index 4f10db32..96a6e0de 100644 --- a/hw/phb4.c +++ b/hw/phb4.c @@ -257,7 +257,7 @@ static inline void phb4_ioda_sel(struct phb4 *p, uint32_t table, */ static int64_t phb4_pcicfg_check(struct phb4 *p, uint32_t bdfn, uint32_t offset, uint32_t size, - uint8_t *pe) + uint16_t *pe) { uint32_t sm = size - 1; @@ -437,7 +437,7 @@ static int64_t phb4_pcicfg_read(struct phb4 *p, uint32_t bdfn, { uint64_t addr, val64; int64_t rc; - uint8_t pe; + uint16_t pe; bool use_asb = false; rc = phb4_pcicfg_check(p, bdfn, offset, size, &pe); @@ -530,7 +530,7 @@ static int64_t phb4_pcicfg_write(struct phb4 *p, uint32_t bdfn, { uint64_t addr; int64_t rc; - uint8_t pe; + uint16_t pe; bool use_asb = false; rc = phb4_pcicfg_check(p, bdfn, offset, size, &pe); From patchwork Thu Nov 16 00:36:06 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Herrenschmidt X-Patchwork-Id: 838365 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3ycj4B6Bcgz9s7h for ; Thu, 16 Nov 2017 11:36:58 +1100 (AEDT) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3ycj4B4qjJzDqpX for ; Thu, 16 Nov 2017 11:36:58 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: ozlabs.org; spf=permerror (mailfrom) smtp.mailfrom=kernel.crashing.org (client-ip=63.228.1.57; helo=gate.crashing.org; envelope-from=benh@kernel.crashing.org; receiver=) Received: from gate.crashing.org (gate.crashing.org [63.228.1.57]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3ycj3q3LWbzDqpR for ; Thu, 16 Nov 2017 11:36:39 +1100 (AEDT) Received: from pasglop.ozlabs.ibm.com (localhost.localdomain [127.0.0.1]) by gate.crashing.org (8.14.1/8.14.1) with ESMTP id vAG0aB6f004806; Wed, 15 Nov 2017 18:36:16 -0600 From: Benjamin Herrenschmidt To: skiboot@lists.ozlabs.org Date: Thu, 16 Nov 2017 11:36:06 +1100 Message-Id: <20171116003606.25488-2-benh@kernel.crashing.org> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171116003606.25488-1-benh@kernel.crashing.org> References: <20171116003606.25488-1-benh@kernel.crashing.org> Subject: [Skiboot] [PATCH 2/2] phb4: Fix PE mapping of M32 BAR X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.24 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" The M32 BAR is the PHB4 region used to map all the non-prefetchable or 32-bit device BARs. It's supposed to have its segments remapped via the MDT and Linux relies on that to assign them individual PE#. However, we weren't configuring that properly and instead used the mode where PE# == segment#, thus causing EEH to freeze the wrong device or PE#. Signed-off-by: Benjamin Herrenschmidt --- hw/phb4.c | 24 +++++++++++------------- 1 file changed, 11 insertions(+), 13 deletions(-) diff --git a/hw/phb4.c b/hw/phb4.c index 96a6e0de..454820d6 100644 --- a/hw/phb4.c +++ b/hw/phb4.c @@ -873,19 +873,15 @@ static uint64_t phb4_default_mbt0(struct phb4 *p, unsigned int bar_idx) switch (p->mbt_size - bar_idx - 1) { case 0: mbt0 = SETFIELD(IODA3_MBT0_MODE, 0ull, IODA3_MBT0_MODE_MDT); - mbt0 = SETFIELD(IODA3_MBT0_MDT_COLUMN, mbt0, 0); + mbt0 = SETFIELD(IODA3_MBT0_MDT_COLUMN, mbt0, 3); break; case 1: mbt0 = SETFIELD(IODA3_MBT0_MODE, 0ull, IODA3_MBT0_MODE_MDT); - mbt0 = SETFIELD(IODA3_MBT0_MDT_COLUMN, mbt0, 1); - break; - case 2: - mbt0 = SETFIELD(IODA3_MBT0_MODE, 0ull, IODA3_MBT0_MODE_MDT); mbt0 = SETFIELD(IODA3_MBT0_MDT_COLUMN, mbt0, 2); break; - case 3: + case 2: mbt0 = SETFIELD(IODA3_MBT0_MODE, 0ull, IODA3_MBT0_MODE_MDT); - mbt0 = SETFIELD(IODA3_MBT0_MDT_COLUMN, mbt0, 3); + mbt0 = SETFIELD(IODA3_MBT0_MDT_COLUMN, mbt0, 1); break; default: mbt0 = SETFIELD(IODA3_MBT0_MODE, 0ull, IODA3_MBT0_MODE_PE_SEG); @@ -957,16 +953,18 @@ static void phb4_init_ioda_cache(struct phb4 *p) } } - for (i = 0; i < p->mbt_size; i++) { + + /* Initialize MBT entries for BARs 1...N */ + for (i = 1; i < p->mbt_size; i++) { p->mbt_cache[i][0] = phb4_default_mbt0(p, i); p->mbt_cache[i][1] = 0; } - /* Initialise M32 bar using MDT entry 0 */ - p->mbt_cache[0][0] |= IODA3_MBT0_TYPE_M32 | - (p->mm1_base & IODA3_MBT0_BASE_ADDR); - p->mbt_cache[0][1] = IODA3_MBT1_ENABLE | - ((~(M32_PCI_SIZE - 1)) & IODA3_MBT1_MASK); + /* Initialize M32 bar using MBT entry 0, MDT colunm A */ + p->mbt_cache[0][0] = SETFIELD(IODA3_MBT0_MODE, 0ull, IODA3_MBT0_MODE_MDT); + p->mbt_cache[0][0] |= SETFIELD(IODA3_MBT0_MDT_COLUMN, 0ull, 0); + p->mbt_cache[0][0] |= IODA3_MBT0_TYPE_M32 | (p->mm1_base & IODA3_MBT0_BASE_ADDR); + p->mbt_cache[0][1] = IODA3_MBT1_ENABLE | ((~(M32_PCI_SIZE - 1)) & IODA3_MBT1_MASK); } static int64_t phb4_wait_bit(struct phb4 *p, uint32_t reg,