From patchwork Wed Nov 15 14:17:52 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Goldschmidt X-Patchwork-Id: 838195 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3ycRMW0nmlz9s7v for ; Thu, 16 Nov 2017 01:19:18 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id BC098C21D8D; Wed, 15 Nov 2017 14:18:34 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 4AB56C21DC5; Wed, 15 Nov 2017 14:18:32 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id F0D14C21DB1; Wed, 15 Nov 2017 14:17:56 +0000 (UTC) Received: from mailout.pepperl-fuchs.com (mailout.pepperl-fuchs.com [212.21.166.229]) by lists.denx.de (Postfix) with ESMTPS id E5EC8C21D80 for ; Wed, 15 Nov 2017 14:17:52 +0000 (UTC) Received: from PFDE-CAS1.EU.P-F.BIZ (pfde-cas1.eu.p-f.biz [172.24.5.133]) by mailout.pepperl-fuchs.com (Postfix) with ESMTP id BE15381D4F; Wed, 15 Nov 2017 15:17:52 +0100 (CET) Received: from PFDE-MX11.EU.P-F.BIZ ([fe80::d571:1e54:8f01:3111]) by PFDE-CAS1.EU.P-F.BIZ ([::1]) with mapi id 14.03.0301.000; Wed, 15 Nov 2017 15:17:52 +0100 From: Goldschmidt Simon To: Vignesh R , Marek Vasut , Jagan Teki , Jason Rush Thread-Topic: [PATCH 1/2] common: make bouncebuf work for non-DMA transfers Thread-Index: AdNeHEImTRteK4O0RC+VObV9owLynQ== Date: Wed, 15 Nov 2017 14:17:52 +0000 Message-ID: Accept-Language: de-DE, en-US Content-Language: de-DE X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [172.24.5.147] x-exclaimer-md-config: 1e262833-c6b8-4d86-a546-40bddc43f2e2 MIME-Version: 1.0 Cc: "u-boot@lists.denx.de" Subject: [U-Boot] [PATCH 1/2] common: make bouncebuf work for non-DMA transfers X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Bounce buffer may be used for CPU-only transfers (this is currently the case for cadence_qspi). However, in this case, invalidating the data cache might throw away copied data that is still in the cache only. To make CPU-only transfers work with bouncebuf (but still take advantage of having aligned buffers), a new flag 'GEN_BB_NODMA' is introduced. If this flag is set, cache flushing/invalidation is skipped and only the alignment part of bouncebuf is active. Signed-off-by: Simon Goldschmidt --- common/bouncebuf.c | 9 +++++---- include/bouncebuf.h | 9 +++++++++ 2 files changed, 14 insertions(+), 4 deletions(-) diff --git a/common/bouncebuf.c b/common/bouncebuf.c index 054d9e0302..0d18477f13 100644 --- a/common/bouncebuf.c +++ b/common/bouncebuf.c @@ -55,16 +55,17 @@ int bounce_buffer_start(struct bounce_buffer *state, void *data, * Flush data to RAM so DMA reads can pick it up, * and any CPU writebacks don't race with DMA writes */ - flush_dcache_range((unsigned long)state->bounce_buffer, - (unsigned long)(state->bounce_buffer) + - state->len_aligned); + if (!(state->flags & GEN_BB_NODMA)) + flush_dcache_range((unsigned long)state->bounce_buffer, + (unsigned long)(state->bounce_buffer) + + state->len_aligned); return 0; } int bounce_buffer_stop(struct bounce_buffer *state) { - if (state->flags & GEN_BB_WRITE) { + if ((state->flags & (GEN_BB_WRITE|GEN_BB_NODMA)) == GEN_BB_WRITE) { /* Invalidate cache so that CPU can see any newly DMA'd data */ invalidate_dcache_range((unsigned long)state->bounce_buffer, (unsigned long)(state->bounce_buffer) + diff --git a/include/bouncebuf.h b/include/bouncebuf.h index 5ffa99bc13..c6720b3b2e 100644 --- a/include/bouncebuf.h +++ b/include/bouncebuf.h @@ -37,6 +37,15 @@ */ #define GEN_BB_RW (GEN_BB_READ | GEN_BB_WRITE) +/* + * GEN_BB_NODMA -- Data is read/written by CPU only (no DMA), so no cache + * flushing and invalidating is required. Not passing this for GEN_BB_WRITE + * transfers done by the CPU (not DMA) may result in invalid data as the data + * written into the cache is lost by invalidating the dcache after the transfer + * (unless a writethrough cache is used). + */ +#define GEN_BB_NODMA (1 << 2) + struct bounce_buffer { /* Copy of data parameter passed to start() */ void *user_buffer; From patchwork Wed Nov 15 14:17:54 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Simon Goldschmidt X-Patchwork-Id: 838194 X-Patchwork-Delegate: jagannadh.teki@gmail.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3ycRLx0pWvz9s7v for ; Thu, 16 Nov 2017 01:18:49 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id B6CC8C21C29; Wed, 15 Nov 2017 14:18:13 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=none autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 59E5FC21DA3; Wed, 15 Nov 2017 14:18:11 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 5DA40C21C73; Wed, 15 Nov 2017 14:17:58 +0000 (UTC) Received: from mailout.pepperl-fuchs.com (mailout.pepperl-fuchs.com [212.21.166.229]) by lists.denx.de (Postfix) with ESMTPS id DBC9AC21DA2 for ; Wed, 15 Nov 2017 14:17:54 +0000 (UTC) Received: from PFDE-CAS2.EU.P-F.BIZ (pfde-cas2.eu.p-f.biz [172.24.5.134]) by mailout.pepperl-fuchs.com (Postfix) with ESMTP id BA6D081D51; Wed, 15 Nov 2017 15:17:54 +0100 (CET) Received: from PFDE-MX11.EU.P-F.BIZ ([fe80::d571:1e54:8f01:3111]) by PFDE-CAS2.EU.P-F.BIZ ([fe80::8109:cac5:bde5:6fd3%18]) with mapi id 14.03.0301.000; Wed, 15 Nov 2017 15:17:54 +0100 From: Goldschmidt Simon To: Vignesh R , Marek Vasut , Jagan Teki , Jason Rush Thread-Topic: [PATCH 2/2] spi: cadence_spi_apb: fix using bouncebuf with writeback dcache Thread-Index: AdNeHFf2lWyOajisQKuWlIr9ubd82w== Date: Wed, 15 Nov 2017 14:17:54 +0000 Message-ID: Accept-Language: de-DE, en-US Content-Language: de-DE X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [172.24.5.147] x-exclaimer-md-config: 1e262833-c6b8-4d86-a546-40bddc43f2e2 MIME-Version: 1.0 Cc: "u-boot@lists.denx.de" Subject: [U-Boot] [PATCH 2/2] spi: cadence_spi_apb: fix using bouncebuf with writeback dcache X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The last two commits on this file have added bounce buffer handling to indirect read and write transfers. However, these are cpu-only transfers and bouncebuf seems to be written for dma transfers only (it invalidates the dcache in bouncebuf_stop, which throws away data copied by the cpu that are still in cache only). The last two commits resulted in reading random data on mach-socfpga. By using the new flag GEN_BB_NODMA, cadence_qspi is fixed on that platform (although the 'Sync DT bindings with Linux' patches from Jason Rush are still needed to make it work). Signed-off-by: Simon Goldschmidt --- drivers/spi/cadence_qspi_apb.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c index 7d335519b0..a3e1c84758 100644 --- a/drivers/spi/cadence_qspi_apb.c +++ b/drivers/spi/cadence_qspi_apb.c @@ -645,7 +645,7 @@ int cadence_qspi_apb_indirect_read_execute(struct cadence_spi_platdata *plat, writel(CQSPI_REG_INDIRECTRD_START, plat->regbase + CQSPI_REG_INDIRECTRD); - ret = bounce_buffer_start(&bb, (void *)rxbuf, n_rx, GEN_BB_WRITE); + ret = bounce_buffer_start(&bb, (void *)rxbuf, n_rx, GEN_BB_WRITE|GEN_BB_NODMA); if (ret) return ret; bb_rxbuf = bb.bounce_buffer; @@ -743,7 +743,7 @@ int cadence_qspi_apb_indirect_write_execute(struct cadence_spi_platdata *plat, * Handle non-4-byte aligned accesses via bounce buffer to * avoid data abort. */ - ret = bounce_buffer_start(&bb, (void *)txbuf, n_tx, GEN_BB_READ); + ret = bounce_buffer_start(&bb, (void *)txbuf, n_tx, GEN_BB_READ|GEN_BB_NODMA); if (ret) return ret; bb_txbuf = bb.bounce_buffer;