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[73.202.231.77]) by smtp.googlemail.com with ESMTPSA id n15sm453714pjt.13.2019.10.15.18.05.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Oct 2019 18:05:56 -0700 (PDT) From: Steve Longerbeam To: Daniel Lezcano , Thomas Gleixner , Rob Herring , Mark Rutland , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , linux-kernel@vger.kernel.org (open list:CLOCKSOURCE, CLOCKEVENT DRIVERS), devicetree@vger.kernel.org (open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS), linux-arm-kernel@lists.infradead.org (moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE) Cc: Steve Longerbeam Subject: [PATCH 2/2] dt-bindings: timer: imx: gpt: Add pin group bindings for input capture Date: Tue, 15 Oct 2019 18:05:44 -0700 Message-Id: <20191016010544.14561-3-slongerbeam@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20191016010544.14561-1-slongerbeam@gmail.com> References: <20191016010544.14561-1-slongerbeam@gmail.com> Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add pin group bindings to support input capture function of the i.MX GPT. Signed-off-by: Steve Longerbeam --- .../devicetree/bindings/timer/fsl,imxgpt.txt | 28 +++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/Documentation/devicetree/bindings/timer/fsl,imxgpt.txt b/Documentation/devicetree/bindings/timer/fsl,imxgpt.txt index 5d8fd5b52598..32797b7b0d02 100644 --- a/Documentation/devicetree/bindings/timer/fsl,imxgpt.txt +++ b/Documentation/devicetree/bindings/timer/fsl,imxgpt.txt @@ -33,6 +33,13 @@ Required properties: an entry for each entry in clock-names. - clock-names : must include "ipg" entry first, then "per" entry. +Optional properties: + +- pinctrl-0: For the i.MX GPT to support the Input Capture function, + the input capture channel pin groups must be listed here. +- pinctrl-names: must be "default". + + Example: gpt1: timer@10003000 { @@ -43,3 +50,24 @@ gpt1: timer@10003000 { <&clks IMX27_CLK_PER1_GATE>; clock-names = "ipg", "per"; }; + + +Example with input capture channel 0 support: + +pinctrl_gpt_input_capture0: gptinputcapture0grp { + fsl,pins = < + MX6QDL_PAD_SD1_DAT0__GPT_CAPTURE1 0x1b0b0 + >; +}; + +gpt: gpt@2098000 { + compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt"; + reg = <0x02098000 0x4000>; + interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clks IMX6QDL_CLK_GPT_IPG>, + <&clks IMX6QDL_CLK_GPT_IPG_PER>, + <&clks IMX6QDL_CLK_GPT_3M>; + clock-names = "ipg", "per", "osc_per"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpt_input_capture0>; +};