From patchwork Fri Oct 11 07:13:59 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Steven Hao X-Patchwork-Id: 1175130 X-Patchwork-Delegate: trini@ti.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=outlook.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=outlook.com header.i=@outlook.com header.b="Y39vNUSB"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 46qRSl10fyz9sCJ for ; Fri, 11 Oct 2019 23:04:04 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id BC414C21D83; Fri, 11 Oct 2019 12:03:58 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=FREEMAIL_FROM, SPF_HELO_PASS, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 3DA5DC21D65; Fri, 11 Oct 2019 12:02:03 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id D92BBC21C38; Fri, 11 Oct 2019 07:14:09 +0000 (UTC) Received: from APC01-SG2-obe.outbound.protection.outlook.com (mail-oln040092253038.outbound.protection.outlook.com [40.92.253.38]) by lists.denx.de (Postfix) with ESMTPS id 18D54C21BE5 for ; Fri, 11 Oct 2019 07:14:07 +0000 (UTC) ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=mBmcRLjSqIGlBBp8TVwUi6MVKVYSndERtyyzmEPn4aSDRt71NpVbhy1T+oBV+rOXJMNcp8+ckbKUn/h75W7UqJsGs+SgvZhwbudCGY2WaMjsT99UClNPNSeZK0FQZAPtOWZQblF8a0eUipkHdOzmn/PJVCEEO338KgnNsCDM5Pp8c7cOXNN5x0ISAJgZBVOadNaNDxZhCdt27m/7+nJmsVMSg6+JTzt9Lhd12QaqMZnuotrfmKMqJRmwAqmzIKjngz0ws8tT/XeTrTPa+HSVeOXOo0W8xJQP/dXaUHq5bAlwwwJ085mCwuDCiZAnyiYKwEYI1+foipg2QB58o73ouQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=hwL/E8IgL4hFw5STbALwSAjmJabpqq+Wccjf0JwyU6c=; b=gUoLkqa27nEriIUnZJAAbcZmXSjbHNtDzNjFizTmOj3vanGRo0PmsIm5vF4ITJKrOu1GJMuCMBnsqJJXmDULXyZ56wF1clmYJAuEXEGE/Uz/F71UVwKVzXm7p0UYXF3AY+km7flHWaPU2P3NJfQ8+JvSNzq1ZDBx/w9ThHlvsrf1K1Vly8ZxTZ9dj1CzhUhCH02aG8rPn3LVvWNxN910TjWgU5z9Axkajs/kVnGG+xNeVKZkfBVfD8DG4396+tYslnCGZl0CiCiLuKDEorOdZcTJCAOpLerK60GVCO7F6F8XSAujT0xKl3qz70ZLTKzaxghu83gj1YqreZKaOVEMSw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=none; dmarc=none; dkim=none; arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=outlook.com; s=selector1; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=hwL/E8IgL4hFw5STbALwSAjmJabpqq+Wccjf0JwyU6c=; b=Y39vNUSBSZtR3ltRrJ3181dJZLdlNxszj44v2XvLHMriOfoupUFq2aTidK6vXZnlOjFjE0o/D0A9LAhK41Zqay7NowwGdyeeYjWR6NALYOOQfJQULgxthpI+4ByZleGt7AMjC76Pg3pTic2gwac3hBfUQLv0dpPiaQefhzsTKl4s3zT96kblSDmhy4GsHpaQCB0SrE0tud3kvwyd/cKAE59CdZxEXbvs8/5Pn0LDSPxbdd7MfnyQMRplHlIa+0aFQsod6J46W4eJS64th88G+P5bp/heUzSVJ5kGyM6TKS0wxxyJRej/7HYSkS3eUarsgmqNL9+YyNgzZ1N/X4edSg== Received: from HK2APC01FT013.eop-APC01.prod.protection.outlook.com (10.152.248.57) by HK2APC01HT050.eop-APC01.prod.protection.outlook.com (10.152.249.154) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.2347.16; Fri, 11 Oct 2019 07:14:00 +0000 Received: from HK0PR03MB3953.apcprd03.prod.outlook.com (10.152.248.53) by HK2APC01FT013.mail.protection.outlook.com (10.152.248.160) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.20.2347.16 via Frontend Transport; Fri, 11 Oct 2019 07:14:00 +0000 Received: from HK0PR03MB3953.apcprd03.prod.outlook.com ([fe80::c80c:4c1d:ab34:85de]) by HK0PR03MB3953.apcprd03.prod.outlook.com ([fe80::c80c:4c1d:ab34:85de%6]) with mapi id 15.20.2347.021; Fri, 11 Oct 2019 07:14:00 +0000 From: liu hao To: "xypron.glpk@gmx.de" , "albert.u.boot@aribaud.net" Thread-Topic: [PATCH v2] arm: add initial support for the Phytium FT2004 SoC Thread-Index: AQHVgAN0Drdk5z0MQU63HF2hRr+Zvg== Date: Fri, 11 Oct 2019 07:13:59 +0000 Message-ID: Accept-Language: zh-CN, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-clientproxiedby: HK0PR04CA0015.apcprd04.prod.outlook.com (2603:1096:203:36::27) To HK0PR03MB3953.apcprd03.prod.outlook.com (2603:1096:203:98::21) x-incomingtopheadermarker: OriginalChecksum:C00765D7217E7D4F0B7CA4B3B883A8F45CB6534B4D8936BEA9FDDC55DEB627BE; UpperCasedChecksum:55341CE1A818FFCCF906E65C8691AE941EBC06FD83DB6DE6E5EDED8B96F2F806; SizeAsReceived:8442; Count:49 x-ms-exchange-messagesentrepresentingtype: 1 x-mailer: git-send-email 2.7.4 x-tmn: [GfOmdzbqDi+sRtDFHY59GbJJkdPWJxU8] x-microsoft-original-message-id: <1570777991-22222-1-git-send-email-steven_hao5189@outlook.com> x-ms-publictraffictype: Email x-incomingheadercount: 49 x-eopattributedmessage: 0 x-ms-exchange-slblob-mailprops: =?iso-8859-1?q?wA9o+SYgtsCLhtQBjIqWonG/om?= =?iso-8859-1?q?XvULEXxLxfSQ+nUY0KL9yKRy4fLlYS27DVhnH/1hugHaqI4DQeA?= =?iso-8859-1?q?Or8bMaYhBpsjf6T1DlUl4Q7mWzTkJEBxQgAHCnESbTL+1Jj3JXB?= =?iso-8859-1?q?m8FyqYvxQ0rf3k0DSK3BS8ouAEUtz31KkY4qo3ZH5DsDle7dD5H?= =?iso-8859-1?q?SCxwpF8qt/sdpsysKPa6fgML+E7fxN7hfCpQ7PiI/uYbHlPTu3P?= =?iso-8859-1?q?+fpEJyr+12uTpTAAWrBq6LYpXiqGToXAg5mWXyew+qdKfwxZyiH?= =?iso-8859-1?q?5cojfZIpAueIflVmjAFXNovgJR8XcGLeEUjM6Ee9ARx1HvIAqYn?= =?iso-8859-1?q?MFRPk/KNOzYoRDyXxxqXYIuC+mQKeQinoLveJ41QdFM9XPaonUO?= =?iso-8859-1?q?p/LroxYUWGBOdA/gYA3yBj3KJzpv0UvuZ92P/Rh7o6H/alupFJO?= =?iso-8859-1?q?1Tu6qVG8G1xbCKbqKRZkTyGKnYQo17W9O5y8ih2DtdO9JUvtjfr?= =?iso-8859-1?q?PBEOSGRKDJalmE5QAEtCWxdQD6fMEPyTcrO8rQJO/eZbd7g/gvr?= =?iso-8859-1?q?nZNx9NBHLPYiTJgXNFFPLA0KU5L4MloMnOtB00sWbK+KQpgQHan?= =?iso-8859-1?q?wbKzZcAjggpulTfLvyqNdvRXRFMJcEhTEJ7hFNKml5lpbFQGgIh?= =?iso-8859-1?q?46jSrBB8hvULUzeWzxrZJcaSDWp5GASNKAYC/TAGAWnARhG7wL6?= =?iso-8859-1?q?FlmKbhBh+DB8cBYsR1Jh9IzOM5Ubz22bQ+KftGdTUGFgbPisRxP?= =?iso-8859-1?q?mC1I8Kv37vS+bxQDXThuPaR3fOzNoQdPreK1t0zcHyYTR98cumk?= =?iso-8859-1?q?D6Ar8JMQbO1cafbReLfSZSrMA2L1AMBoWB4dKPVRMNw/CU+vPuM?= =?iso-8859-1?q?y/Jaodnz6tCxDFWH9+QtVSOd5tzRSB5U9mI24WiARPVtARpCF/h?= =?iso-8859-1?q?iHhwbyI7oFju5rgT6/iRpuPunbZ3X5j/bchnjvJgN+Xdw4Nh8rF?= =?iso-8859-1?q?dMUx7khvi8cELMaxYA+AP6XzeqkZvKX1TRfC5C1RnIZgKyrBfpp?= =?iso-8859-1?q?rHfaFNilzr+sV/OxPKSEzIU690xgDjKSvjoDftWtdxOCReJw4ow?= =?iso-8859-1?q?=3D=3D?= x-ms-traffictypediagnostic: HK2APC01HT050: x-ms-exchange-purlcount: 2 x-microsoft-antispam: BCL:0; x-microsoft-antispam-message-info: q5aOyP4D5hV724sWU1gB1oPSwN6fZSpYRQhWL9wcZT39u3c9pK2GKgqdTMsL2L1JpUR1cU3KUUzGKj7x6ugVvmRiPz0rAFHUQdlf3MqsrYVjf7GuAqp5IankQ99oEH/vYp8gOcimSHtkiUxIvKcDrPpX0Y/y5JxrsSSKO1boFZPR3xqE84fMLhLWNTbX7ksYJsmQdWp7cTW5c3nfFF7t0XHOmpUvOjra4WhIC/Ll/k0= x-ms-exchange-transport-forked: True MIME-Version: 1.0 X-OriginatorOrg: outlook.com X-MS-Exchange-CrossTenant-RMS-PersistedConsumerOrg: 00000000-0000-0000-0000-000000000000 X-MS-Exchange-CrossTenant-Network-Message-Id: e5b7fdda-4aec-43fc-68c1-08d74e1a966c X-MS-Exchange-CrossTenant-rms-persistedconsumerorg: 00000000-0000-0000-0000-000000000000 X-MS-Exchange-CrossTenant-originalarrivaltime: 11 Oct 2019 07:13:59.9365 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Internet X-MS-Exchange-CrossTenant-id: 84df9e7f-e9f6-40af-b435-aaaaaaaaaaaa X-MS-Exchange-Transport-CrossTenantHeadersStamped: HK2APC01HT050 X-Mailman-Approved-At: Fri, 11 Oct 2019 12:02:02 +0000 Cc: Tom Rini , "liuhao@phytium.com.cn" , liu hao , "ryder.lee@mediatek.com" , "sr@denx.de" , "u-boot@lists.denx.de" Subject: [U-Boot] [PATCH v2] arm: add initial support for the Phytium FT2004 SoC X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This adds platform code and the device tree for the Phytium FT2004 SoC. The initial support comprises the UART and the GMAC. v2: - Some printf() are removed or replace by debug(). @Tom - The ft2004_defconfig file is generated with savedefconfig. @Tom, @Heinrich Cc: Tom Rini Cc: Heinrich Schuchardt Signed-off-by: Steven Hao --- MAINTAINERS | 6 +++ arch/arm/Kconfig | 8 ++++ arch/arm/dts/Makefile | 2 + arch/arm/dts/phytium-ft2004.dts | 33 ++++++++++++++ board/phytium/ft2004/Kconfig | 12 +++++ board/phytium/ft2004/MAINTAINERS | 8 ++++ board/phytium/ft2004/Makefile | 9 ++++ board/phytium/ft2004/cpu.h | 23 ++++++++++ board/phytium/ft2004/ft2004.c | 95 ++++++++++++++++++++++++++++++++++++++++ configs/ft2004_defconfig | 23 ++++++++++ include/configs/ft2004.h | 24 ++++++++++ 11 files changed, 243 insertions(+) create mode 100644 arch/arm/dts/phytium-ft2004.dts create mode 100644 board/phytium/ft2004/Kconfig create mode 100644 board/phytium/ft2004/MAINTAINERS create mode 100644 board/phytium/ft2004/Makefile create mode 100644 board/phytium/ft2004/cpu.h create mode 100644 board/phytium/ft2004/ft2004.c create mode 100644 configs/ft2004_defconfig create mode 100644 include/configs/ft2004.h diff --git a/MAINTAINERS b/MAINTAINERS index c536566..1f354b0 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -468,6 +468,12 @@ S: Maintained T: git https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze.git F: arch/arm/mach-zynqmp-r5/ +ARM PHYTIUM +M: liuhao +M: shuyiqi +S: Maintained +F: arch/arm/dts/phytium-ft2004.dts + BINMAN M: Simon Glass S: Maintained diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 384e382..b4a7cb0 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1612,6 +1612,13 @@ config ARCH_ASPEED select OF_CONTROL imply CMD_DM +config TARGET_FT2004 + bool "Support Phytium FT2004 Platform" + select ARM64 + help + Support for FT2004 platform. + It has 1GB Sdram, uart and gmac. + endchoice config ARCH_SUPPORT_TFABOOT @@ -1812,6 +1819,7 @@ source "board/woodburn/Kconfig" source "board/xilinx/Kconfig" source "board/xilinx/zynq/Kconfig" source "board/xilinx/zynqmp/Kconfig" +source "board/phytium/ft2004/Kconfig" source "arch/arm/Kconfig.debug" diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 73d47f5..d6144fe 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -816,6 +816,8 @@ dtb-$(CONFIG_TARGET_VEXPRESS_CA5X2) += vexpress-v2p-ca5s.dtb dtb-$(CONFIG_TARGET_VEXPRESS_CA9X4) += vexpress-v2p-ca9.dtb dtb-$(CONFIG_TARGET_VEXPRESS_CA15_TC2) += vexpress-v2p-ca15_a7.dtb +dtb-$(CONFIG_TARGET_FT2004) += phytium-ft2004.dtb + targets += $(dtb-y) # Add any required device tree compiler flags here diff --git a/arch/arm/dts/phytium-ft2004.dts b/arch/arm/dts/phytium-ft2004.dts new file mode 100644 index 0000000..e34cb09 --- /dev/null +++ b/arch/arm/dts/phytium-ft2004.dts @@ -0,0 +1,33 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019, Phytium Ltd. + * shuyiqi + */ + +/dts-v1/; + +/ { + model = "Phytium FT2004"; + compatible = "phytium,ft2004"; + #address-cells = <2>; + #size-cells = <2>; + + ethernet@2820c000 { + compatible = "st,stm32-dwmac"; + reg = <0x0 0x2820C000 0x0 0x2000>; + phy-mode = "rgmii"; + }; + + ethernet@28210000 { + compatible = "st,stm32-dwmac"; + reg = <0x0 0x28210000 0x0 0x2000>; + phy-mode = "rgmii"; + }; + + uart@28001000 { + compatible = "arm,pl011"; + reg = <0x0 0x28001000 0x0 0x1000>; + clock = <48000000>; + }; +}; + diff --git a/board/phytium/ft2004/Kconfig b/board/phytium/ft2004/Kconfig new file mode 100644 index 0000000..865a609 --- /dev/null +++ b/board/phytium/ft2004/Kconfig @@ -0,0 +1,12 @@ +if TARGET_FT2004 + +config SYS_BOARD + default "ft2004" + +config SYS_VENDOR + default "phytium" + +config SYS_CONFIG_NAME + default "ft2004" + +endif diff --git a/board/phytium/ft2004/MAINTAINERS b/board/phytium/ft2004/MAINTAINERS new file mode 100644 index 0000000..8ddbb23 --- /dev/null +++ b/board/phytium/ft2004/MAINTAINERS @@ -0,0 +1,8 @@ +FT2004 BOARD +M: liuhao +M: shuyiqi +S: Maintained +F: board/phytium/ft2004/* +F: include/configs/ft2004.h +F: configs/ft2004_defconfig + diff --git a/board/phytium/ft2004/Makefile b/board/phytium/ft2004/Makefile new file mode 100644 index 0000000..e860789 --- /dev/null +++ b/board/phytium/ft2004/Makefile @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2019 +# shuyiqi +# liuhao +# + +obj-y += ft2004.o + diff --git a/board/phytium/ft2004/cpu.h b/board/phytium/ft2004/cpu.h new file mode 100644 index 0000000..3574a6b --- /dev/null +++ b/board/phytium/ft2004/cpu.h @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2019 + * Phytium Technology Ltd + * shuyiqi + */ + +#ifndef _FT2004_CPU_H +#define _FT2004_CPU_H + +/* FLUSH L3 CASHE */ +#define HNF_COUNT 0x8 +#define HNF_PSTATE_REQ (HNF_BASE + 0x10) +#define HNF_PSTATE_STAT (HNF_BASE + 0x18) +#define HNF_PSTATE_OFF 0x0 +#define HNF_PSTATE_SFONLY 0x1 +#define HNF_PSTATE_HALF 0x2 +#define HNF_PSTATE_FULL 0x3 +#define HNF_STRIDE 0x10000 +#define HNF_BASE (unsigned long)(0x3A200000) + +#endif /* _FT2004_CPU_H */ + diff --git a/board/phytium/ft2004/ft2004.c b/board/phytium/ft2004/ft2004.c new file mode 100644 index 0000000..fd54314 --- /dev/null +++ b/board/phytium/ft2004/ft2004.c @@ -0,0 +1,95 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019 + * shuyiqi + * liuhao + */ + +#include +#include +#include +#include +#include +#include +#include +#include "cpu.h" + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + gd->mem_clk = 0; + gd->ram_size = PHYS_SDRAM_1_SIZE; + return 0; +} + +int dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + + return 0; +} + +int board_init(void) +{ + return 0; +} + +void reset_cpu(ulong addr) +{ + struct arm_smccc_res res; + + arm_smccc_smc(0x84000009, 0, 0, 0, 0, 0, 0, 0, &res); + debug("reset cpu error, %lx\n", res.a0); +} + +static struct mm_region ft2004_mem_map[] = { + { + .virt = 0x0UL, + .phys = 0x0UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | + PTE_BLOCK_UXN + }, + { + .virt = (u64)PHYS_SDRAM_1, + .phys = (u64)PHYS_SDRAM_1, + .size = (u64)PHYS_SDRAM_1_SIZE, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_NS | + PTE_BLOCK_INNER_SHARE + }, + { + 0, + } +}; + +struct mm_region *mem_map = ft2004_mem_map; + +int print_cpuinfo(void) +{ + printf("CPU: Phytium ft2004 %ld MHz\n", gd->cpu_clk); + return 0; +} + +int __asm_flush_l3_dcache(void) +{ + int i, pstate; + + for (i = 0; i < HNF_COUNT; i++) + writeq(HNF_PSTATE_SFONLY, HNF_PSTATE_REQ + i * HNF_STRIDE); + for (i = 0; i < HNF_COUNT; i++) { + do { + pstate = readq(HNF_PSTATE_STAT + i * HNF_STRIDE); + } while ((pstate & 0xf) != (HNF_PSTATE_SFONLY << 2)); + } + + for (i = 0; i < HNF_COUNT; i++) + writeq(HNF_PSTATE_FULL, HNF_PSTATE_REQ + i * HNF_STRIDE); + + return 0; +} + diff --git a/configs/ft2004_defconfig b/configs/ft2004_defconfig new file mode 100644 index 0000000..875d529 --- /dev/null +++ b/configs/ft2004_defconfig @@ -0,0 +1,23 @@ +CONFIG_ARM=y +CONFIG_ARM_SMCCC=y +CONFIG_TARGET_FT2004=y +CONFIG_SYS_TEXT_BASE=0x88000000 +CONFIG_NR_DRAM_BANKS=1 +# CONFIG_PSCI_RESET is not set +CONFIG_AHCI=y +# CONFIG_DISPLAY_CPUINFO is not set +# CONFIG_DISPLAY_BOARDINFO is not set +CONFIG_SYS_PROMPT="ft2004#" +# CONFIG_CMD_LZMADEC is not set +# CONFIG_CMD_UNZIP is not set +CONFIG_CMD_TFTPPUT=y +CONFIG_CMD_PING=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="phytium-ft2004" +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_DM=y +# CONFIG_MMC is not set +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_DM_SERIAL=y +CONFIG_PL01X_SERIAL=y diff --git a/include/configs/ft2004.h b/include/configs/ft2004.h new file mode 100644 index 0000000..227d25b --- /dev/null +++ b/include/configs/ft2004.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2019 + * shuyiqi + * liuhao + */ + +#ifndef __FT_2004_CONFIG_H__ +#define __FT_2004_CONFIG_H__ + +/* Sdram Bank #1 Address */ +#define PHYS_SDRAM_1 0x80000000 +#define PHYS_SDRAM_1_SIZE 0x7B000000 +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 + +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000000) + +/* Size of Malloc Pool */ +#define CONFIG_ENV_SIZE 4096 +#define CONFIG_SYS_MALLOC_LEN (1 * 1024 * 1024 + CONFIG_ENV_SIZE) + +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE - 0x100000) + +#endif