From patchwork Thu Oct 10 12:09:58 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Pratik R. Sampat" X-Patchwork-Id: 1174834 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 46q77W3TxFz9sPJ for ; Fri, 11 Oct 2019 10:48:07 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 46q77W24vYzDqRr for ; Fri, 11 Oct 2019 10:48:07 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=linux.ibm.com (client-ip=148.163.156.1; helo=mx0a-001b2d01.pphosted.com; envelope-from=psampat@linux.ibm.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 46pqfP3jvnzDr4Q for ; Thu, 10 Oct 2019 23:10:14 +1100 (AEDT) Received: from pps.filterd (m0098396.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x9AC8bVi143429 for ; Thu, 10 Oct 2019 08:10:12 -0400 Received: from e06smtp02.uk.ibm.com (e06smtp02.uk.ibm.com [195.75.94.98]) by mx0a-001b2d01.pphosted.com with ESMTP id 2vj18kpnxe-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Thu, 10 Oct 2019 08:10:12 -0400 Received: from localhost by e06smtp02.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Thu, 10 Oct 2019 13:10:08 +0100 Received: from d06av21.portsmouth.uk.ibm.com (d06av21.portsmouth.uk.ibm.com [9.149.105.232]) by b06avi18626390.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x9AC9ZHC26804526 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 10 Oct 2019 12:09:35 GMT Received: from d06av21.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 7D7925204F; Thu, 10 Oct 2019 12:10:05 +0000 (GMT) Received: from pratiks-thinkpad.ibmuc.com (unknown [9.199.37.96]) by d06av21.portsmouth.uk.ibm.com (Postfix) with ESMTP id A28BC52052; Thu, 10 Oct 2019 12:10:03 +0000 (GMT) From: Pratik Rajesh Sampat To: skiboot@lists.ozlabs.org, svaidy@linux.ibm.com, ego@linux.vnet.ibm.com, oohall@gmail.com, premjha2@in.ibm.com, akshay.adiga@linux.vnet.ibm.com, pratik.sampat@in.ibm.com Date: Thu, 10 Oct 2019 17:39:58 +0530 X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191010121000.23691-1-psampat@linux.ibm.com> References: <20191010121000.23691-1-psampat@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 x-cbid: 19101012-0008-0000-0000-00000320DA1D X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19101012-0009-0000-0000-00004A3FE2FB Message-Id: <20191010121000.23691-2-psampat@linux.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-10-10_04:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1908290000 definitions=main-1910100113 X-Mailman-Approved-At: Fri, 11 Oct 2019 10:47:36 +1100 Subject: [Skiboot] [PATCH Skiboot v1.2 1/3] Self Save: Fixed bugs pertaining to SPR self save. X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" From: Prem Shanker Jha Commit fixes some issues with code found during integration test - replacement of addi with xor instruction during self save API. - fixing instruction generation for MFMSR during self save - data struct updates in STOP API - error RC updates for hcode image build - HOMER parser updates. - removed self save support for URMOR and HRMOR - code changes for compilation with OPAL - populating CME Image header with unsecure HOMER address. Key_Cronus_Test=PM_REGRESS Change-Id: I7cedcc466267c4245255d8d75c01ed695e316720 Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/66580 Tested-by: FSP CI Jenkins Tested-by: HWSV CI Tested-by: PPE CI Tested-by: Jenkins Server Tested-by: Cronus HW CI Tested-by: Hostboot CI Reviewed-by: Gregory S. Still Reviewed-by: RAHUL BATRA Reviewed-by: Jennifer A. Stofer Reviewed-on: http://rchgit01.rchland.ibm.com/gerrit1/66587 Reviewed-by: Christian R. Geddes Signed-off-by: Akshay Adiga Signed-off-by: Pratik Rajesh Sampat --- libpore/p9_cpu_reg_restore_instruction.H | 1 + libpore/p9_stop_api.C | 72 ++++++++++++++++-------- libpore/p9_stop_api.H | 2 - libpore/p9_stop_data_struct.H | 4 +- libpore/p9_stop_util.H | 7 ++- 5 files changed, 56 insertions(+), 30 deletions(-) diff --git a/libpore/p9_cpu_reg_restore_instruction.H b/libpore/p9_cpu_reg_restore_instruction.H index dd4358a8..27603b23 100644 --- a/libpore/p9_cpu_reg_restore_instruction.H +++ b/libpore/p9_cpu_reg_restore_instruction.H @@ -68,6 +68,7 @@ enum MFSPR_CONST = 339, BLR_INST = 0x4e800020, MTSPR_BASE_OPCODE = 0x7c0003a6, + MFSPR_BASE_OPCODE = 0x7c0002a6, ATTN_OPCODE = 0x00000200, OPCODE_18 = 18, SELF_SAVE_FUNC_ADD = 0x2300, diff --git a/libpore/p9_stop_api.C b/libpore/p9_stop_api.C index 33aaf788..f41086b4 100644 --- a/libpore/p9_stop_api.C +++ b/libpore/p9_stop_api.C @@ -54,26 +54,26 @@ namespace stopImageSection const StopSprReg_t g_sprRegister[] = { - { P9_STOP_SPR_CIABR, true, 0 }, - { P9_STOP_SPR_DAWR, true, 1 }, - { P9_STOP_SPR_DAWRX, true, 2 }, - { P9_STOP_SPR_HSPRG0, true, 3 }, - { P9_STOP_SPR_LDBAR, true, 4, }, - { P9_STOP_SPR_LPCR, true, 5 }, - { P9_STOP_SPR_PSSCR, true, 6 }, - { P9_STOP_SPR_MSR, true, 7 }, - { P9_STOP_SPR_HRMOR, false, 20 }, - { P9_STOP_SPR_HID, false, 21 }, - { P9_STOP_SPR_HMEER, false, 22 }, - { P9_STOP_SPR_PMCR, false, 23 }, - { P9_STOP_SPR_PTCR, false, 24 }, - { P9_STOP_SPR_SMFCTRL, true, 28 }, - { P9_STOP_SPR_USPRG0, true, 29 }, - { P9_STOP_SPR_USPRG1, true, 30 }, - { P9_STOP_SPR_URMOR, false, 31 }, + { P9_STOP_SPR_CIABR, true, 0 }, + { P9_STOP_SPR_DAWR, true, 1 }, + { P9_STOP_SPR_DAWRX, true, 2 }, + { P9_STOP_SPR_HSPRG0, true, 3 }, + { P9_STOP_SPR_LDBAR, true, 4, }, + { P9_STOP_SPR_LPCR, true, 5 }, + { P9_STOP_SPR_PSSCR, true, 6 }, + { P9_STOP_SPR_MSR, true, 7 }, + { P9_STOP_SPR_HRMOR, false, 255 }, + { P9_STOP_SPR_HID, false, 21 }, + { P9_STOP_SPR_HMEER, false, 22 }, + { P9_STOP_SPR_PMCR, false, 23 }, + { P9_STOP_SPR_PTCR, false, 24 }, + { P9_STOP_SPR_SMFCTRL, true, 28 }, + { P9_STOP_SPR_USPRG0, true, 29 }, + { P9_STOP_SPR_USPRG1, true, 30 }, + { P9_STOP_SPR_URMOR, false, 255 }, }; -const uint32_t MAX_SPR_SUPPORTED = 17; +const uint32_t MAX_SPR_SUPPORTED = 17; const uint32_t LEGACY_CORE_SCOM_SUPPORTED = 15; const uint32_t LEGACY_QUAD_SCOM_SUPPORTED = 63; @@ -255,7 +255,7 @@ STATIC uint32_t getOriInstruction( const uint16_t i_Rs, const uint16_t i_Ra, */ STATIC uint32_t genKeyForSprLookup( const CpuReg_t i_regId ) { - return getOriInstruction( 0, 0, (uint16_t) i_regId ); + return getOriInstruction( 24, 0, (uint16_t) i_regId ); } //----------------------------------------------------------------------------- @@ -330,7 +330,7 @@ STATIC uint32_t getMtsprInstruction( const uint16_t i_Rs, const uint16_t i_Spr ) */ STATIC uint32_t getMfmsrInstruction( const uint16_t i_Rt ) { - uint32_t mfmsrInstOpcode = ((OPCODE_31 << 26) | (i_Rt << 21) | (MFMSR_CONST)); + uint32_t mfmsrInstOpcode = ((OPCODE_31 << 26) | (i_Rt << 21) | ((MFMSR_CONST)<< 1)); return SWIZZLE_4_BYTE(mfmsrInstOpcode); } @@ -361,8 +361,13 @@ STATIC uint32_t getRldicrInstruction( const uint16_t i_Ra, const uint16_t i_Rs, STATIC uint32_t getMfsprInstruction( const uint16_t i_Rt, const uint16_t i_sprNum ) { - uint32_t mfsprInstOpcode = 0; - mfsprInstOpcode = (( OPCODE_31 << 26 ) | ( i_Rt << 21 ) | ( i_sprNum << 11 ) | ( MFSPR_CONST << 1 )); + uint32_t mfsprInstOpcode = 0; + uint32_t temp = (( i_sprNum & 0x03FF ) << 11); + mfsprInstOpcode = (uint8_t)i_Rt << 21; + mfsprInstOpcode |= (( temp & 0x0000F800 ) << 5); + mfsprInstOpcode |= (( temp & 0x001F0000 ) >> 5); + mfsprInstOpcode |= MFSPR_BASE_OPCODE; + return SWIZZLE_4_BYTE(mfsprInstOpcode); } @@ -615,14 +620,14 @@ STATIC StopReturnCode_t getSprRegIndexAdjustment( const uint32_t i_saveMaskPos, do { - if( (( i_saveMaskPos >= SPR_BIT_POS_8 ) && ( i_saveMaskPos <= SPR_BIT_POS_19 )) || + if( (( i_saveMaskPos >= SPR_BIT_POS_8 ) && ( i_saveMaskPos <= SPR_BIT_POS_20 )) || (( i_saveMaskPos >= SPR_BIT_POS_25 ) && ( i_saveMaskPos <= SPR_BIT_POS_27 )) ) { l_rc = STOP_SAVE_SPR_BIT_POS_RESERVE; break; } - if( (i_saveMaskPos > SPR_BIT_POS_19) && (i_saveMaskPos < SPR_BIT_POS_25 ) ) + if( (i_saveMaskPos > SPR_BIT_POS_20) && (i_saveMaskPos < SPR_BIT_POS_25) ) { *i_sprAdjIndex = 12; } @@ -1411,6 +1416,7 @@ StopReturnCode_t p9_stop_save_cpureg_control( void* i_pImage, uint32_t* l_pRestoreStart = NULL; uint32_t* l_pSprSave = NULL; void* l_pTempLoc = NULL; + uint32_t * l_pTempWord = NULL; SmfHomerSection_t* l_pHomer = NULL; uint8_t l_selfRestVer = 0; @@ -1440,6 +1446,11 @@ StopReturnCode_t p9_stop_save_cpureg_control( void* i_pImage, { l_sprPos = g_sprRegister[l_sprIndex].iv_saveMaskPos; + if( l_sprPos > MAX_SPR_BIT_POS ) + { + continue; + } + //Check if a given SPR needs to be self-saved each time on STOP entry if( i_saveRegVector & ( TEST_BIT_PATTERN >> l_sprPos ) ) @@ -1493,6 +1504,19 @@ StopReturnCode_t p9_stop_save_cpureg_control( void* i_pImage, //update specific instructions of self save region to enable saving for SPR l_rc = updateSelfSaveEntry( l_pSprSave, g_sprRegister[l_sprIndex].iv_sprId ); + if( l_rc ) + { + MY_ERR( "Failed to update self save instructions for 0x%08x", + (uint32_t) g_sprRegister[l_sprIndex].iv_sprId ); + } + + if( l_pTempLoc ) + { + l_pTempWord = (uint32_t *)l_pTempLoc; + l_pTempWord++; + *l_pTempWord = getXorInstruction( 0, 0, 0 ); + } + }// end if( i_saveRegVector..) }// end for } diff --git a/libpore/p9_stop_api.H b/libpore/p9_stop_api.H index 17caedb3..ef0d9d1e 100644 --- a/libpore/p9_stop_api.H +++ b/libpore/p9_stop_api.H @@ -148,7 +148,6 @@ typedef enum BIT_POS_LPCR = 5, BIT_POS_PSSCR = 6, BIT_POS_MSR = 7, - BIT_POS_HRMOR = 20, BIT_POS_HID = 21, BIT_POS_HMEER = 22, BIT_POS_PMCR = 23, @@ -156,7 +155,6 @@ typedef enum BIT_POS_SMFCTRL = 28, BIT_POS_USPRG0 = 29, BIT_POS_USPRG1 = 30, - BIT_POS_URMOR = 31, } SprBitPositionList_t; diff --git a/libpore/p9_stop_data_struct.H b/libpore/p9_stop_data_struct.H index 1e9721e0..4e73aab5 100644 --- a/libpore/p9_stop_data_struct.H +++ b/libpore/p9_stop_data_struct.H @@ -67,9 +67,9 @@ enum SIZE_PER_SPR_RESTORE_INST = ((4 * sizeof(uint8_t)) / sizeof(uint32_t)), MAX_THREAD_LEVEL_SPRS = 11, MAX_CORE_LEVEL_SPRS = 6, - MAX_SPR_BIT_POS = 31, + MAX_SPR_BIT_POS = 30, SPR_BIT_POS_8 = 8, - SPR_BIT_POS_19 = 19, + SPR_BIT_POS_20 = 20, SPR_BIT_POS_25 = 25, SPR_BIT_POS_27 = 27, }; diff --git a/libpore/p9_stop_util.H b/libpore/p9_stop_util.H index 3266fdef..79b4e959 100644 --- a/libpore/p9_stop_util.H +++ b/libpore/p9_stop_util.H @@ -5,7 +5,7 @@ /* */ /* OpenPOWER HostBoot Project */ /* */ -/* Contributors Listed Below - COPYRIGHT 2016,2017 */ +/* Contributors Listed Below - COPYRIGHT 2016,2018 */ /* [+] International Business Machines Corp. */ /* */ /* */ @@ -95,7 +95,10 @@ typedef struct uint64_t cpmrMagicWord; uint32_t buildDate; uint32_t version; - uint8_t reserve1[7]; + uint8_t reserve1[4]; + uint8_t selfRestoreVer; + uint8_t stopApiVer; + uint8_t urmorFix; uint8_t fusedModeStatus; uint32_t cmeImgOffset; uint32_t cmeImgLength; From patchwork Thu Oct 10 12:09:59 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Pratik R. Sampat" X-Patchwork-Id: 1174832 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 46q76y5bVJz9sN1 for ; Fri, 11 Oct 2019 10:47:38 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 46q76y4VmtzDqRk for ; Fri, 11 Oct 2019 10:47:38 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=linux.ibm.com (client-ip=148.163.156.1; helo=mx0a-001b2d01.pphosted.com; envelope-from=psampat@linux.ibm.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from mx0a-001b2d01.pphosted.com (mx0a-001b2d01.pphosted.com [148.163.156.1]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 46pqfN1F2xzDr4N for ; Thu, 10 Oct 2019 23:10:16 +1100 (AEDT) Received: from pps.filterd (m0098409.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x9AC7q7n025298 for ; Thu, 10 Oct 2019 08:10:14 -0400 Received: from e06smtp02.uk.ibm.com (e06smtp02.uk.ibm.com [195.75.94.98]) by mx0a-001b2d01.pphosted.com with ESMTP id 2vj290mesc-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Thu, 10 Oct 2019 08:10:14 -0400 Received: from localhost by e06smtp02.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Thu, 10 Oct 2019 13:10:10 +0100 Received: from d06av21.portsmouth.uk.ibm.com (d06av21.portsmouth.uk.ibm.com [9.149.105.232]) by b06cxnps4076.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x9ACA70v49283142 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 10 Oct 2019 12:10:07 GMT Received: from d06av21.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id C92EC52067; Thu, 10 Oct 2019 12:10:07 +0000 (GMT) Received: from pratiks-thinkpad.ibmuc.com (unknown [9.199.37.96]) by d06av21.portsmouth.uk.ibm.com (Postfix) with ESMTP id E092752052; Thu, 10 Oct 2019 12:10:05 +0000 (GMT) From: Pratik Rajesh Sampat To: skiboot@lists.ozlabs.org, svaidy@linux.ibm.com, ego@linux.vnet.ibm.com, oohall@gmail.com, premjha2@in.ibm.com, akshay.adiga@linux.vnet.ibm.com, pratik.sampat@in.ibm.com Date: Thu, 10 Oct 2019 17:39:59 +0530 X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191010121000.23691-1-psampat@linux.ibm.com> References: <20191010121000.23691-1-psampat@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 x-cbid: 19101012-0008-0000-0000-00000320DA1F X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19101012-0009-0000-0000-00004A3FE2FD Message-Id: <20191010121000.23691-3-psampat@linux.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-10-10_04:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1908290000 definitions=main-1910100113 X-Mailman-Approved-At: Fri, 11 Oct 2019 10:47:36 +1100 Subject: [Skiboot] [PATCH Skiboot v1.2 2/3] Self save API integration X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" The commit makes the self save API available outside the firmware by defining an OPAL wrapper. This wrapper has a similar interface to that of self restore and expects the cpu pir, SPR number, minus the value of that SPR to be passed in its paramters and returns OPAL_SUCCESS on success. Signed-off-by: Pratik Rajesh Sampat --- hw/slw.c | 88 +++++++++++++++++++++++++++++++++++++++++++ include/opal-api.h | 3 +- include/p9_stop_api.H | 16 ++++++++ include/skiboot.h | 3 ++ libpore/p9_stop_api.C | 2 +- 5 files changed, 110 insertions(+), 2 deletions(-) diff --git a/hw/slw.c b/hw/slw.c index bb88f0f1..b79aaab3 100644 --- a/hw/slw.c +++ b/hw/slw.c @@ -36,6 +36,42 @@ static bool slw_current_le = false; enum wakeup_engine_states wakeup_engine_state = WAKEUP_ENGINE_NOT_PRESENT; bool has_deep_states = false; +/** + * The struct and SPR list is partially consistent with libpore/p9_stop_api.c + */ +/** + * @brief summarizes attributes associated with a SPR register. + */ +typedef struct +{ + uint32_t iv_sprId; + bool iv_isThreadScope; + uint32_t iv_saveMaskPos; + +} StopSprReg_t; + +/** + * @brief a true in the table below means register is of scope thread + * whereas a false meanse register is of scope core. + * The number is the bit position on a uint32_t mask + */ + +static const StopSprReg_t g_sprRegister[] = +{ + { P9_STOP_SPR_DAWR, true, 1 }, + { P9_STOP_SPR_HSPRG0, true, 3 }, + { P9_STOP_SPR_LDBAR, true, 4, }, + { P9_STOP_SPR_LPCR, true, 5 }, + { P9_STOP_SPR_PSSCR, true, 6 }, + { P9_STOP_SPR_MSR, true, 7 }, + { P9_STOP_SPR_HRMOR, false, 255 }, + { P9_STOP_SPR_HID, false, 21 }, + { P9_STOP_SPR_HMEER, false, 22 }, + { P9_STOP_SPR_PMCR, false, 23 }, +}; + +static const uint32_t MAX_SPR_SUPPORTED = ARRAY_SIZE(g_sprRegister); + DEFINE_LOG_ENTRY(OPAL_RC_SLW_INIT, OPAL_PLATFORM_ERR_EVT, OPAL_SLW, OPAL_PLATFORM_FIRMWARE, OPAL_PREDICTIVE_ERR_GENERAL, OPAL_NA); @@ -1452,6 +1488,58 @@ int64_t opal_slw_set_reg(uint64_t cpu_pir, uint64_t sprn, uint64_t val) opal_call(OPAL_SLW_SET_REG, opal_slw_set_reg, 3); +int64_t opal_slw_self_save_reg(uint64_t cpu_pir, uint64_t sprn) +{ + struct cpu_thread * c = find_cpu_by_pir(cpu_pir); + struct proc_chip * chip; + int rc; + int index; + uint32_t save_reg_vector = 0; + + if (!c) { + prerror("SLW: Unknown thread with pir %x\n", (u32) cpu_pir); + return OPAL_PARAMETER; + } + + chip = get_chip(c->chip_id); + if (!chip) { + prerror("SLW: Unknown chip for thread with pir %x\n", + (u32) cpu_pir); + return OPAL_PARAMETER; + } + if (proc_gen == proc_gen_p9 && has_deep_states) { + if (wakeup_engine_state != WAKEUP_ENGINE_PRESENT) { + log_simple_error(&e_info(OPAL_RC_SLW_REG), + "SLW: wakeup_engine in bad state=%d chip=%x\n", + wakeup_engine_state, chip->id); + return OPAL_INTERNAL_ERROR; + } + for (index = 0; index < MAX_SPR_SUPPORTED; ++index) { + if (sprn == (CpuReg_t) g_sprRegister[index].iv_sprId) { + save_reg_vector = PPC_BIT32( + g_sprRegister[index].iv_saveMaskPos); + break; + } + } + if (save_reg_vector == 0) + return OPAL_INTERNAL_ERROR; + rc = p9_stop_save_cpureg_control((void *) chip->homer_base, + cpu_pir, save_reg_vector); + + if (rc) { + log_simple_error(&e_info(OPAL_RC_SLW_REG), + "SLW: Failed to save vector %x for CPU %x\n", + save_reg_vector, c->pir); + return OPAL_INTERNAL_ERROR; + } + return OPAL_SUCCESS; + } + prerror("SLW: Does not support deep states\n"); + return OPAL_UNSUPPORTED; +} + +opal_call(OPAL_SLW_SELF_SAVE_REG, opal_slw_self_save_reg, 2); + void slw_init(void) { struct proc_chip *chip; diff --git a/include/opal-api.h b/include/opal-api.h index 782666dd..53ce23e0 100644 --- a/include/opal-api.h +++ b/include/opal-api.h @@ -219,7 +219,8 @@ #define OPAL_XIVE_GET_VP_STATE 170 /* Get NVT state */ #define OPAL_NPU_MEM_ALLOC 171 #define OPAL_NPU_MEM_RELEASE 172 -#define OPAL_LAST 172 +#define OPAL_SLW_SELF_SAVE_REG 173 +#define OPAL_LAST 173 #define QUIESCE_HOLD 1 /* Spin all calls at entry */ #define QUIESCE_REJECT 2 /* Fail all calls with OPAL_BUSY */ diff --git a/include/p9_stop_api.H b/include/p9_stop_api.H index 79abd000..e9962c37 100644 --- a/include/p9_stop_api.H +++ b/include/p9_stop_api.H @@ -34,6 +34,8 @@ /// /// @file p9_stop_api.H /// @brief describes STOP API which create/manipulate STOP image. +/// This header need not be consistent, however is a subset of the +/// libpore/p9_stop_api.H counterpart /// // *HWP HW Owner : Greg Still // *HWP FW Owner : Prem Shanker Jha @@ -155,6 +157,20 @@ StopReturnCode_t p9_stop_save_scom( void* const i_pImage, const ScomOperation_t i_operation, const ScomSection_t i_section ); +/** + * @brief Facilitates self save and restore of a list of SPRs of a thread. + * @param[in] i_pImage points to the start of HOMER image of P9 chip. + * @param[in] i_pir PIR associated with thread + * @param[in] i_saveRegVector bit vector representing SPRs that needs to be restored. + * @return STOP_SAVE_SUCCESS if API succeeds, error code otherwise. + * @note SPR save vector is a bit vector. For each SPR supported, + * there is an associated bit position in the bit vector.Refer + * to definition of SprBitPositionList_t to determine bit position + * associated with a particular SPR. + */ +StopReturnCode_t +p9_stop_save_cpureg_control( void* i_pImage, const uint64_t i_pir, + const uint32_t i_saveRegVector ); #ifdef __cplusplus } // extern "C" }; // namespace stopImageSection ends diff --git a/include/skiboot.h b/include/skiboot.h index 6cac1cfd..1aa8bf7c 100644 --- a/include/skiboot.h +++ b/include/skiboot.h @@ -299,6 +299,9 @@ extern void xive_late_init(void); /* SLW reinit function for switching core settings */ extern int64_t slw_reinit(uint64_t flags); +/* Self save SPR before entering the stop state */ +extern int64_t opal_slw_self_save_reg(uint64_t cpu_pir, uint64_t sprn); + /* Patch SPR in SLW image */ extern int64_t opal_slw_set_reg(uint64_t cpu_pir, uint64_t sprn, uint64_t val); diff --git a/libpore/p9_stop_api.C b/libpore/p9_stop_api.C index f41086b4..d231d1eb 100644 --- a/libpore/p9_stop_api.C +++ b/libpore/p9_stop_api.C @@ -1401,7 +1401,7 @@ STATIC StopReturnCode_t updateSelfSaveEntry( uint32_t* i_pSaveReg, uint16_t i_sp //----------------------------------------------------------------------------- -StopReturnCode_t p9_stop_save_cpureg_control( void* i_pImage, +StopReturnCode_t p9_stop_save_cpureg_control( void* const i_pImage, const uint64_t i_pir, const uint32_t i_saveRegVector ) { From patchwork Thu Oct 10 12:10:00 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Pratik R. Sampat" X-Patchwork-Id: 1174835 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 46q77p3ffGz9sN1 for ; Fri, 11 Oct 2019 10:48:22 +1100 (AEDT) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from bilbo.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 46q77p2hsSzDqQc for ; Fri, 11 Oct 2019 10:48:22 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: lists.ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=linux.ibm.com (client-ip=148.163.158.5; helo=mx0a-001b2d01.pphosted.com; envelope-from=psampat@linux.ibm.com; receiver=) Authentication-Results: lists.ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Received: from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 46pqfQ4lJrzDr4N for ; Thu, 10 Oct 2019 23:10:19 +1100 (AEDT) Received: from pps.filterd (m0098419.ppops.net [127.0.0.1]) by mx0b-001b2d01.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x9AC7xdt108088 for ; Thu, 10 Oct 2019 08:10:16 -0400 Received: from e06smtp07.uk.ibm.com (e06smtp07.uk.ibm.com [195.75.94.103]) by mx0b-001b2d01.pphosted.com with ESMTP id 2vj1nawrxy-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Thu, 10 Oct 2019 08:10:16 -0400 Received: from localhost by e06smtp07.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Thu, 10 Oct 2019 13:10:13 +0100 Received: from d06av21.portsmouth.uk.ibm.com (d06av21.portsmouth.uk.ibm.com [9.149.105.232]) by b06cxnps3075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x9ACAARQ62586960 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Thu, 10 Oct 2019 12:10:10 GMT Received: from d06av21.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 0F97D52050; Thu, 10 Oct 2019 12:10:10 +0000 (GMT) Received: from pratiks-thinkpad.ibmuc.com (unknown [9.199.37.96]) by d06av21.portsmouth.uk.ibm.com (Postfix) with ESMTP id 29CF652054; Thu, 10 Oct 2019 12:10:07 +0000 (GMT) From: Pratik Rajesh Sampat To: skiboot@lists.ozlabs.org, svaidy@linux.ibm.com, ego@linux.vnet.ibm.com, oohall@gmail.com, premjha2@in.ibm.com, akshay.adiga@linux.vnet.ibm.com, pratik.sampat@in.ibm.com Date: Thu, 10 Oct 2019 17:40:00 +0530 X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191010121000.23691-1-psampat@linux.ibm.com> References: <20191010121000.23691-1-psampat@linux.ibm.com> MIME-Version: 1.0 X-TM-AS-GCONF: 00 x-cbid: 19101012-0028-0000-0000-000003A8D8BF X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19101012-0029-0000-0000-0000246AE118 Message-Id: <20191010121000.23691-4-psampat@linux.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2019-10-10_04:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 impostorscore=0 mlxlogscore=999 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1908290000 definitions=main-1910100113 X-Mailman-Approved-At: Fri, 11 Oct 2019 10:47:36 +1100 Subject: [Skiboot] [PATCH Skiboot v1.2 3/3] Advertise the self-save and self-restore attributes in the device tree X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" Support for self save and self restore interface is advertised in the device tree, along with the list of SPRs it supports for each. The Special Purpose Register identification is encoded in a 2048 bitmask structure, where each bit signifies the identification key of that SPR which is consistent with that of the Linux kernel for that register. Signed-off-by: Pratik Rajesh Sampat --- hw/slw.c | 72 +++++++++++++++++++++++++++++++++++++++++++++++ include/skiboot.h | 1 + 2 files changed, 73 insertions(+) diff --git a/hw/slw.c b/hw/slw.c index b79aaab3..d9c2d091 100644 --- a/hw/slw.c +++ b/hw/slw.c @@ -22,6 +22,7 @@ #include #include #include +#include #include #include @@ -753,6 +754,70 @@ static void slw_late_init_p9(struct proc_chip *chip) } } +/* Add device tree properties to determine self-save | restore */ +void add_cpu_self_save_properties(struct dt_node *power_mgt) +{ + int i; + struct dt_node *self_restore, *self_save; + bitmap_t *self_restore_map, *self_save_map; + /* 32 times 64 bits needed to store a 2048 bits bitmask*/ + const int bits_nr = 32; + + const uint64_t self_restore_regs[] = { + 0x130, // HSPRG0 + 0x13E, // LPCR + 0x151, // HMEER + 0x3F0, // HID0 + 0x3F1, // HID1 + 0x3F4, // HID4 + 0x3F6, // HID5 + 0x7D0, // MSR + 0x357 // PSCCR + }; + + const uint64_t self_save_regs[] = { + 0x130, // HSPRG0 + 0x13E, // LPCR + 0x151, // HMEER + 0x7D0, // MSR + 0x357 // PSCCR + }; + const int self_save_regs_nr = ARRAY_SIZE(self_save_regs); + const int self_restore_regs_nr = ARRAY_SIZE(self_restore_regs); + + self_save_map = zalloc(BITMAP_BYTES(0x800)); + self_restore_map = zalloc(BITMAP_BYTES(0x800)); + + for (i = 0; i < self_save_regs_nr; i++) + bitmap_set_bit(*self_save_map, self_save_regs[i]); + + for (i = 0; i < self_restore_regs_nr; i++) + bitmap_set_bit(*self_restore_map, self_restore_regs[i]); + + self_restore = dt_new(power_mgt, "self-restore"); + if (!self_restore) { + prerror("OCC: Failed to create self restore node"); + return; + } + dt_add_property_cells(self_restore, "active", 0x1); + + dt_add_property(self_restore, "sprn-bitmask", *self_restore_map, + bits_nr * sizeof(uint64_t)); + + self_save = dt_new(power_mgt, "self-save"); + if (!self_save) { + prerror("OCC: Failed to create self save node"); + return; + } + if (proc_gen == proc_gen_p9) { + dt_add_property_cells(self_save, "active", 0x1); + + dt_add_property(self_save, "sprn-bitmask", *self_save_map, + bits_nr * sizeof(uint64_t)); + } else + dt_add_property_cells(self_save, "active", 0x0); +} + /* Add device tree properties to describe idle states */ void add_cpu_idle_state_properties(void) { @@ -1543,6 +1608,7 @@ opal_call(OPAL_SLW_SELF_SAVE_REG, opal_slw_self_save_reg, 2); void slw_init(void) { struct proc_chip *chip; + struct dt_node *power_mgt; if (proc_chip_quirks & QUIRK_MAMBO_CALLOUTS) { wakeup_engine_state = WAKEUP_ENGINE_NOT_PRESENT; @@ -1568,4 +1634,10 @@ void slw_init(void) } } add_cpu_idle_state_properties(); + power_mgt = dt_find_by_path(dt_root, "/ibm,opal/power-mgt"); + if (!power_mgt) { + prerror("OCC: dt node /ibm,opal/power-mgt not found\n"); + return; + } + add_cpu_self_save_properties(power_mgt); } diff --git a/include/skiboot.h b/include/skiboot.h index 1aa8bf7c..e8f0f755 100644 --- a/include/skiboot.h +++ b/include/skiboot.h @@ -202,6 +202,7 @@ extern void early_uart_init(void); extern void homer_init(void); extern void slw_init(void); extern void add_cpu_idle_state_properties(void); +extern void add_cpu_self_save_properties(struct dt_node *power_mgt); extern void lpc_rtc_init(void); /* flash support */