From patchwork Thu Oct 10 15:36:29 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Oleg Endo X-Patchwork-Id: 1174666 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-510650-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=t-online.de Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="ShNX8fHR"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 46pwFB6T7yz9sPW for ; Fri, 11 Oct 2019 02:36:48 +1100 (AEDT) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:subject:from:to:date:content-type:mime-version; q= dns; s=default; b=wsxI5KyIDHL8m9845MS7nXPWnzd+xQ+Pl2SKOY6P9zSWYe IGY3CnIXR4wiK8UKn/enapzoMd7mn7TndrtwfOQ/DmWHF0f4uGGxllfbCanQCstj dGbmRj94HCv1tvZjp2VwjaaUxUC/Xl+YTcmFPFhCxcKDT1+bv2PvuZGFn3GnE= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :message-id:subject:from:to:date:content-type:mime-version; s= default; bh=Wp3Ya+TrGkaC64yObveVzp86Brw=; b=ShNX8fHRcREQ1sjGDMyD IZ8/b9JvOnWDm5zmHn57n5KicalDYdsWLcA4cv2kErcpygBGFHAVwOGkQ0If46lQ 2joOyCTu9HqB3izRoZeYwI6Rh0xDp0FBPTLatJGMwRFee9aN4u2IpsHwQLDgKapL M/kFpNeJEaQGWrK4clNFizU= Received: (qmail 79936 invoked by alias); 10 Oct 2019 15:36:41 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 79928 invoked by uid 89); 10 Oct 2019 15:36:41 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-7.3 required=5.0 tests=AWL, BAYES_00, FREEMAIL_FROM, GIT_PATCH_2, GIT_PATCH_3, KAM_ASCII_DIVIDERS, KAM_NUMSUBJECT, RCVD_IN_DNSWL_NONE, SPOOFED_FREEMAIL autolearn=ham version=3.3.1 spammy=r276809, H*r:encrypted, H*r:sk:mailout, H*RU:sk:mailout X-HELO: mailout04.t-online.de Received: from mailout04.t-online.de (HELO mailout04.t-online.de) (194.25.134.18) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 10 Oct 2019 15:36:39 +0000 Received: from fwd19.aul.t-online.de (fwd19.aul.t-online.de [172.20.27.65]) by mailout04.t-online.de (Postfix) with SMTP id 51B9941E31DA for ; Thu, 10 Oct 2019 17:36:36 +0200 (CEST) Received: from yam-desktop (VTdicQZJohhNDVs3BsZYGob3+JHU01Muockpk06LlqXAm-C90vSoMcE6LbsWJRzwCT@[163.58.16.102]) by fwd19.t-online.de with (TLSv1.2:ECDHE-RSA-AES256-GCM-SHA384 encrypted) esmtp id 1iIaUT-4d4mcy0; Thu, 10 Oct 2019 17:36:33 +0200 Message-ID: Subject: [SH][committed] Fix PR 88630 From: Oleg Endo To: gcc-patches Date: Fri, 11 Oct 2019 00:36:29 +0900 Mime-Version: 1.0 X-IsSubscribed: yes Hi, When we did the refactoring of SH's FPSCR handling back in GCC 5, we missed one thing regarding ST-40, it seems. The attached patch fixes the issue as confirmed on the real hardware. Also tested on sh-sim with make -k check RUNTESTFLAGS="--target_board=sh-sim\{-m2/-ml,-m2/-mb,- m2a/-mb,-m4/-ml,-m4/-mb}" Committed to trunk, GCC 9, GCC 8 as r276809, r276825, r276837. Cheers, Oleg gcc/ChangeLog: PR target/88630 * config/sh/sh.h (TARGET_FPU_SH4_300): New macro. * config/sh/sh.c (sh_option_override): Enable fsca and fsrra insns also for TARGET_FPU_SH4_300. (sh_emit_mode_set): Check for TARGET_FPU_SH4_300 instead of TARGET_SH4_300. * config/sh/sh.md (toggle_pr): Add TARGET_FPU_SH4_300 condition. (negsf2): Expand to either negsf2_fpscr or negsf2_no_fpscr. (*negsf2_i): Split into ... (negsf2_fpscr, negsf2_no_fpscr): ... these new patterns. (abssf2): Expand to either abssf2_fpsc or abssf2_no_fpsc. (**abssf2_i): Split into ... (abssf2_fpscr, abssf2_no_fpscr): ... these new patterns. (negdf2): Expand to either negdf2_fpscr or negdf2_no_fpscr. (*negdf2_i): Split into ... (negdf2_fpscr, negdf2_no_fpscr): ... these new patterns. (absdf2): Expand to either absdf2_fpscr or absdf2_no_fpsc. (**abssf2_i): Split into ... (absdf2_fpscr, absdf2_no_fpscr): ... these new patterns. Index: gcc/config/sh/sh.c =================================================================== --- gcc/config/sh/sh.c (revision 276411) +++ gcc/config/sh/sh.c (working copy) @@ -958,11 +958,13 @@ if (flag_unsafe_math_optimizations) { /* Enable fsca insn for SH4A if not otherwise specified by the user. */ - if (global_options_set.x_TARGET_FSCA == 0 && TARGET_SH4A_FP) + if (global_options_set.x_TARGET_FSCA == 0 + && (TARGET_SH4A_FP || TARGET_FPU_SH4_300)) TARGET_FSCA = 1; /* Enable fsrra insn for SH4A if not otherwise specified by the user. */ - if (global_options_set.x_TARGET_FSRRA == 0 && TARGET_SH4A_FP) + if (global_options_set.x_TARGET_FSRRA == 0 + && (TARGET_SH4A_FP || TARGET_FPU_SH4_300)) TARGET_FSRRA = 1; } @@ -12490,7 +12492,7 @@ sh_emit_mode_set (int entity ATTRIBUTE_UNUSED, int mode, int prev_mode, HARD_REG_SET regs_live ATTRIBUTE_UNUSED) { - if ((TARGET_SH4A_FP || TARGET_SH4_300) + if ((TARGET_SH4A_FP || TARGET_FPU_SH4_300) && prev_mode != FP_MODE_NONE && prev_mode != mode) { emit_insn (gen_toggle_pr ()); Index: gcc/config/sh/sh.h =================================================================== --- gcc/config/sh/sh.h (revision 276410) +++ gcc/config/sh/sh.h (working copy) @@ -69,6 +69,8 @@ FPU is disabled (which makes it compatible with SH4al-dsp). */ #define TARGET_SH4A_FP (TARGET_SH4A && TARGET_FPU_ANY) +/* True if the FPU is a SH4-300 variant. */ +#define TARGET_FPU_SH4_300 (TARGET_FPU_ANY && TARGET_SH4_300) /* This is not used by the SH2E calling convention */ #define TARGET_VARARGS_PRETEND_ARGS(FUN_DECL) \ Index: gcc/config/sh/sh.md =================================================================== --- gcc/config/sh/sh.md (revision 276410) +++ gcc/config/sh/sh.md (working copy) @@ -9163,7 +9163,7 @@ (xor:SI (reg:SI FPSCR_REG) (const_int FPSCR_PR))) (set (reg:SI FPSCR_MODES_REG) (unspec_volatile:SI [(const_int 0)] UNSPECV_FPSCR_MODES))] - "TARGET_SH4A_FP" + "TARGET_SH4A_FP || TARGET_FPU_SH4_300" "fpchg" [(set_attr "type" "fpscr_toggle")]) @@ -9391,15 +9391,31 @@ (define_expand "negsf2" [(set (match_operand:SF 0 "fp_arith_reg_operand") (neg:SF (match_operand:SF 1 "fp_arith_reg_operand")))] - "TARGET_SH2E") + "TARGET_FPU_ANY" +{ + if (TARGET_FPU_SH4_300) + emit_insn (gen_negsf2_fpscr (operands[0], operands[1])); + else + emit_insn (gen_negsf2_no_fpscr (operands[0], operands[1])); + DONE; +}) -(define_insn "*negsf2_i" +(define_insn "negsf2_no_fpscr" [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f") (neg:SF (match_operand:SF 1 "fp_arith_reg_operand" "0")))] - "TARGET_SH2E" + "TARGET_FPU_ANY && !TARGET_FPU_SH4_300" "fneg %0" [(set_attr "type" "fmove")]) +(define_insn "negsf2_fpscr" + [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f") + (neg:SF (match_operand:SF 1 "fp_arith_reg_operand" "0"))) + (use (reg:SI FPSCR_MODES_REG))] + "TARGET_FPU_SH4_300" + "fneg %0" + [(set_attr "type" "fmove") + (set_attr "fp_mode" "single")]) + (define_expand "sqrtsf2" [(set (match_operand:SF 0 "fp_arith_reg_operand" "") (sqrt:SF (match_operand:SF 1 "fp_arith_reg_operand" "")))] @@ -9489,15 +9505,31 @@ (define_expand "abssf2" [(set (match_operand:SF 0 "fp_arith_reg_operand") (abs:SF (match_operand:SF 1 "fp_arith_reg_operand")))] - "TARGET_SH2E") + "TARGET_FPU_ANY" +{ + if (TARGET_FPU_SH4_300) + emit_insn (gen_abssf2_fpscr (operands[0], operands[1])); + else + emit_insn (gen_abssf2_no_fpscr (operands[0], operands[1])); + DONE; +}) -(define_insn "*abssf2_i" +(define_insn "abssf2_no_fpscr" [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f") (abs:SF (match_operand:SF 1 "fp_arith_reg_operand" "0")))] - "TARGET_SH2E" + "TARGET_FPU_ANY && !TARGET_FPU_SH4_300" "fabs %0" [(set_attr "type" "fmove")]) +(define_insn "abssf2_fpscr" + [(set (match_operand:SF 0 "fp_arith_reg_operand" "=f") + (abs:SF (match_operand:SF 1 "fp_arith_reg_operand" "0"))) + (use (reg:SI FPSCR_MODES_REG))] + "TARGET_FPU_SH4_300" + "fabs %0" + [(set_attr "type" "fmove") + (set_attr "fp_mode" "single")]) + (define_expand "adddf3" [(set (match_operand:DF 0 "fp_arith_reg_operand" "") (plus:DF (match_operand:DF 1 "fp_arith_reg_operand" "") @@ -9673,12 +9705,28 @@ (define_expand "negdf2" [(set (match_operand:DF 0 "fp_arith_reg_operand") (neg:DF (match_operand:DF 1 "fp_arith_reg_operand")))] - "TARGET_FPU_DOUBLE") + "TARGET_FPU_DOUBLE" +{ + if (TARGET_FPU_SH4_300) + emit_insn (gen_negdf2_fpscr (operands[0], operands[1])); + else + emit_insn (gen_negdf2_no_fpscr (operands[0], operands[1])); + DONE; +}) -(define_insn "*negdf2_i" +(define_insn "negdf2_fpscr" [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f") + (neg:DF (match_operand:DF 1 "fp_arith_reg_operand" "0"))) + (use (reg:SI FPSCR_MODES_REG))] + "TARGET_FPU_SH4_300" + "fneg %0" + [(set_attr "type" "fmove") + (set_attr "fp_mode" "double")]) + +(define_insn "negdf2_no_fpscr" + [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f") (neg:DF (match_operand:DF 1 "fp_arith_reg_operand" "0")))] - "TARGET_FPU_DOUBLE" + "TARGET_FPU_DOUBLE && !TARGET_FPU_SH4_300" "fneg %0" [(set_attr "type" "fmove")]) @@ -9704,15 +9752,31 @@ (define_expand "absdf2" [(set (match_operand:DF 0 "fp_arith_reg_operand") (abs:DF (match_operand:DF 1 "fp_arith_reg_operand")))] - "TARGET_FPU_DOUBLE") + "TARGET_FPU_DOUBLE" +{ + if (TARGET_FPU_SH4_300) + emit_insn (gen_absdf2_fpscr (operands[0], operands[1])); + else + emit_insn (gen_absdf2_no_fpscr (operands[0], operands[1])); + DONE; +}) -(define_insn "*absdf2_i" +(define_insn "absdf2_no_fpscr" [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f") (abs:DF (match_operand:DF 1 "fp_arith_reg_operand" "0")))] - "TARGET_FPU_DOUBLE" + "TARGET_FPU_DOUBLE && !TARGET_FPU_SH4_300" "fabs %0" [(set_attr "type" "fmove")]) +(define_insn "absdf2_fpscr" + [(set (match_operand:DF 0 "fp_arith_reg_operand" "=f") + (abs:DF (match_operand:DF 1 "fp_arith_reg_operand" "0"))) + (use (reg:SI FPSCR_MODES_REG))] + "TARGET_FPU_SH4_300" + "fabs %0" + [(set_attr "type" "fmove") + (set_attr "fp_mode" "double")]) + (define_expand "extendsfdf2" [(set (match_operand:DF 0 "fp_arith_reg_operand" "") (float_extend:DF (match_operand:SF 1 "fpul_operand" "")))]