From patchwork Tue Nov 14 17:28:42 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Reza Arbab X-Patchwork-Id: 837952 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.2 with cipher ADH-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 3ybvcz74MLz9s3w for ; Wed, 15 Nov 2017 04:29:07 +1100 (AEDT) Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) by lists.ozlabs.org (Postfix) with ESMTP id 3ybvcz4b5MzDqky for ; Wed, 15 Nov 2017 04:29:07 +1100 (AEDT) X-Original-To: skiboot@lists.ozlabs.org Delivered-To: skiboot@lists.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=linux.vnet.ibm.com (client-ip=148.163.158.5; helo=mx0a-001b2d01.pphosted.com; envelope-from=arbab@linux.vnet.ibm.com; receiver=) Received: from mx0a-001b2d01.pphosted.com (mx0b-001b2d01.pphosted.com [148.163.158.5]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by lists.ozlabs.org (Postfix) with ESMTPS id 3ybvcj1rh9zDqkr for ; Wed, 15 Nov 2017 04:28:52 +1100 (AEDT) Received: from pps.filterd (m0098421.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id vAEHOC5q126301 for ; Tue, 14 Nov 2017 12:28:49 -0500 Received: from e17.ny.us.ibm.com (e17.ny.us.ibm.com [129.33.205.207]) by mx0a-001b2d01.pphosted.com with ESMTP id 2e84ncgv4j-1 (version=TLSv1.2 cipher=AES256-SHA bits=256 verify=NOT) for ; Tue, 14 Nov 2017 12:28:49 -0500 Received: from localhost by e17.ny.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; Tue, 14 Nov 2017 12:28:45 -0500 Received: from b01ledav004.gho.pok.ibm.com (b01ledav004.gho.pok.ibm.com [9.57.199.109]) by b01cxnp23033.gho.pok.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id vAEHSj9056688778; Tue, 14 Nov 2017 17:28:45 GMT Received: from localhost (unknown [127.0.0.1]) by IMSVA (Postfix) with SMTP id 3E97A11204B; Tue, 14 Nov 2017 12:28:10 -0500 (EST) X-IMSS-HAND-OFF-DIRECTIVE: 127.0.0.1:10026 Received: from arbab-laptop.localdomain (unknown [9.41.250.162]) by b01ledav004.gho.pok.ibm.com (Postfix) with ESMTP id 4DB56112034; Tue, 14 Nov 2017 12:28:09 -0500 (EST) Received: by arbab-laptop.localdomain (Postfix, from userid 152845) id F2A39460252; Tue, 14 Nov 2017 11:28:42 -0600 (CST) From: Reza Arbab To: Stewart Smith Date: Tue, 14 Nov 2017 11:28:42 -0600 X-Mailer: git-send-email 1.8.3.1 X-TM-AS-GCONF: 00 x-cbid: 17111417-0040-0000-0000-000003C2A11B X-IBM-SpamModules-Scores: X-IBM-SpamModules-Versions: BY=3.00008066; HX=3.00000241; KW=3.00000007; PH=3.00000004; SC=3.00000240; SDB=6.00945826; UDB=6.00477371; IPR=6.00726123; BA=6.00005690; NDR=6.00000001; ZLA=6.00000005; ZF=6.00000009; ZB=6.00000000; ZP=6.00000000; ZH=6.00000000; ZU=6.00000002; MB=3.00018013; XFM=3.00000015; UTC=2017-11-14 17:28:46 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 17111417-0041-0000-0000-000007B7C0C3 Message-Id: <1510680522-8292-1-git-send-email-arbab@linux.vnet.ibm.com> X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-11-14_08:, , signatures=0 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 suspectscore=0 phishscore=0 bulkscore=0 spamscore=0 clxscore=1015 lowpriorityscore=0 impostorscore=0 adultscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.0.1-1709140000 definitions=main-1711140237 Subject: [Skiboot] [PATCH] Revert "npu2: hw-procedures: Enable low power mode" X-BeenThere: skiboot@lists.ozlabs.org X-Mailman-Version: 2.1.24 Precedence: list List-Id: Mailing list for skiboot development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: skiboot@lists.ozlabs.org, Alistair Popple MIME-Version: 1.0 Errors-To: skiboot-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "Skiboot" As it turns out, low power mode is not yet ready for prime time. We shouldn't write the low power config register until it is. This reverts commit a05054c53a37850a2118d01fcf6669ebb10d1a33. Signed-off-by: Reza Arbab Acked-by: Alistair Popple --- Sorry for the churn on this. We had gotten conflicting direction on exactly what the hardware is capable of at this time. hw/npu2-hw-procedures.c | 19 +------------------ include/npu2-regs.h | 6 ------ 2 files changed, 1 insertion(+), 24 deletions(-) diff --git a/hw/npu2-hw-procedures.c b/hw/npu2-hw-procedures.c index 85c2427..7a5d188 100644 --- a/hw/npu2-hw-procedures.c +++ b/hw/npu2-hw-procedures.c @@ -320,26 +320,9 @@ static uint32_t phy_reset_complete(struct npu2_dev *ndev) phy_write_lane(ndev, &NPU2_PHY_RX_E_INTEG_COARSE_GAIN, lane, 11); } - return PROCEDURE_NEXT; -} - -/* Procedure 1.2.11 - Enable Low Power Mode */ -static uint32_t enable_low_power(struct npu2_dev *ndev) -{ - uint64_t val; - - val = SETFIELD(NPU2_NTL_LOW_POWER_CFG_MODE_ENABLE, 0ull, 1); - val = SETFIELD(NPU2_NTL_LOW_POWER_CFG_ONLY_MODE, val, 1); - val = SETFIELD(NPU2_NTL_LOW_POWER_CFG_TIMER_TICK_CONFIG, val, 22); - val = SETFIELD(NPU2_NTL_LOW_POWER_CFG_MIN_CRED_THRESH, val, 68); - val = SETFIELD(NPU2_NTL_LOW_POWER_CFG_MAX_CRED_THRESH, val, 68); - val = SETFIELD(NPU2_NTL_LOW_POWER_CFG_CNT_THRESH, val, 477); - npu2_write(ndev->npu, NPU2_NTL_LOW_POWER_CFG(ndev), val); - return PROCEDURE_COMPLETE; } -DEFINE_PROCEDURE(phy_reset, phy_reset_wait, phy_reset_complete, - enable_low_power); +DEFINE_PROCEDURE(phy_reset, phy_reset_wait, phy_reset_complete); /* Procedure 1.2.6 - I/O PHY Tx Impedance Calibration */ static uint32_t phy_tx_zcal(struct npu2_dev *ndev) diff --git a/include/npu2-regs.h b/include/npu2-regs.h index 307e93b..759404c 100644 --- a/include/npu2-regs.h +++ b/include/npu2-regs.h @@ -248,12 +248,6 @@ void npu2_write_mask(struct npu2 *p, uint64_t reg, uint64_t val, uint64_t mask); #define NPU2_NTL_MISC_CFG1(ndev) NPU2_NTLU_REG_OFFSET(ndev, 0x0C0) #define NPU2_NTL_SCRATCH1(ndev) NPU2_NTLU_REG_OFFSET(ndev, 0x0D0) #define NPU2_NTL_LOW_POWER_CFG(ndev) NPU2_NTLU_REG_OFFSET(ndev, 0x0E0) -#define NPU2_NTL_LOW_POWER_CFG_MODE_ENABLE PPC_BIT(0) -#define NPU2_NTL_LOW_POWER_CFG_ONLY_MODE PPC_BIT(1) -#define NPU2_NTL_LOW_POWER_CFG_TIMER_TICK_CONFIG PPC_BITMASK(2,7) -#define NPU2_NTL_LOW_POWER_CFG_MIN_CRED_THRESH PPC_BITMASK(8,19) -#define NPU2_NTL_LOW_POWER_CFG_MAX_CRED_THRESH PPC_BITMASK(20,31) -#define NPU2_NTL_LOW_POWER_CFG_CNT_THRESH PPC_BITMASK(32,43) #define NPU2_NTL_DBG_INHIBIT_CFG(ndev) NPU2_NTL_REG_OFFSET(ndev, 0x220) #define NPU2_NTL_DISPLAY_CTL(ndev) NPU2_NTL_REG_OFFSET(ndev, 0x280) #define NPU2_NTL_DISPLAY_DATA0(ndev) NPU2_NTL_REG_OFFSET(ndev, 0x288)