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Wed, 9 Oct 2019 20:26:22 +0000 (GMT) Received: from ibm-toto.the-meissners.org (unknown [9.32.77.177]) by b03ledav002.gho.boulder.ibm.com (Postfix) with ESMTPS; Wed, 9 Oct 2019 20:26:22 +0000 (GMT) Date: Wed, 9 Oct 2019 16:26:20 -0400 From: Michael Meissner To: Michael Meissner , gcc-patches@gcc.gnu.org, segher@kernel.crashing.org, dje.gcc@gmail.com Subject: [PATCH] V5, #6 of 15: Make vector load/store instruction length correct with prefixed addresses Message-ID: <20191009202620.GF2063@ibm-toto.the-meissners.org> Mail-Followup-To: Michael Meissner , gcc-patches@gcc.gnu.org, segher@kernel.crashing.org, dje.gcc@gmail.com References: <20191009194846.GA31507@ibm-toto.the-meissners.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20191009194846.GA31507@ibm-toto.the-meissners.org> User-Agent: Mutt/1.5.21 (2010-09-15) This patch updates the instruction length for 128-bit move insns for types that go into a single vector register. It is a lot simpler than the previous patch, which was written before I added the prefixed_length and non_prefixed_length attributes. Along with the other patches, I have done bootstraps on a little endian power8 system, and there were no regressions in the test suite. Can I check this into the trunk? 2019-10-08 Michael Meissner * config/rs6000/vsx.md (vsx_mov_64bit): Make sure the instruction length is correct for prefixed loads and stores. Index: gcc/config/rs6000/vsx.md =================================================================== --- gcc/config/rs6000/vsx.md (revision 276713) +++ gcc/config/rs6000/vsx.md (working copy) @@ -1149,10 +1149,14 @@ (define_insn "vsx_mov_64bit" "vecstore, vecload, vecsimple, mffgpr, mftgpr, load, store, load, store, *, vecsimple, vecsimple, vecsimple, *, *, vecstore, vecload") - (set_attr "length" + (set_attr "non_prefixed_length" "*, *, *, 8, *, 8, 8, 8, 8, 8, *, *, *, 20, 8, *, *") + (set_attr "prefixed_length" + "*, *, *, 8, *, 20, + 20, 20, 20, 8, *, *, + *, 20, 8, *, *") (set_attr "isa" ", , , *, *, *, *, *, *, *, p9v, *,