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Wed, 9 Oct 2019 19:56:03 +0000 (GMT) Received: from ibm-toto.the-meissners.org (unknown [9.32.77.177]) by b03ledav003.gho.boulder.ibm.com (Postfix) with ESMTPS; Wed, 9 Oct 2019 19:56:02 +0000 (GMT) Date: Wed, 9 Oct 2019 15:56:01 -0400 From: Michael Meissner To: Michael Meissner , gcc-patches@gcc.gnu.org, segher@kernel.crashing.org, dje.gcc@gmail.com Subject: [PATCH] V5, #2 of 15: Fix prefixed instruction length for some 128-bit types Message-ID: <20191009195601.GB2063@ibm-toto.the-meissners.org> Mail-Followup-To: Michael Meissner , gcc-patches@gcc.gnu.org, segher@kernel.crashing.org, dje.gcc@gmail.com References: <20191009194846.GA31507@ibm-toto.the-meissners.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20191009194846.GA31507@ibm-toto.the-meissners.org> User-Agent: Mutt/1.5.21 (2010-09-15) This patch fixes the prefixed and non-prefixed instruction sizes for the 128-bit types that aren't loaded into 128-bit vectors (TDmode, TFmode, IFmode, PTImode). Along with the other patches, I have done bootstraps on a little endian power8 system, and there were no regressions in the test suite. Can I check this into the trunk? 2019-10-08 Michael Meissner * config/rs6000/rs6000.md (mov_64bit_dm): Set prefixed and non-prefixed length. (movtd_64bit_nodm): Set prefixed and non-prefixed length. (mov_ppc64): Set prefixed and non-prefixed length. Index: gcc/config/rs6000/rs6000.md =================================================================== --- gcc/config/rs6000/rs6000.md (revision 276713) +++ gcc/config/rs6000/rs6000.md (working copy) @@ -7773,9 +7773,13 @@ (define_insn_and_split "*mov_64bit "#" "&& reload_completed" [(pc)] -{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; } - [(set_attr "length" "8") - (set_attr "isa" "*,*,*,*,*,*,*,*,p8v,p8v")]) +{ + rs6000_split_multireg_move (operands[0], operands[1]); + DONE; +} + [(set_attr "isa" "*,*,*,*,*,*,*,*,p8v,p8v") + (set_attr "non_prefixed_length" "8") + (set_attr "prefixed_length" "20")]) (define_insn_and_split "*movtd_64bit_nodm" [(set (match_operand:TD 0 "nonimmediate_operand" "=m,d,d,Y,r,r") @@ -7786,8 +7790,12 @@ (define_insn_and_split "*movtd_64bit_nod "#" "&& reload_completed" [(pc)] -{ rs6000_split_multireg_move (operands[0], operands[1]); DONE; } - [(set_attr "length" "8,8,8,12,12,8")]) +{ + rs6000_split_multireg_move (operands[0], operands[1]); + DONE; +} + [(set_attr "non_prefixed_length" "8") + (set_attr "prefixed_length" "20")]) (define_insn_and_split "*mov_32bit" [(set (match_operand:FMOVE128_FPR 0 "nonimmediate_operand" "=m,d,d,d,Y,r,r") @@ -8984,7 +8992,8 @@ (define_insn "*mov_ppc64" return rs6000_output_move_128bit (operands); } [(set_attr "type" "store,store,load,load,*,*") - (set_attr "length" "8")]) + (set_attr "prefixed_length" "20") + (set_attr "non_prefixed_length" "8")]) (define_split [(set (match_operand:TI2 0 "int_reg_operand")