From patchwork Wed Oct 9 07:40:24 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?Q2h1bmZlbmcgWXVuICjkupHmmKXls7Ap?= X-Patchwork-Id: 1173663 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 46p5kH56fVz9sN1 for ; Wed, 9 Oct 2019 18:41:11 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729589AbfJIHlK (ORCPT ); Wed, 9 Oct 2019 03:41:10 -0400 Received: from mailgw02.mediatek.com ([1.203.163.81]:28011 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726336AbfJIHlJ (ORCPT ); Wed, 9 Oct 2019 03:41:09 -0400 X-UUID: 1c0ef69487f141ad80e3b5c84a2adce7-20191009 X-UUID: 1c0ef69487f141ad80e3b5c84a2adce7-20191009 Received: from mtkcas32.mediatek.inc [(172.27.4.253)] by mailgw02.mediatek.com (envelope-from ) (mailgw01.mediatek.com ESMTP with TLS) with ESMTP id 397385473; Wed, 09 Oct 2019 15:41:03 +0800 Received: from mtkcas09.mediatek.inc (172.21.101.178) by MTKMBS31N2.mediatek.inc (172.27.4.87) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Wed, 9 Oct 2019 15:41:00 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas09.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Wed, 9 Oct 2019 15:40:58 +0800 From: Chunfeng Yun To: Kishon Vijay Abraham I , Rob Herring CC: Mark Rutland , Matthias Brugger , Chunfeng Yun , , , , Subject: [RESEND PATCH v3 01/11] dt-bindings: phy-mtk-tphy: add two optional properties for u2phy Date: Wed, 9 Oct 2019 15:40:24 +0800 Message-ID: <1570606834-5644-1-git-send-email-chunfeng.yun@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty MIME-Version: 1.0 X-TM-SNTS-SMTP: D92F16B9EE319C5ADF5B71546DF82E0BFA49E37F44BEABF32811ABA90F90DB2B2000:8 X-MTK: N Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add two optional properties, one for tuning J-K voltage by INTR, another for disconnect threshold, both of them are related with connect detection Signed-off-by: Chunfeng Yun --- v3: change commit log v2: change description --- Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt b/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt index a5f7a4f0dbc1..ce6abfbdfbe1 100644 --- a/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt +++ b/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt @@ -52,6 +52,8 @@ Optional properties (PHY_TYPE_USB2 port (child) node): - mediatek,eye-vrt : u32, the selection of VRT reference voltage - mediatek,eye-term : u32, the selection of HS_TX TERM reference voltage - mediatek,bc12 : bool, enable BC12 of u2phy if support it +- mediatek,discth : u32, the selection of disconnect threshold +- mediatek,intr : u32, the selection of internal R (resistance) Example: From patchwork Wed Oct 9 07:40:25 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?Q2h1bmZlbmcgWXVuICjkupHmmKXls7Ap?= X-Patchwork-Id: 1173664 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 46p5kN3w6lz9sN1 for ; Wed, 9 Oct 2019 18:41:16 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729790AbfJIHlM (ORCPT ); Wed, 9 Oct 2019 03:41:12 -0400 Received: from Mailgw01.mediatek.com ([1.203.163.78]:64445 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1729285AbfJIHlL (ORCPT ); Wed, 9 Oct 2019 03:41:11 -0400 X-UUID: dfd5932131c74183bd2bba32fb30f582-20191009 X-UUID: dfd5932131c74183bd2bba32fb30f582-20191009 Received: from mtkcas36.mediatek.inc [(172.27.4.253)] by mailgw01.mediatek.com (envelope-from ) (mailgw01.mediatek.com ESMTP with TLS) with ESMTP id 334976308; Wed, 09 Oct 2019 15:41:04 +0800 Received: from mtkcas09.mediatek.inc (172.21.101.178) by MTKMBS31N1.mediatek.inc (172.27.4.69) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Wed, 9 Oct 2019 15:41:02 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas09.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Wed, 9 Oct 2019 15:41:00 +0800 From: Chunfeng Yun To: Kishon Vijay Abraham I , Rob Herring CC: Mark Rutland , Matthias Brugger , Chunfeng Yun , , , , Subject: [RESEND PATCH v3 02/11] dt-bindings: phy-mtk-tphy: make the ref clock optional Date: Wed, 9 Oct 2019 15:40:25 +0800 Message-ID: <1570606834-5644-2-git-send-email-chunfeng.yun@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1570606834-5644-1-git-send-email-chunfeng.yun@mediatek.com> References: <1570606834-5644-1-git-send-email-chunfeng.yun@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: 529B75F880549219B19A483FC609AD75F20A14647891354584FF2E06AC6263472000:8 X-MTK: N Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Make the ref clock optional, then we no need refer to a fixed-clock in DTS anymore when the clock of USB3 PHY comes from oscillator directly Signed-off-by: Chunfeng Yun Acked-by: Rob Herring --- v3: add acked-by Rob v2: no changes --- .../devicetree/bindings/phy/phy-mtk-tphy.txt | 13 +++++++------ 1 file changed, 7 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt b/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt index ce6abfbdfbe1..1f4a36dd80e0 100644 --- a/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt +++ b/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt @@ -34,12 +34,6 @@ Optional properties (controller (parent) node): Required properties (port (child) node): - reg : address and length of the register set for the port. -- clocks : a list of phandle + clock-specifier pairs, one for each - entry in clock-names -- clock-names : must contain - "ref": 48M reference clock for HighSpeed analog phy; and 26M - reference clock for SuperSpeed analog phy, sometimes is - 24M, 25M or 27M, depended on platform. - #phy-cells : should be 1 (See second example) cell after port phandle is phy type from: - PHY_TYPE_USB2 @@ -48,6 +42,13 @@ Required properties (port (child) node): - PHY_TYPE_SATA Optional properties (PHY_TYPE_USB2 port (child) node): +- clocks : a list of phandle + clock-specifier pairs, one for each + entry in clock-names +- clock-names : may contain + "ref": 48M reference clock for HighSpeed anolog phy; and 26M + reference clock for SuperSpeed anolog phy, sometimes is + 24M, 25M or 27M, depended on platform. + - mediatek,eye-src : u32, the value of slew rate calibrate - mediatek,eye-vrt : u32, the selection of VRT reference voltage - mediatek,eye-term : u32, the selection of HS_TX TERM reference voltage From patchwork Wed Oct 9 07:40:26 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?Q2h1bmZlbmcgWXVuICjkupHmmKXls7Ap?= X-Patchwork-Id: 1173665 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 46p5kP2yDTz9sPF for ; Wed, 9 Oct 2019 18:41:17 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729596AbfJIHlQ (ORCPT ); Wed, 9 Oct 2019 03:41:16 -0400 Received: from Mailgw01.mediatek.com ([1.203.163.78]:25202 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726336AbfJIHlN (ORCPT ); Wed, 9 Oct 2019 03:41:13 -0400 X-UUID: 1c2c8945898f44379b96f4c6da2a9510-20191009 X-UUID: 1c2c8945898f44379b96f4c6da2a9510-20191009 Received: from mtkcas32.mediatek.inc [(172.27.4.253)] by mailgw01.mediatek.com (envelope-from ) (mailgw01.mediatek.com ESMTP with TLS) with ESMTP id 712371107; Wed, 09 Oct 2019 15:41:06 +0800 Received: from mtkcas09.mediatek.inc (172.21.101.178) by MTKMBS31DR.mediatek.inc (172.27.6.102) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Wed, 9 Oct 2019 15:41:04 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas09.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Wed, 9 Oct 2019 15:41:03 +0800 From: Chunfeng Yun To: Kishon Vijay Abraham I , Rob Herring CC: Mark Rutland , Matthias Brugger , Chunfeng Yun , , , , Subject: [RESEND PATCH v3 03/11] dt-bindings: phy-mtk-tphy: remove unused u3phya_ref clock Date: Wed, 9 Oct 2019 15:40:26 +0800 Message-ID: <1570606834-5644-3-git-send-email-chunfeng.yun@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1570606834-5644-1-git-send-email-chunfeng.yun@mediatek.com> References: <1570606834-5644-1-git-send-email-chunfeng.yun@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: 1720D9286211C13975F0039AA85CB57381AE6118C83D4742D036AE587AC9B3092000:8 X-MTK: N Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The u3phya_ref clock is already moved into sub-node, and renamed as ref clock, no used anymore now, so remove it to avoid confusion Signed-off-by: Chunfeng Yun Reviewed-by: Rob Herring --- v3: no changes v2: add Reviewed-by Rob --- Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt | 4 ---- 1 file changed, 4 deletions(-) diff --git a/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt b/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt index 1f4a36dd80e0..48bc1a2e9299 100644 --- a/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt +++ b/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt @@ -13,10 +13,6 @@ Required properties (controller (parent) node): "mediatek,mt8173-u3phy"; make use of "mediatek,generic-tphy-v1" on mt2701 instead and "mediatek,generic-tphy-v2" on mt2712 instead. - - clocks : (deprecated, use port's clocks instead) a list of phandle + - clock-specifier pairs, one for each entry in clock-names - - clock-names : (deprecated, use port's one instead) must contain - "u3phya_ref": for reference clock of usb3.0 analog phy. Required nodes : a sub-node is required for each port the controller provides. Address range information including the usual From patchwork Wed Oct 9 07:40:27 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?Q2h1bmZlbmcgWXVuICjkupHmmKXls7Ap?= X-Patchwork-Id: 1173666 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 46p5kR4WHrz9sN1 for ; Wed, 9 Oct 2019 18:41:19 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726336AbfJIHlS (ORCPT ); Wed, 9 Oct 2019 03:41:18 -0400 Received: from mailgw02.mediatek.com ([1.203.163.81]:34807 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1729285AbfJIHlR (ORCPT ); Wed, 9 Oct 2019 03:41:17 -0400 X-UUID: 1870a9197fd94a71b8d4fc96f83bbf18-20191009 X-UUID: 1870a9197fd94a71b8d4fc96f83bbf18-20191009 Received: from mtkcas36.mediatek.inc [(172.27.4.253)] by mailgw02.mediatek.com (envelope-from ) (mailgw01.mediatek.com ESMTP with TLS) with ESMTP id 540729341; Wed, 09 Oct 2019 15:41:09 +0800 Received: from mtkcas09.mediatek.inc (172.21.101.178) by MTKMBS31N2.mediatek.inc (172.27.4.87) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Wed, 9 Oct 2019 15:41:06 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas09.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Wed, 9 Oct 2019 15:41:05 +0800 From: Chunfeng Yun To: Kishon Vijay Abraham I , Rob Herring CC: Mark Rutland , Matthias Brugger , Chunfeng Yun , , , , Subject: [RESEND PATCH v3 04/11] dt-bindings: phy-mtk-tphy: add a new reference clock Date: Wed, 9 Oct 2019 15:40:27 +0800 Message-ID: <1570606834-5644-4-git-send-email-chunfeng.yun@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1570606834-5644-1-git-send-email-chunfeng.yun@mediatek.com> References: <1570606834-5644-1-git-send-email-chunfeng.yun@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: F919BEA736F2E41C7EDF4A0549A97035BFD402A7E81A4B2B03EF41062627BD702000:8 X-MTK: N Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Usually the digital and analog phys use the same reference clock, but on some platforms, they are separated, so add another optional clock to support it. In order to keep the clock names consistent with PHY IP's, use the da_ref for analog phy and ref clock for digital phy. Signed-off-by: Chunfeng Yun Acked-by: Rob Herring --- v3: add acked-by Rob v2: fix typo of analog and needed --- Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt b/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt index 48bc1a2e9299..a859b0db4051 100644 --- a/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt +++ b/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt @@ -41,9 +41,12 @@ Optional properties (PHY_TYPE_USB2 port (child) node): - clocks : a list of phandle + clock-specifier pairs, one for each entry in clock-names - clock-names : may contain - "ref": 48M reference clock for HighSpeed anolog phy; and 26M - reference clock for SuperSpeed anolog phy, sometimes is + "ref": 48M reference clock for HighSpeed (digital) phy; and 26M + reference clock for SuperSpeed (digital) phy, sometimes is 24M, 25M or 27M, depended on platform. + "da_ref": the reference clock of analog phy, used if the clocks + of analog and digital phys are separated, otherwise uses + "ref" clock only if needed. - mediatek,eye-src : u32, the value of slew rate calibrate - mediatek,eye-vrt : u32, the selection of VRT reference voltage From patchwork Wed Oct 9 07:40:28 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?b?Q2h1bmZlbmcgWXVuICjkupHmmKXls7Ap?= X-Patchwork-Id: 1173667 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 46p5kZ07Gcz9sN1 for ; Wed, 9 Oct 2019 18:41:26 +1100 (AEDT) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729918AbfJIHlU (ORCPT ); Wed, 9 Oct 2019 03:41:20 -0400 Received: from mailgw02.mediatek.com ([1.203.163.81]:55445 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1729863AbfJIHlT (ORCPT ); Wed, 9 Oct 2019 03:41:19 -0400 X-UUID: 7de2cdb847244d8a91cf92e47980e8ee-20191009 X-UUID: 7de2cdb847244d8a91cf92e47980e8ee-20191009 Received: from mtkcas35.mediatek.inc [(172.27.4.253)] by mailgw02.mediatek.com (envelope-from ) (mailgw01.mediatek.com ESMTP with TLS) with ESMTP id 740149483; Wed, 09 Oct 2019 15:41:11 +0800 Received: from mtkcas09.mediatek.inc (172.21.101.178) by MTKMBS31N1.mediatek.inc (172.27.4.69) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Wed, 9 Oct 2019 15:41:08 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas09.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Wed, 9 Oct 2019 15:41:07 +0800 From: Chunfeng Yun To: Kishon Vijay Abraham I , Rob Herring CC: Mark Rutland , Matthias Brugger , Chunfeng Yun , , , , Subject: [RESEND PATCH v3 05/11] dt-bindings: phy-mtk-tphy: add the properties about address mapping Date: Wed, 9 Oct 2019 15:40:28 +0800 Message-ID: <1570606834-5644-5-git-send-email-chunfeng.yun@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1570606834-5644-1-git-send-email-chunfeng.yun@mediatek.com> References: <1570606834-5644-1-git-send-email-chunfeng.yun@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: C05F62D1C5E751FB6397A3C160DCD05478728B7C988E223A8B72F79807F3C4242000:8 X-MTK: N Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add three required properties about the address mapping, including '#address-cells', '#size-cells' and 'ranges' Signed-off-by: Chunfeng Yun Reviewed-by: Rob Herring --- v3: no changes v2: add Reviewed-by Rob --- Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt b/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt index a859b0db4051..dd75b676b71d 100644 --- a/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt +++ b/Documentation/devicetree/bindings/phy/phy-mtk-tphy.txt @@ -14,6 +14,16 @@ Required properties (controller (parent) node): make use of "mediatek,generic-tphy-v1" on mt2701 instead and "mediatek,generic-tphy-v2" on mt2712 instead. +- #address-cells: the number of cells used to represent physical + base addresses. +- #size-cells: the number of cells used to represent the size of an address. +- ranges: the address mapping relationship to the parent, defined with + - empty value: if optional 'reg' is used. + - non-empty value: if optional 'reg' is not used. should set + the child's base address to 0, the physical address + within parent's address space, and the length of + the address map. + Required nodes : a sub-node is required for each port the controller provides. Address range information including the usual 'reg' property is used inside these nodes to describe