From patchwork Mon Oct 7 17:06:44 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 1172914 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=amsat.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="NAXJKlWY"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 46n6f94tpxz9sCJ for ; Tue, 8 Oct 2019 04:19:13 +1100 (AEDT) Received: from localhost ([::1]:48044 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iHWf9-0001Zm-Fq for incoming@patchwork.ozlabs.org; Mon, 07 Oct 2019 13:19:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36999) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1iHWTH-0006k5-Sj for qemu-devel@nongnu.org; Mon, 07 Oct 2019 13:06:57 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1iHWTF-0004ut-Rm for qemu-devel@nongnu.org; Mon, 07 Oct 2019 13:06:55 -0400 Received: from mail-wm1-x342.google.com ([2a00:1450:4864:20::342]:38709) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1iHWTF-0004uZ-KI; Mon, 07 Oct 2019 13:06:53 -0400 Received: by mail-wm1-x342.google.com with SMTP id 3so262871wmi.3; Mon, 07 Oct 2019 10:06:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=e1Snfw54qByhFem85dbkNaD4L+dqPgwwgdg4e/O7Ibc=; b=NAXJKlWYcUB/LUYRANjRSqPjRaIn6iB91jdJl5Xn029Mzo9UqXjpN0UKY+bqOPoL17 mDU71Jz2bhdQZMdprLFbZ4HU9AXSxf34KnPkmo9ifbRwN0jBp/wTrg55/RtSOHvXHj4N FTLJ+LEdwecQzWl8L1geTErpY5hi6a5l2GENUOm6mJJYhxGpnNtL5u4RGoSQo7YXo36N E/NJhKcKyZAElzb3Uq1E/KGJhtnLg3OEGIV2O58/TFZDxcJidujtXQtbGlXdOVXGuprB U4+HeBQPO1t7VU+c62OPlJRr/uwKWs4zG+UmjEHTfMTyf3iiHnzX31/XdDHmtLazaRE9 7adg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=e1Snfw54qByhFem85dbkNaD4L+dqPgwwgdg4e/O7Ibc=; b=UD5kklZB/+YIfSq+rBvGatWOhf36YHp52PLR+wwJQq2T00NA5f+00ik/qtE9l41Oh0 rWVno911dSDIrX+M8kzOrZK3HQa+eLECI4HAQdw1P9WSs6X/O4AzXWLs0wNTZ1olUkQf 9Sw/h+tfI08cHnj20vw5ObbBBo/0CUBoBcaJXPa9qGpoMXd1HbFHDdezt0zKPk8Kbkv1 gRiaQoOYMDqdkYBx4i8vZaPnJn7ZsBPZLfmPmdOVxUB2PLaq0HUZNrTX8rjPsWIYKK5v BsX7CJyeZZj/y/SiNih5qcUYGwfP6b+IRXU90myv90nUaNU24jFtwOkIFIzFPPUUQJ8l n9Bw== X-Gm-Message-State: APjAAAWDqq3HbxIj739N2vxEIcFWn1nOYmXIRZr73ZTBvoy29vWXU+4i 11EchpzJWyb5zDiAkovuOJfgknojCmM= X-Google-Smtp-Source: APXvYqyBu9Iat3kMycK9D9B9YrRS+adpZ1OjfNu7j1QNJ5nvfADvKaTt+XP9CyqowNp6Sx15TKPIug== X-Received: by 2002:a1c:1b0b:: with SMTP id b11mr249281wmb.82.1570468012040; Mon, 07 Oct 2019 10:06:52 -0700 (PDT) Received: from x1w.redhat.com (46.red-83-42-66.dynamicip.rima-tde.net. [83.42.66.46]) by smtp.gmail.com with ESMTPSA id x5sm14036603wrt.75.2019.10.07.10.06.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Oct 2019 10:06:51 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH 1/3] hw/char: Add the BCM2835 miniuart Date: Mon, 7 Oct 2019 19:06:44 +0200 Message-Id: <20191007170646.14961-2-f4bug@amsat.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191007170646.14961-1-f4bug@amsat.org> References: <20191007170646.14961-1-f4bug@amsat.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::342 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Alistair Francis , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Andrew Baumann , qemu-arm@nongnu.org, Paolo Bonzini , Marc-Andre Lureau , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" The miniuart code is already present in the multi-device hw/char/bcm2835_aux.c. Simply extracting it does not generate patch easy to review. Instead, add it again, rename the function names accordingly, use the "hw/registerfields.h" API. This is roughtly a copy of commit 97398d900caacc. Signed-off-by: Philippe Mathieu-Daudé Acked-by: Alistair Francis --- hw/char/Makefile.objs | 1 + hw/char/bcm2835_miniuart.c | 327 +++++++++++++++++++++++++++++ hw/char/trace-events | 4 + include/hw/char/bcm2835_miniuart.h | 37 ++++ 4 files changed, 369 insertions(+) create mode 100644 hw/char/bcm2835_miniuart.c create mode 100644 include/hw/char/bcm2835_miniuart.h diff --git a/hw/char/Makefile.objs b/hw/char/Makefile.objs index 02d8a66925..5bd93bde9f 100644 --- a/hw/char/Makefile.objs +++ b/hw/char/Makefile.objs @@ -22,6 +22,7 @@ obj-$(CONFIG_DIGIC) += digic-uart.o obj-$(CONFIG_STM32F2XX_USART) += stm32f2xx_usart.o obj-$(CONFIG_RASPI) += bcm2835_aux.o +common-obj-$(CONFIG_RASPI) += bcm2835_miniuart.o common-obj-$(CONFIG_CMSDK_APB_UART) += cmsdk-apb-uart.o common-obj-$(CONFIG_ETRAXFS) += etraxfs_ser.o common-obj-$(CONFIG_ISA_DEBUG) += debugcon.o diff --git a/hw/char/bcm2835_miniuart.c b/hw/char/bcm2835_miniuart.c new file mode 100644 index 0000000000..0e99cecce7 --- /dev/null +++ b/hw/char/bcm2835_miniuart.c @@ -0,0 +1,327 @@ +/* + * BCM2835 (Raspberry Pi) mini UART block. + * + * Copyright (c) 2015, Microsoft + * Written by Andrew Baumann + * Based on pl011.c. + * + * This code is licensed under the GPL. + * + * At present only the core UART functions (data path for tx/rx) are + * implemented. The following features/registers are unimplemented: + * - Line/modem control + * - Scratch register + * - Extra control + * - Baudrate + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "hw/char/bcm2835_miniuart.h" +#include "hw/qdev-properties.h" +#include "hw/registerfields.h" +#include "migration/vmstate.h" +#include "trace.h" + +REG32(MU_IO, 0x00) +REG32(MU_IER, 0x04) +REG32(MU_IIR, 0x08) +REG32(MU_LCR, 0x0c) +REG32(MU_MCR, 0x10) +REG32(MU_LSR, 0x14) +REG32(MU_MSR, 0x18) +REG32(MU_SCRATCH, 0x1c) +REG32(MU_CNTL, 0x20) +REG32(MU_STAT, 0x24) +REG32(MU_BAUD, 0x28) + +/* bits in IER/IIR registers */ +#define RX_INT 0x1 +#define TX_INT 0x2 + +static void bcm2835_miniuart_update(BCM2835MiniUartState *s) +{ + /* + * Signal an interrupt if either: + * + * 1. rx interrupt is enabled and we have a non-empty rx fifo, or + * 2. the tx interrupt is enabled (since we instantly drain the tx fifo) + */ + s->iir = 0; + if ((s->ier & RX_INT) && s->read_count != 0) { + s->iir |= RX_INT; + } + if (s->ier & TX_INT) { + s->iir |= TX_INT; + } + qemu_set_irq(s->irq, s->iir != 0); +} + +static bool is_16650(hwaddr offset) +{ + return offset < A_MU_CNTL; +} + +static uint64_t bcm2835_miniuart_read(void *opaque, hwaddr offset, + unsigned size) +{ + BCM2835MiniUartState *s = opaque; + uint32_t c, res = 0; + + switch (offset) { + case A_MU_IO: + /* "DLAB bit set means access baudrate register" is NYI */ + c = s->read_fifo[s->read_pos]; + if (s->read_count > 0) { + s->read_count--; + if (++s->read_pos == BCM2835_MINIUART_RX_FIFO_LEN) { + s->read_pos = 0; + } + } + qemu_chr_fe_accept_input(&s->chr); + bcm2835_miniuart_update(s); + res = c; + break; + + case A_MU_IER: + /* "DLAB bit set means access baudrate register" is NYI */ + res = 0xc0 | s->ier; /* FIFO enables always read 1 */ + break; + + case A_MU_IIR: + res = 0xc0; /* FIFO enables */ + /* + * The spec is unclear on what happens when both tx and rx + * interrupts are active, besides that this cannot occur. At + * present, we choose to prioritise the rx interrupt, since + * the tx fifo is always empty. + */ + if (s->read_count != 0) { + res |= 0x4; + } else { + res |= 0x2; + } + if (s->iir == 0) { + res |= 0x1; + } + break; + + case A_MU_LCR: + qemu_log_mask(LOG_UNIMP, "%s: A_MU_LCR_REG unsupported\n", __func__); + break; + + case A_MU_MCR: + qemu_log_mask(LOG_UNIMP, "%s: A_MU_MCR_REG unsupported\n", __func__); + break; + + case A_MU_LSR: + res = 0x60; /* tx idle, empty */ + if (s->read_count != 0) { + res |= 0x1; + } + break; + + case A_MU_MSR: + qemu_log_mask(LOG_UNIMP, "%s: A_MU_MSR_REG unsupported\n", __func__); + break; + + case A_MU_SCRATCH: + qemu_log_mask(LOG_UNIMP, "%s: A_MU_SCRATCH unsupported\n", __func__); + break; + + case A_MU_CNTL: + res = 0x3; /* tx, rx enabled */ + break; + + case A_MU_STAT: + res = 0x30e; /* space in the output buffer, empty tx fifo, idle tx/rx */ + if (s->read_count > 0) { + res |= 0x1; /* data in input buffer */ + assert(s->read_count < BCM2835_MINIUART_RX_FIFO_LEN); + res |= ((uint32_t)s->read_count) << 16; /* rx fifo fill level */ + } + break; + + case A_MU_BAUD: + qemu_log_mask(LOG_UNIMP, "%s: A_MU_BAUD_REG unsupported\n", __func__); + break; + + default: + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n", + __func__, offset); + break; + } + + if (is_16650(offset)) { + trace_serial_ioport_read((offset & 0x1f) >> 2, res); + } else { + trace_bcm2835_miniuart_read(offset, res); + } + + return res; +} + +static void bcm2835_miniuart_write(void *opaque, hwaddr offset, uint64_t value, + unsigned size) +{ + BCM2835MiniUartState *s = opaque; + unsigned char ch; + + if (is_16650(offset)) { + trace_serial_ioport_write((offset & 0x1f) >> 2, value); + } else { + trace_bcm2835_miniuart_write(offset, value); + } + + switch (offset) { + case A_MU_IO: + /* "DLAB bit set means access baudrate register" is NYI */ + ch = value; + /* + * XXX this blocks entire thread. Rewrite to use + * qemu_chr_fe_write and background I/O callbacks + */ + qemu_chr_fe_write_all(&s->chr, &ch, 1); + break; + + case A_MU_IER: + /* "DLAB bit set means access baudrate register" is NYI */ + s->ier = value & (TX_INT | RX_INT); + bcm2835_miniuart_update(s); + break; + + case A_MU_IIR: + if (value & 0x2) { + s->read_count = 0; + } + break; + + case A_MU_LCR: + qemu_log_mask(LOG_UNIMP, "%s: A_MU_LCR_REG unsupported\n", __func__); + break; + + case A_MU_MCR: + qemu_log_mask(LOG_UNIMP, "%s: A_MU_MCR_REG unsupported\n", __func__); + break; + + case A_MU_SCRATCH: + qemu_log_mask(LOG_UNIMP, "%s: A_MU_SCRATCH unsupported\n", __func__); + break; + + case A_MU_CNTL: + qemu_log_mask(LOG_UNIMP, "%s: A_MU_CNTL_REG unsupported\n", __func__); + break; + + case A_MU_BAUD: + qemu_log_mask(LOG_UNIMP, "%s: A_MU_BAUD_REG unsupported\n", __func__); + break; + + default: + qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n", + __func__, offset); + } + + bcm2835_miniuart_update(s); +} + +static int bcm2835_miniuart_can_receive(void *opaque) +{ + BCM2835MiniUartState *s = opaque; + + return s->read_count < BCM2835_MINIUART_RX_FIFO_LEN; +} + +static void bcm2835_miniuart_put_fifo(void *opaque, uint8_t value) +{ + BCM2835MiniUartState *s = opaque; + int slot; + + slot = s->read_pos + s->read_count; + if (slot >= BCM2835_MINIUART_RX_FIFO_LEN) { + slot -= BCM2835_MINIUART_RX_FIFO_LEN; + } + s->read_fifo[slot] = value; + s->read_count++; + if (s->read_count == BCM2835_MINIUART_RX_FIFO_LEN) { + /* buffer full */ + } + bcm2835_miniuart_update(s); +} + +static void bcm2835_miniuart_receive(void *opaque, const uint8_t *buf, int size) +{ + bcm2835_miniuart_put_fifo(opaque, *buf); +} + +static const MemoryRegionOps bcm2835_miniuart_ops = { + .read = bcm2835_miniuart_read, + .write = bcm2835_miniuart_write, + .endianness = DEVICE_NATIVE_ENDIAN, + .valid.min_access_size = 4, + .valid.max_access_size = 4, +}; + +static const VMStateDescription vmstate_bcm2835_aux = { + .name = TYPE_BCM2835_MINIUART, + .version_id = 1, + .minimum_version_id = 1, + .fields = (VMStateField[]) { + VMSTATE_UINT8_ARRAY(read_fifo, BCM2835MiniUartState, + BCM2835_MINIUART_RX_FIFO_LEN), + VMSTATE_UINT8(read_pos, BCM2835MiniUartState), + VMSTATE_UINT8(read_count, BCM2835MiniUartState), + VMSTATE_UINT8(ier, BCM2835MiniUartState), + VMSTATE_UINT8(iir, BCM2835MiniUartState), + VMSTATE_END_OF_LIST() + } +}; + +static void bcm2835_miniuart_init(Object *obj) +{ + SysBusDevice *sbd = SYS_BUS_DEVICE(obj); + BCM2835MiniUartState *s = BCM2835_MINIUART(obj); + + memory_region_init_io(&s->iomem, OBJECT(s), &bcm2835_miniuart_ops, s, + TYPE_BCM2835_MINIUART, 0x40); + sysbus_init_mmio(sbd, &s->iomem); + sysbus_init_irq(sbd, &s->irq); +} + +static void bcm2835_miniuart_realize(DeviceState *dev, Error **errp) +{ + BCM2835MiniUartState *s = BCM2835_MINIUART(dev); + + qemu_chr_fe_set_handlers(&s->chr, bcm2835_miniuart_can_receive, + bcm2835_miniuart_receive, NULL, NULL, + s, NULL, true); +} + +static Property bcm2835_miniuart_props[] = { + DEFINE_PROP_CHR("chardev", BCM2835MiniUartState, chr), + DEFINE_PROP_END_OF_LIST(), +}; + +static void bcm2835_miniuart_class_init(ObjectClass *oc, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(oc); + + dc->realize = bcm2835_miniuart_realize; + dc->vmsd = &vmstate_bcm2835_aux; + set_bit(DEVICE_CATEGORY_INPUT, dc->categories); + dc->props = bcm2835_miniuart_props; +} + +static const TypeInfo bcm2835_miniuart_info = { + .name = TYPE_BCM2835_MINIUART, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(BCM2835MiniUartState), + .instance_init = bcm2835_miniuart_init, + .class_init = bcm2835_miniuart_class_init, +}; + +static void bcm2835_miniuart_register_types(void) +{ + type_register_static(&bcm2835_miniuart_info); +} + +type_init(bcm2835_miniuart_register_types) diff --git a/hw/char/trace-events b/hw/char/trace-events index 2ce7f2f998..f1e6dd9918 100644 --- a/hw/char/trace-events +++ b/hw/char/trace-events @@ -1,5 +1,9 @@ # See docs/devel/tracing.txt for syntax documentation. +# bcm2835_miniuart.c +bcm2835_miniuart_read(uint64_t addr, uint32_t value) "read addr 0x%"PRIx64" value 0x%x" +bcm2835_miniuart_write(uint64_t addr, uint32_t value) "read addr 0x%"PRIx64" value 0x%x" + # parallel.c parallel_ioport_read(const char *desc, uint16_t addr, uint8_t value) "read [%s] addr 0x%02x val 0x%02x" parallel_ioport_write(const char *desc, uint16_t addr, uint8_t value) "write [%s] addr 0x%02x val 0x%02x" diff --git a/include/hw/char/bcm2835_miniuart.h b/include/hw/char/bcm2835_miniuart.h new file mode 100644 index 0000000000..54d3b622ed --- /dev/null +++ b/include/hw/char/bcm2835_miniuart.h @@ -0,0 +1,37 @@ +/* + * BCM2835 (Raspberry Pi) mini UART block. + * + * Copyright (c) 2015, Microsoft + * Written by Andrew Baumann + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef HW_CHAR_BCM2835_MINIUART_H +#define HW_CHAR_BCM2835_MINIUART_H + +#include "chardev/char-fe.h" +#include "hw/sysbus.h" +#include "hw/irq.h" + +#define TYPE_BCM2835_MINIUART "bcm2835-miniuart" +#define BCM2835_MINIUART(obj) \ + OBJECT_CHECK(BCM2835MiniUartState, (obj), TYPE_BCM2835_MINIUART) + +#define BCM2835_MINIUART_RX_FIFO_LEN 8 + +typedef struct { + /*< private >*/ + SysBusDevice parent_obj; + /*< public >*/ + + MemoryRegion iomem; + CharBackend chr; + qemu_irq irq; + + uint8_t read_fifo[BCM2835_MINIUART_RX_FIFO_LEN]; + uint8_t read_pos, read_count; + uint8_t ier, iir; +} BCM2835MiniUartState; + +#endif From patchwork Mon Oct 7 17:06:45 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 1172908 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=amsat.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="vbK7cbx6"; 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[83.42.66.46]) by smtp.gmail.com with ESMTPSA id x5sm14036603wrt.75.2019.10.07.10.06.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Oct 2019 10:06:53 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH 2/3] hw/char/bcm2835_aux: Use the BCM2835 miniuart block Date: Mon, 7 Oct 2019 19:06:45 +0200 Message-Id: <20191007170646.14961-3-f4bug@amsat.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191007170646.14961-1-f4bug@amsat.org> References: <20191007170646.14961-1-f4bug@amsat.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::441 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Alistair Francis , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Andrew Baumann , qemu-arm@nongnu.org, Paolo Bonzini , Marc-Andre Lureau , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" In the previous commit we extracted the miniuart block. Time to use it. It is mapped at offset 0x40 in the AUX block, and uses the first IRQ. Due to incomplete Clock Tree support, Linux kernel fails at initializing the UART clock and disable this block. For now Disable this feature with the 'aux_enable_supported' variable. Signed-off-by: Philippe Mathieu-Daudé --- hw/char/bcm2835_aux.c | 280 +++++++++------------------------- hw/char/trace-events | 4 + include/hw/char/bcm2835_aux.h | 10 +- 3 files changed, 83 insertions(+), 211 deletions(-) diff --git a/hw/char/bcm2835_aux.c b/hw/char/bcm2835_aux.c index 3f855196e3..a1ca9741d6 100644 --- a/hw/char/bcm2835_aux.c +++ b/hw/char/bcm2835_aux.c @@ -2,19 +2,10 @@ * BCM2835 (Raspberry Pi / Pi 2) Aux block (mini UART and SPI). * Copyright (c) 2015, Microsoft * Written by Andrew Baumann - * Based on pl011.c, copyright terms below: - * - * Arm PrimeCell PL011 UART - * - * Copyright (c) 2006 CodeSourcery. - * Written by Paul Brook * * This code is licensed under the GPL. * - * At present only the core UART functions (data path for tx/rx) are - * implemented. The following features/registers are unimplemented: - * - Line/modem control - * - Scratch register + * The following features/registers are unimplemented: * - Extra control * - Baudrate * - SPI interfaces @@ -24,189 +15,77 @@ #include "hw/char/bcm2835_aux.h" #include "hw/irq.h" #include "hw/qdev-properties.h" +#include "hw/registerfields.h" #include "migration/vmstate.h" #include "qemu/log.h" #include "qemu/module.h" +#include "qapi/error.h" +#include "trace.h" -#define AUX_IRQ 0x0 -#define AUX_ENABLES 0x4 -#define AUX_MU_IO_REG 0x40 -#define AUX_MU_IER_REG 0x44 -#define AUX_MU_IIR_REG 0x48 -#define AUX_MU_LCR_REG 0x4c -#define AUX_MU_MCR_REG 0x50 -#define AUX_MU_LSR_REG 0x54 -#define AUX_MU_MSR_REG 0x58 -#define AUX_MU_SCRATCH 0x5c -#define AUX_MU_CNTL_REG 0x60 -#define AUX_MU_STAT_REG 0x64 -#define AUX_MU_BAUD_REG 0x68 +REG32(AUX_IRQ, 0x00) +REG32(AUX_ENABLE, 0x04) -/* bits in IER/IIR registers */ -#define RX_INT 0x1 -#define TX_INT 0x2 +static const bool aux_enable_supported = false; static void bcm2835_aux_update(BCM2835AuxState *s) { - /* signal an interrupt if either: - * 1. rx interrupt is enabled and we have a non-empty rx fifo, or - * 2. the tx interrupt is enabled (since we instantly drain the tx fifo) - */ - s->iir = 0; - if ((s->ier & RX_INT) && s->read_count != 0) { - s->iir |= RX_INT; - } - if (s->ier & TX_INT) { - s->iir |= TX_INT; - } - qemu_set_irq(s->irq, s->iir != 0); + qemu_set_irq(s->irq, !!(s->reg[R_AUX_IRQ] & s->reg[R_AUX_ENABLE])); +} + +static void bcm2835_aux_set_irq(void *opaque, int irq, int level) +{ + BCM2835AuxState *s = opaque; + + s->reg[R_AUX_IRQ] = deposit32(s->reg[R_AUX_IRQ], irq, 1, !!level); + + bcm2835_aux_update(s); } static uint64_t bcm2835_aux_read(void *opaque, hwaddr offset, unsigned size) { - BCM2835AuxState *s = opaque; - uint32_t c, res; + BCM2835AuxState *s = BCM2835_AUX(opaque); + uint32_t res = 0; switch (offset) { - case AUX_IRQ: - return s->iir != 0; + case A_AUX_IRQ: + res = s->reg[R_AUX_IRQ]; + break; - case AUX_ENABLES: - return 1; /* mini UART permanently enabled */ - - case AUX_MU_IO_REG: - /* "DLAB bit set means access baudrate register" is NYI */ - c = s->read_fifo[s->read_pos]; - if (s->read_count > 0) { - s->read_count--; - if (++s->read_pos == BCM2835_AUX_RX_FIFO_LEN) { - s->read_pos = 0; - } - } - qemu_chr_fe_accept_input(&s->chr); - bcm2835_aux_update(s); - return c; - - case AUX_MU_IER_REG: - /* "DLAB bit set means access baudrate register" is NYI */ - return 0xc0 | s->ier; /* FIFO enables always read 1 */ - - case AUX_MU_IIR_REG: - res = 0xc0; /* FIFO enables */ - /* The spec is unclear on what happens when both tx and rx - * interrupts are active, besides that this cannot occur. At - * present, we choose to prioritise the rx interrupt, since - * the tx fifo is always empty. */ - if (s->read_count != 0) { - res |= 0x4; - } else { - res |= 0x2; - } - if (s->iir == 0) { - res |= 0x1; - } - return res; - - case AUX_MU_LCR_REG: - qemu_log_mask(LOG_UNIMP, "%s: AUX_MU_LCR_REG unsupported\n", __func__); - return 0; - - case AUX_MU_MCR_REG: - qemu_log_mask(LOG_UNIMP, "%s: AUX_MU_MCR_REG unsupported\n", __func__); - return 0; - - case AUX_MU_LSR_REG: - res = 0x60; /* tx idle, empty */ - if (s->read_count != 0) { - res |= 0x1; - } - return res; - - case AUX_MU_MSR_REG: - qemu_log_mask(LOG_UNIMP, "%s: AUX_MU_MSR_REG unsupported\n", __func__); - return 0; - - case AUX_MU_SCRATCH: - qemu_log_mask(LOG_UNIMP, "%s: AUX_MU_SCRATCH unsupported\n", __func__); - return 0; - - case AUX_MU_CNTL_REG: - return 0x3; /* tx, rx enabled */ - - case AUX_MU_STAT_REG: - res = 0x30e; /* space in the output buffer, empty tx fifo, idle tx/rx */ - if (s->read_count > 0) { - res |= 0x1; /* data in input buffer */ - assert(s->read_count < BCM2835_AUX_RX_FIFO_LEN); - res |= ((uint32_t)s->read_count) << 16; /* rx fifo fill level */ - } - return res; - - case AUX_MU_BAUD_REG: - qemu_log_mask(LOG_UNIMP, "%s: AUX_MU_BAUD_REG unsupported\n", __func__); - return 0; + case A_AUX_ENABLE: + res = s->reg[R_AUX_ENABLE]; + break; default: qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n", __func__, offset); - return 0; + break; } + trace_bcm2835_aux_read(offset, res); + + return res; } static void bcm2835_aux_write(void *opaque, hwaddr offset, uint64_t value, unsigned size) { - BCM2835AuxState *s = opaque; - unsigned char ch; + BCM2835AuxState *s = BCM2835_AUX(opaque); + trace_bcm2835_aux_write(offset, value); switch (offset) { - case AUX_ENABLES: - if (value != 1) { - qemu_log_mask(LOG_UNIMP, "%s: unsupported attempt to enable SPI " - "or disable UART\n", __func__); + case A_AUX_ENABLE: + if (value <= 1) { + if (aux_enable_supported) { + memory_region_set_enabled( + sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->uart), 0), + value); + } + } else { + qemu_log_mask(LOG_UNIMP, "%s: unsupported attempt to enable SPI:" + " 0x%"PRIx64"\n", + __func__, value); } break; - case AUX_MU_IO_REG: - /* "DLAB bit set means access baudrate register" is NYI */ - ch = value; - /* XXX this blocks entire thread. Rewrite to use - * qemu_chr_fe_write and background I/O callbacks */ - qemu_chr_fe_write_all(&s->chr, &ch, 1); - break; - - case AUX_MU_IER_REG: - /* "DLAB bit set means access baudrate register" is NYI */ - s->ier = value & (TX_INT | RX_INT); - bcm2835_aux_update(s); - break; - - case AUX_MU_IIR_REG: - if (value & 0x2) { - s->read_count = 0; - } - break; - - case AUX_MU_LCR_REG: - qemu_log_mask(LOG_UNIMP, "%s: AUX_MU_LCR_REG unsupported\n", __func__); - break; - - case AUX_MU_MCR_REG: - qemu_log_mask(LOG_UNIMP, "%s: AUX_MU_MCR_REG unsupported\n", __func__); - break; - - case AUX_MU_SCRATCH: - qemu_log_mask(LOG_UNIMP, "%s: AUX_MU_SCRATCH unsupported\n", __func__); - break; - - case AUX_MU_CNTL_REG: - qemu_log_mask(LOG_UNIMP, "%s: AUX_MU_CNTL_REG unsupported\n", __func__); - break; - - case AUX_MU_BAUD_REG: - qemu_log_mask(LOG_UNIMP, "%s: AUX_MU_BAUD_REG unsupported\n", __func__); - break; - default: qemu_log_mask(LOG_GUEST_ERROR, "%s: Bad offset %"HWADDR_PRIx"\n", __func__, offset); @@ -215,35 +94,6 @@ static void bcm2835_aux_write(void *opaque, hwaddr offset, uint64_t value, bcm2835_aux_update(s); } -static int bcm2835_aux_can_receive(void *opaque) -{ - BCM2835AuxState *s = opaque; - - return s->read_count < BCM2835_AUX_RX_FIFO_LEN; -} - -static void bcm2835_aux_put_fifo(void *opaque, uint8_t value) -{ - BCM2835AuxState *s = opaque; - int slot; - - slot = s->read_pos + s->read_count; - if (slot >= BCM2835_AUX_RX_FIFO_LEN) { - slot -= BCM2835_AUX_RX_FIFO_LEN; - } - s->read_fifo[slot] = value; - s->read_count++; - if (s->read_count == BCM2835_AUX_RX_FIFO_LEN) { - /* buffer full */ - } - bcm2835_aux_update(s); -} - -static void bcm2835_aux_receive(void *opaque, const uint8_t *buf, int size) -{ - bcm2835_aux_put_fifo(opaque, *buf); -} - static const MemoryRegionOps bcm2835_aux_ops = { .read = bcm2835_aux_read, .write = bcm2835_aux_write, @@ -254,15 +104,9 @@ static const MemoryRegionOps bcm2835_aux_ops = { static const VMStateDescription vmstate_bcm2835_aux = { .name = TYPE_BCM2835_AUX, - .version_id = 1, - .minimum_version_id = 1, + .version_id = 2, + .minimum_version_id = 2, .fields = (VMStateField[]) { - VMSTATE_UINT8_ARRAY(read_fifo, BCM2835AuxState, - BCM2835_AUX_RX_FIFO_LEN), - VMSTATE_UINT8(read_pos, BCM2835AuxState), - VMSTATE_UINT8(read_count, BCM2835AuxState), - VMSTATE_UINT8(ier, BCM2835AuxState), - VMSTATE_UINT8(iir, BCM2835AuxState), VMSTATE_END_OF_LIST() } }; @@ -276,18 +120,45 @@ static void bcm2835_aux_init(Object *obj) TYPE_BCM2835_AUX, 0x100); sysbus_init_mmio(sbd, &s->iomem); sysbus_init_irq(sbd, &s->irq); + + qdev_init_gpio_in_named(DEVICE(obj), bcm2835_aux_set_irq, "aux-irq", 3); + + sysbus_init_child_obj(obj, "miniuart", &s->uart, sizeof(s->uart), + TYPE_BCM2835_MINIUART); + object_property_add_alias(obj, "chardev", OBJECT(&s->uart), "chardev", + &error_abort); } static void bcm2835_aux_realize(DeviceState *dev, Error **errp) { BCM2835AuxState *s = BCM2835_AUX(dev); + Error *err = NULL; - qemu_chr_fe_set_handlers(&s->chr, bcm2835_aux_can_receive, - bcm2835_aux_receive, NULL, NULL, s, NULL, true); + object_property_set_bool(OBJECT(&s->uart), true, "realized", &err); + if (err) { + error_propagate(errp, err); + return; + } + memory_region_add_subregion(&s->iomem, 0x40, + sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->uart), 0)); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart), 0, + qdev_get_gpio_in_named(dev, "aux-irq", 0)); +} + +static void bcm2835_aux_reset(DeviceState *dev) +{ + BCM2835AuxState *s = BCM2835_AUX(dev); + + s->reg[R_AUX_IRQ] = s->reg[R_AUX_ENABLE] = 0; + + if (aux_enable_supported) { + memory_region_set_enabled( + sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->uart), 0), + false); + } } static Property bcm2835_aux_props[] = { - DEFINE_PROP_CHR("chardev", BCM2835AuxState, chr), DEFINE_PROP_END_OF_LIST(), }; @@ -296,8 +167,9 @@ static void bcm2835_aux_class_init(ObjectClass *oc, void *data) DeviceClass *dc = DEVICE_CLASS(oc); dc->realize = bcm2835_aux_realize; + dc->reset = bcm2835_aux_reset; dc->vmsd = &vmstate_bcm2835_aux; - set_bit(DEVICE_CATEGORY_INPUT, dc->categories); + set_bit(DEVICE_CATEGORY_MISC, dc->categories); dc->props = bcm2835_aux_props; } diff --git a/hw/char/trace-events b/hw/char/trace-events index f1e6dd9918..0c86a907df 100644 --- a/hw/char/trace-events +++ b/hw/char/trace-events @@ -1,5 +1,9 @@ # See docs/devel/tracing.txt for syntax documentation. +# bcm2835_aux.c +bcm2835_aux_read(uint64_t addr, uint32_t value) "read addr 0x%"PRIx64" value 0x%x" +bcm2835_aux_write(uint64_t addr, uint32_t value) "read addr 0x%"PRIx64" value 0x%x" + # bcm2835_miniuart.c bcm2835_miniuart_read(uint64_t addr, uint32_t value) "read addr 0x%"PRIx64" value 0x%x" bcm2835_miniuart_write(uint64_t addr, uint32_t value) "read addr 0x%"PRIx64" value 0x%x" diff --git a/include/hw/char/bcm2835_aux.h b/include/hw/char/bcm2835_aux.h index cdbf7e3e37..a7b3a6ac60 100644 --- a/include/hw/char/bcm2835_aux.h +++ b/include/hw/char/bcm2835_aux.h @@ -9,25 +9,21 @@ #define BCM2835_AUX_H #include "hw/sysbus.h" -#include "chardev/char-fe.h" +#include "hw/char/bcm2835_miniuart.h" #define TYPE_BCM2835_AUX "bcm2835-aux" #define BCM2835_AUX(obj) OBJECT_CHECK(BCM2835AuxState, (obj), TYPE_BCM2835_AUX) -#define BCM2835_AUX_RX_FIFO_LEN 8 - typedef struct { /*< private >*/ SysBusDevice parent_obj; /*< public >*/ MemoryRegion iomem; - CharBackend chr; qemu_irq irq; - uint8_t read_fifo[BCM2835_AUX_RX_FIFO_LEN]; - uint8_t read_pos, read_count; - uint8_t ier, iir; + uint32_t reg[2]; + BCM2835MiniUartState uart; } BCM2835AuxState; #endif From patchwork Mon Oct 7 17:06:46 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= X-Patchwork-Id: 1172915 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=amsat.org Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="m36v3Zb/"; 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[83.42.66.46]) by smtp.gmail.com with ESMTPSA id x5sm14036603wrt.75.2019.10.07.10.06.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Oct 2019 10:06:54 -0700 (PDT) From: =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH 3/3] hw: Move BCM2835 AUX device from hw/char/ to hw/misc/ Date: Mon, 7 Oct 2019 19:06:46 +0200 Message-Id: <20191007170646.14961-4-f4bug@amsat.org> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20191007170646.14961-1-f4bug@amsat.org> References: <20191007170646.14961-1-f4bug@amsat.org> MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::442 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Alistair Francis , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= , Andrew Baumann , qemu-arm@nongnu.org, Paolo Bonzini , Marc-Andre Lureau , =?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" The BCM2835 AUX device is a MUX between one UART block and two SPI blocks. Move it to the hw/misc/ folder. Signed-off-by: Philippe Mathieu-Daudé --- hw/char/Makefile.objs | 1 - hw/char/trace-events | 4 ---- hw/misc/Makefile.objs | 1 + hw/{char => misc}/bcm2835_aux.c | 2 +- hw/misc/trace-events | 4 ++++ include/hw/arm/bcm2835_peripherals.h | 2 +- include/hw/{char => misc}/bcm2835_aux.h | 0 7 files changed, 7 insertions(+), 7 deletions(-) rename hw/{char => misc}/bcm2835_aux.c (99%) rename include/hw/{char => misc}/bcm2835_aux.h (100%) diff --git a/hw/char/Makefile.objs b/hw/char/Makefile.objs index 5bd93bde9f..d6b8ce5e60 100644 --- a/hw/char/Makefile.objs +++ b/hw/char/Makefile.objs @@ -20,7 +20,6 @@ obj-$(CONFIG_SH4) += sh_serial.o obj-$(CONFIG_PSERIES) += spapr_vty.o obj-$(CONFIG_DIGIC) += digic-uart.o obj-$(CONFIG_STM32F2XX_USART) += stm32f2xx_usart.o -obj-$(CONFIG_RASPI) += bcm2835_aux.o common-obj-$(CONFIG_RASPI) += bcm2835_miniuart.o common-obj-$(CONFIG_CMSDK_APB_UART) += cmsdk-apb-uart.o diff --git a/hw/char/trace-events b/hw/char/trace-events index 0c86a907df..f1e6dd9918 100644 --- a/hw/char/trace-events +++ b/hw/char/trace-events @@ -1,9 +1,5 @@ # See docs/devel/tracing.txt for syntax documentation. -# bcm2835_aux.c -bcm2835_aux_read(uint64_t addr, uint32_t value) "read addr 0x%"PRIx64" value 0x%x" -bcm2835_aux_write(uint64_t addr, uint32_t value) "read addr 0x%"PRIx64" value 0x%x" - # bcm2835_miniuart.c bcm2835_miniuart_read(uint64_t addr, uint32_t value) "read addr 0x%"PRIx64" value 0x%x" bcm2835_miniuart_write(uint64_t addr, uint32_t value) "read addr 0x%"PRIx64" value 0x%x" diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs index a150680966..9ffeee7f46 100644 --- a/hw/misc/Makefile.objs +++ b/hw/misc/Makefile.objs @@ -50,6 +50,7 @@ common-obj-$(CONFIG_OMAP) += omap_gpmc.o common-obj-$(CONFIG_OMAP) += omap_l4.o common-obj-$(CONFIG_OMAP) += omap_sdrc.o common-obj-$(CONFIG_OMAP) += omap_tap.o +common-obj-$(CONFIG_RASPI) += bcm2835_aux.o common-obj-$(CONFIG_RASPI) += bcm2835_mbox.o common-obj-$(CONFIG_RASPI) += bcm2835_property.o common-obj-$(CONFIG_RASPI) += bcm2835_rng.o diff --git a/hw/char/bcm2835_aux.c b/hw/misc/bcm2835_aux.c similarity index 99% rename from hw/char/bcm2835_aux.c rename to hw/misc/bcm2835_aux.c index a1ca9741d6..83698e2ece 100644 --- a/hw/char/bcm2835_aux.c +++ b/hw/misc/bcm2835_aux.c @@ -12,7 +12,7 @@ */ #include "qemu/osdep.h" -#include "hw/char/bcm2835_aux.h" +#include "hw/misc/bcm2835_aux.h" #include "hw/irq.h" #include "hw/qdev-properties.h" #include "hw/registerfields.h" diff --git a/hw/misc/trace-events b/hw/misc/trace-events index 74276225f8..0756d58162 100644 --- a/hw/misc/trace-events +++ b/hw/misc/trace-events @@ -1,5 +1,9 @@ # See docs/devel/tracing.txt for syntax documentation. +# bcm2835_aux.c +bcm2835_aux_read(uint64_t addr, uint32_t value) "read addr 0x%"PRIx64" value 0x%x" +bcm2835_aux_write(uint64_t addr, uint32_t value) "read addr 0x%"PRIx64" value 0x%x" + # eccmemctl.c ecc_mem_writel_mer(uint32_t val) "Write memory enable 0x%08x" ecc_mem_writel_mdr(uint32_t val) "Write memory delay 0x%08x" diff --git a/include/hw/arm/bcm2835_peripherals.h b/include/hw/arm/bcm2835_peripherals.h index 6b17f6a382..7aae515d7e 100644 --- a/include/hw/arm/bcm2835_peripherals.h +++ b/include/hw/arm/bcm2835_peripherals.h @@ -13,7 +13,7 @@ #include "hw/sysbus.h" #include "hw/char/pl011.h" -#include "hw/char/bcm2835_aux.h" +#include "hw/misc/bcm2835_aux.h" #include "hw/display/bcm2835_fb.h" #include "hw/dma/bcm2835_dma.h" #include "hw/intc/bcm2835_ic.h" diff --git a/include/hw/char/bcm2835_aux.h b/include/hw/misc/bcm2835_aux.h similarity index 100% rename from include/hw/char/bcm2835_aux.h rename to include/hw/misc/bcm2835_aux.h