From patchwork Wed Oct 2 06:00:21 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 1170466 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=kvm-ppc-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="bbIE3m09"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 46jlqq1ndmz9sQn for ; Wed, 2 Oct 2019 16:00:55 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726933AbfJBGAz (ORCPT ); Wed, 2 Oct 2019 02:00:55 -0400 Received: from mail-pg1-f195.google.com ([209.85.215.195]:37486 "EHLO mail-pg1-f195.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725988AbfJBGAy (ORCPT ); Wed, 2 Oct 2019 02:00:54 -0400 Received: by mail-pg1-f195.google.com with SMTP id c17so11291511pgg.4 for ; Tue, 01 Oct 2019 23:00:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ZX0zfvRtAA562ZIDPi2zpxAIxjmN5v6Crr7qVu5FmrU=; b=bbIE3m09qoM3Nhg1pDfzgXvJ5cycSo8nBFBen9sKa8wWGDwyPG+WzZPsohI9cAqkJD paoyyBM9d55eVjCmxkYDRWy/tW6dpom92Lt+unyZpEKtVSMXlkomB9aMyzGkgDYFepdm CPmnc0oN5POjVmnYFHoPReUAWDrMyZ6nBlD+fZatqRuw1VmBMNR5an09QTApAVplBqie 1pIyNcllNbIYPA4f2+1P1n67UnDuXiYHR001ePXGAqQi4qq3LQqyf58kjEqTTz4vuS8o ezyzV8LIAELSyU3gpP/3TrvgObF7fpFDOS1vd5hLjscDMhqB+51UGqwg2v/BTtZfu+YI Bsbw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ZX0zfvRtAA562ZIDPi2zpxAIxjmN5v6Crr7qVu5FmrU=; b=mxc1nEKZC2KONvls4zwlLUuVca7vh9Pn8jmT3TH64P4BeyNz/Q2tXrtO8vBOO82H24 pYrSAPL6FZ6F5EC5jTNGeCws8Al0Kj9cARHyOpu1LAs0fLciw8/pORCPoIb010awuzw1 75wS7Ur3AdP0QtkPhXrksnUusYQ8rbiGIZnkVR6McQXY7emP7RRQj5St/GQ9NjlYSSv2 X1IdLQrmzAaL2u9bfu3xqVfqTItuycgmk/3NqGSSUQHlQJyaLP78mGx4pINs6hgyt/tS uHQZCai0ekBhGddGgtMWD9R0kBuiZfn9DaMnf6v1nwq7Ah+rwZwBP9YkhecLpg24Rofc 1qBg== X-Gm-Message-State: APjAAAUKlk4BcF2RjHcYHrPWNQS+oFhnyYYCFy8utHGDDBMbsg21R7f3 O+3429GIfYs24II0VlMsCUoVpSMw X-Google-Smtp-Source: APXvYqxpOUJiAWQWLhHKq4Z4wupgehTb+RECvCZtis6VSMWD4sfbNZ7d7WEErWx7KhYsJgQ7GBcWjg== X-Received: by 2002:a62:5441:: with SMTP id i62mr2714468pfb.49.1569996053651; Tue, 01 Oct 2019 23:00:53 -0700 (PDT) Received: from bobo.ozlabs.ibm.com ([122.99.82.10]) by smtp.gmail.com with ESMTPSA id v12sm18660749pgr.31.2019.10.01.23.00.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Oct 2019 23:00:53 -0700 (PDT) From: Nicholas Piggin To: kvm-ppc@vger.kernel.org Cc: Nicholas Piggin , Paul Mackerras Subject: [PATCH v2 1/5] KVM: PPC: Book3S: Define and use SRR1_MSR_BITS Date: Wed, 2 Oct 2019 16:00:21 +1000 Message-Id: <20191002060025.11644-2-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191002060025.11644-1-npiggin@gmail.com> References: <20191002060025.11644-1-npiggin@gmail.com> MIME-Version: 1.0 Sender: kvm-ppc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm-ppc@vger.kernel.org Acked-by: Paul Mackerras Signed-off-by: Nicholas Piggin --- arch/powerpc/include/asm/reg.h | 12 ++++++++++++ arch/powerpc/kvm/book3s.c | 2 +- arch/powerpc/kvm/book3s_hv_nested.c | 2 +- 3 files changed, 14 insertions(+), 2 deletions(-) diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h index b3cbb1136bce..75c7e95a321b 100644 --- a/arch/powerpc/include/asm/reg.h +++ b/arch/powerpc/include/asm/reg.h @@ -748,6 +748,18 @@ #define SPRN_USPRG7 0x107 /* SPRG7 userspace read */ #define SPRN_SRR0 0x01A /* Save/Restore Register 0 */ #define SPRN_SRR1 0x01B /* Save/Restore Register 1 */ + +#ifdef CONFIG_PPC_BOOK3S +/* + * Bits loaded from MSR upon interrupt. + * PPC (64-bit) bits 33-36,42-47 are interrupt dependent, the others are + * loaded from MSR. The exception is that SRESET and MCE do not always load + * bit 62 (RI) from MSR. Don't use PPC_BITMASK for this because 32-bit uses + * it. + */ +#define SRR1_MSR_BITS (~0x783f0000UL) +#endif + #define SRR1_ISI_NOPT 0x40000000 /* ISI: Not found in hash */ #define SRR1_ISI_N_OR_G 0x10000000 /* ISI: Access is no-exec or G */ #define SRR1_ISI_PROT 0x08000000 /* ISI: Other protection fault */ diff --git a/arch/powerpc/kvm/book3s.c b/arch/powerpc/kvm/book3s.c index d7fcdfa7fee4..38466df81d33 100644 --- a/arch/powerpc/kvm/book3s.c +++ b/arch/powerpc/kvm/book3s.c @@ -136,7 +136,7 @@ void kvmppc_inject_interrupt(struct kvm_vcpu *vcpu, int vec, u64 flags) { kvmppc_unfixup_split_real(vcpu); kvmppc_set_srr0(vcpu, kvmppc_get_pc(vcpu)); - kvmppc_set_srr1(vcpu, (kvmppc_get_msr(vcpu) & ~0x783f0000ul) | flags); + kvmppc_set_srr1(vcpu, (kvmppc_get_msr(vcpu) & SRR1_MSR_BITS) | flags); kvmppc_set_pc(vcpu, kvmppc_interrupt_offset(vcpu) + vec); vcpu->arch.mmu.reset_msr(vcpu); } diff --git a/arch/powerpc/kvm/book3s_hv_nested.c b/arch/powerpc/kvm/book3s_hv_nested.c index cdf30c6eaf54..dc97e5be76f6 100644 --- a/arch/powerpc/kvm/book3s_hv_nested.c +++ b/arch/powerpc/kvm/book3s_hv_nested.c @@ -1186,7 +1186,7 @@ static int kvmhv_translate_addr_nested(struct kvm_vcpu *vcpu, forward_to_l1: vcpu->arch.fault_dsisr = flags; if (vcpu->arch.trap == BOOK3S_INTERRUPT_H_INST_STORAGE) { - vcpu->arch.shregs.msr &= ~0x783f0000ul; + vcpu->arch.shregs.msr &= SRR1_MSR_BITS; vcpu->arch.shregs.msr |= flags; } return RESUME_HOST; From patchwork Wed Oct 2 06:00:22 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 1170467 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=kvm-ppc-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="TEdRdGef"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 46jlqs3gYdz9sR6 for ; Wed, 2 Oct 2019 16:00:57 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727181AbfJBGA5 (ORCPT ); Wed, 2 Oct 2019 02:00:57 -0400 Received: from mail-pf1-f196.google.com ([209.85.210.196]:33428 "EHLO mail-pf1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725988AbfJBGA4 (ORCPT ); Wed, 2 Oct 2019 02:00:56 -0400 Received: by mail-pf1-f196.google.com with SMTP id q10so9764122pfl.0 for ; Tue, 01 Oct 2019 23:00:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=B5GgFrZHZTu1T2sX7rlhrRAxSELLepdKkHJkIjcDvCQ=; b=TEdRdGef+tBZ4GyjlHFNCF9ltAJ9Pby1U6Y37DDBNIgOrW8if0PChAYd6VlOcJqBta ARlzNCsKHnL1GLFGkSrwEVCxpAOlBuDEx1OGYi2lNT9OsyQGBeEnX34YtNOAnhA0atrH buz8EPMN3x0gbthb/1dl4mibjtJCvfgGJ9ig0nqPi7ZEqWTssU5TOKPP2NxdwJPZBWFH Gcc0wi6a4TmhszmR6MiswF5/3QtAxvgPCIF38SKEJMpTwHi/aXjMTzsX1wCKK8UPhoxj Nj6ShpRhc7ChIUc6H1tVr5unDytm/Fnq5zqSEESarCS2yIEXaDG5BiV4I7FXX8WtNc4q Xk1g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=B5GgFrZHZTu1T2sX7rlhrRAxSELLepdKkHJkIjcDvCQ=; b=JkHm/a2B/Xa/w1rWAo2GiqgYad5vK+96bnFOmuCFWXd0s+eHcC7O3Fr8teI4XTedz9 H1TP8PUNAuEYJd1euVh0tds9plMe7W86kj4vO3sRKuM5KjmIP9qxr+sSo2UjFwjv2DXE vdXLeHUSQ5sJuA+lcqLr5mmcdeO4PCtuH1X5om3Fg7b52ZsdwxKxQIAhvpnnb7ZTll3B 5qq5oYWlYaYtREBpFkjFX1SxrNNQ18jt61oimueFEkNg6WHnT3Ej/AHsvyXLdgeh/ZC0 zAVXd3BImV7hUsYNJyn+Ytzonjz+puUMPcmfNo1R1y4X118aFXytZUGqoD9sAwGoVWtc eYkg== X-Gm-Message-State: APjAAAUo9PKGSUr4TsdVPgv1rt/r7ugdcyqcDoioFhqkEFPxN/VC6y4j BoGE6uUPd/DaTCtIfrs40fnrtdZC X-Google-Smtp-Source: APXvYqyBEekzpDOdjjuoZIumYX9PleQAQPlGOSBZfHg+n9sOB+M0qDcnOpb7Os4hHztQzTNLa5DRpA== X-Received: by 2002:aa7:9358:: with SMTP id 24mr2545714pfn.241.1569996055733; Tue, 01 Oct 2019 23:00:55 -0700 (PDT) Received: from bobo.ozlabs.ibm.com ([122.99.82.10]) by smtp.gmail.com with ESMTPSA id v12sm18660749pgr.31.2019.10.01.23.00.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Oct 2019 23:00:55 -0700 (PDT) From: Nicholas Piggin To: kvm-ppc@vger.kernel.org Cc: Nicholas Piggin Subject: [PATCH v2 2/5] KVM: PPC: Book3S: Replace reset_msr mmu op with inject_interrupt arch op Date: Wed, 2 Oct 2019 16:00:22 +1000 Message-Id: <20191002060025.11644-3-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191002060025.11644-1-npiggin@gmail.com> References: <20191002060025.11644-1-npiggin@gmail.com> MIME-Version: 1.0 Sender: kvm-ppc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm-ppc@vger.kernel.org reset_msr sets the MSR for interrupt injection, but it's cleaner and more flexible to provide a single op to set both MSR and PC for the interrupt. Signed-off-by: Nicholas Piggin --- arch/powerpc/include/asm/kvm_host.h | 1 - arch/powerpc/include/asm/kvm_ppc.h | 1 + arch/powerpc/kvm/book3s.c | 27 +------------------ arch/powerpc/kvm/book3s_32_mmu.c | 6 ----- arch/powerpc/kvm/book3s_64_mmu.c | 15 ----------- arch/powerpc/kvm/book3s_64_mmu_hv.c | 13 ---------- arch/powerpc/kvm/book3s_hv.c | 22 ++++++++++++++++ arch/powerpc/kvm/book3s_pr.c | 40 ++++++++++++++++++++++++++++- 8 files changed, 63 insertions(+), 62 deletions(-) diff --git a/arch/powerpc/include/asm/kvm_host.h b/arch/powerpc/include/asm/kvm_host.h index 6fe6ad64cba5..4273e799203d 100644 --- a/arch/powerpc/include/asm/kvm_host.h +++ b/arch/powerpc/include/asm/kvm_host.h @@ -401,7 +401,6 @@ struct kvmppc_mmu { u32 (*mfsrin)(struct kvm_vcpu *vcpu, u32 srnum); int (*xlate)(struct kvm_vcpu *vcpu, gva_t eaddr, struct kvmppc_pte *pte, bool data, bool iswrite); - void (*reset_msr)(struct kvm_vcpu *vcpu); void (*tlbie)(struct kvm_vcpu *vcpu, ulong addr, bool large); int (*esid_to_vsid)(struct kvm_vcpu *vcpu, ulong esid, u64 *vsid); u64 (*ea_to_vp)(struct kvm_vcpu *vcpu, gva_t eaddr, bool data); diff --git a/arch/powerpc/include/asm/kvm_ppc.h b/arch/powerpc/include/asm/kvm_ppc.h index ee62776e5433..d63f649fe713 100644 --- a/arch/powerpc/include/asm/kvm_ppc.h +++ b/arch/powerpc/include/asm/kvm_ppc.h @@ -271,6 +271,7 @@ struct kvmppc_ops { union kvmppc_one_reg *val); void (*vcpu_load)(struct kvm_vcpu *vcpu, int cpu); void (*vcpu_put)(struct kvm_vcpu *vcpu); + void (*inject_interrupt)(struct kvm_vcpu *vcpu, int vec, u64 srr1_flags); void (*set_msr)(struct kvm_vcpu *vcpu, u64 msr); int (*vcpu_run)(struct kvm_run *run, struct kvm_vcpu *vcpu); struct kvm_vcpu *(*vcpu_create)(struct kvm *kvm, unsigned int id); diff --git a/arch/powerpc/kvm/book3s.c b/arch/powerpc/kvm/book3s.c index 38466df81d33..27050cbf609b 100644 --- a/arch/powerpc/kvm/book3s.c +++ b/arch/powerpc/kvm/book3s.c @@ -74,27 +74,6 @@ struct kvm_stats_debugfs_item debugfs_entries[] = { { NULL } }; -void kvmppc_unfixup_split_real(struct kvm_vcpu *vcpu) -{ - if (vcpu->arch.hflags & BOOK3S_HFLAG_SPLIT_HACK) { - ulong pc = kvmppc_get_pc(vcpu); - ulong lr = kvmppc_get_lr(vcpu); - if ((pc & SPLIT_HACK_MASK) == SPLIT_HACK_OFFS) - kvmppc_set_pc(vcpu, pc & ~SPLIT_HACK_MASK); - if ((lr & SPLIT_HACK_MASK) == SPLIT_HACK_OFFS) - kvmppc_set_lr(vcpu, lr & ~SPLIT_HACK_MASK); - vcpu->arch.hflags &= ~BOOK3S_HFLAG_SPLIT_HACK; - } -} -EXPORT_SYMBOL_GPL(kvmppc_unfixup_split_real); - -static inline unsigned long kvmppc_interrupt_offset(struct kvm_vcpu *vcpu) -{ - if (!is_kvmppc_hv_enabled(vcpu->kvm)) - return to_book3s(vcpu)->hior; - return 0; -} - static inline void kvmppc_update_int_pending(struct kvm_vcpu *vcpu, unsigned long pending_now, unsigned long old_pending) { @@ -134,11 +113,7 @@ static inline bool kvmppc_critical_section(struct kvm_vcpu *vcpu) void kvmppc_inject_interrupt(struct kvm_vcpu *vcpu, int vec, u64 flags) { - kvmppc_unfixup_split_real(vcpu); - kvmppc_set_srr0(vcpu, kvmppc_get_pc(vcpu)); - kvmppc_set_srr1(vcpu, (kvmppc_get_msr(vcpu) & SRR1_MSR_BITS) | flags); - kvmppc_set_pc(vcpu, kvmppc_interrupt_offset(vcpu) + vec); - vcpu->arch.mmu.reset_msr(vcpu); + vcpu->kvm->arch.kvm_ops->inject_interrupt(vcpu, vec, flags); } static int kvmppc_book3s_vec2irqprio(unsigned int vec) diff --git a/arch/powerpc/kvm/book3s_32_mmu.c b/arch/powerpc/kvm/book3s_32_mmu.c index 18f244aad7aa..f21e73492ce3 100644 --- a/arch/powerpc/kvm/book3s_32_mmu.c +++ b/arch/powerpc/kvm/book3s_32_mmu.c @@ -90,11 +90,6 @@ static u64 kvmppc_mmu_book3s_32_ea_to_vp(struct kvm_vcpu *vcpu, gva_t eaddr, return (((u64)eaddr >> 12) & 0xffff) | (vsid << 16); } -static void kvmppc_mmu_book3s_32_reset_msr(struct kvm_vcpu *vcpu) -{ - kvmppc_set_msr(vcpu, 0); -} - static hva_t kvmppc_mmu_book3s_32_get_pteg(struct kvm_vcpu *vcpu, u32 sre, gva_t eaddr, bool primary) @@ -406,7 +401,6 @@ void kvmppc_mmu_book3s_32_init(struct kvm_vcpu *vcpu) mmu->mtsrin = kvmppc_mmu_book3s_32_mtsrin; mmu->mfsrin = kvmppc_mmu_book3s_32_mfsrin; mmu->xlate = kvmppc_mmu_book3s_32_xlate; - mmu->reset_msr = kvmppc_mmu_book3s_32_reset_msr; mmu->tlbie = kvmppc_mmu_book3s_32_tlbie; mmu->esid_to_vsid = kvmppc_mmu_book3s_32_esid_to_vsid; mmu->ea_to_vp = kvmppc_mmu_book3s_32_ea_to_vp; diff --git a/arch/powerpc/kvm/book3s_64_mmu.c b/arch/powerpc/kvm/book3s_64_mmu.c index 5f63a5f7f24f..599133256a95 100644 --- a/arch/powerpc/kvm/book3s_64_mmu.c +++ b/arch/powerpc/kvm/book3s_64_mmu.c @@ -24,20 +24,6 @@ #define dprintk(X...) do { } while(0) #endif -static void kvmppc_mmu_book3s_64_reset_msr(struct kvm_vcpu *vcpu) -{ - unsigned long msr = vcpu->arch.intr_msr; - unsigned long cur_msr = kvmppc_get_msr(vcpu); - - /* If transactional, change to suspend mode on IRQ delivery */ - if (MSR_TM_TRANSACTIONAL(cur_msr)) - msr |= MSR_TS_S; - else - msr |= cur_msr & MSR_TS_MASK; - - kvmppc_set_msr(vcpu, msr); -} - static struct kvmppc_slb *kvmppc_mmu_book3s_64_find_slbe( struct kvm_vcpu *vcpu, gva_t eaddr) @@ -676,7 +662,6 @@ void kvmppc_mmu_book3s_64_init(struct kvm_vcpu *vcpu) mmu->slbie = kvmppc_mmu_book3s_64_slbie; mmu->slbia = kvmppc_mmu_book3s_64_slbia; mmu->xlate = kvmppc_mmu_book3s_64_xlate; - mmu->reset_msr = kvmppc_mmu_book3s_64_reset_msr; mmu->tlbie = kvmppc_mmu_book3s_64_tlbie; mmu->esid_to_vsid = kvmppc_mmu_book3s_64_esid_to_vsid; mmu->ea_to_vp = kvmppc_mmu_book3s_64_ea_to_vp; diff --git a/arch/powerpc/kvm/book3s_64_mmu_hv.c b/arch/powerpc/kvm/book3s_64_mmu_hv.c index 9a75f0e1933b..7cf80567ccaf 100644 --- a/arch/powerpc/kvm/book3s_64_mmu_hv.c +++ b/arch/powerpc/kvm/book3s_64_mmu_hv.c @@ -275,18 +275,6 @@ int kvmppc_mmu_hv_init(void) return 0; } -static void kvmppc_mmu_book3s_64_hv_reset_msr(struct kvm_vcpu *vcpu) -{ - unsigned long msr = vcpu->arch.intr_msr; - - /* If transactional, change to suspend mode on IRQ delivery */ - if (MSR_TM_TRANSACTIONAL(vcpu->arch.shregs.msr)) - msr |= MSR_TS_S; - else - msr |= vcpu->arch.shregs.msr & MSR_TS_MASK; - kvmppc_set_msr(vcpu, msr); -} - static long kvmppc_virtmode_do_h_enter(struct kvm *kvm, unsigned long flags, long pte_index, unsigned long pteh, unsigned long ptel, unsigned long *pte_idx_ret) @@ -2161,7 +2149,6 @@ void kvmppc_mmu_book3s_hv_init(struct kvm_vcpu *vcpu) vcpu->arch.slb_nr = 32; /* POWER7/POWER8 */ mmu->xlate = kvmppc_mmu_book3s_64_hv_xlate; - mmu->reset_msr = kvmppc_mmu_book3s_64_hv_reset_msr; vcpu->arch.hflags |= BOOK3S_HFLAG_SLB; } diff --git a/arch/powerpc/kvm/book3s_hv.c b/arch/powerpc/kvm/book3s_hv.c index 709cf1fd4cf4..94a0a9911b27 100644 --- a/arch/powerpc/kvm/book3s_hv.c +++ b/arch/powerpc/kvm/book3s_hv.c @@ -338,6 +338,27 @@ static void kvmppc_core_vcpu_put_hv(struct kvm_vcpu *vcpu) spin_unlock_irqrestore(&vcpu->arch.tbacct_lock, flags); } +static void kvmppc_inject_interrupt_hv(struct kvm_vcpu *vcpu, int vec, u64 srr1_flags) +{ + unsigned long msr, pc, new_msr, new_pc; + + msr = kvmppc_get_msr(vcpu); + pc = kvmppc_get_pc(vcpu); + new_msr = vcpu->arch.intr_msr; + new_pc = vec; + + /* If transactional, change to suspend mode on IRQ delivery */ + if (MSR_TM_TRANSACTIONAL(msr)) + new_msr |= MSR_TS_S; + else + new_msr |= msr & MSR_TS_MASK; + + kvmppc_set_srr0(vcpu, pc); + kvmppc_set_srr1(vcpu, (msr & SRR1_MSR_BITS) | srr1_flags); + kvmppc_set_pc(vcpu, new_pc); + kvmppc_set_msr(vcpu, new_msr); +} + static void kvmppc_set_msr_hv(struct kvm_vcpu *vcpu, u64 msr) { /* @@ -5401,6 +5422,7 @@ static struct kvmppc_ops kvm_ops_hv = { .set_one_reg = kvmppc_set_one_reg_hv, .vcpu_load = kvmppc_core_vcpu_load_hv, .vcpu_put = kvmppc_core_vcpu_put_hv, + .inject_interrupt = kvmppc_inject_interrupt_hv, .set_msr = kvmppc_set_msr_hv, .vcpu_run = kvmppc_vcpu_run_hv, .vcpu_create = kvmppc_core_vcpu_create_hv, diff --git a/arch/powerpc/kvm/book3s_pr.c b/arch/powerpc/kvm/book3s_pr.c index cc65af8fe6f7..ce4fcf76e53e 100644 --- a/arch/powerpc/kvm/book3s_pr.c +++ b/arch/powerpc/kvm/book3s_pr.c @@ -90,7 +90,43 @@ static void kvmppc_fixup_split_real(struct kvm_vcpu *vcpu) kvmppc_set_pc(vcpu, pc | SPLIT_HACK_OFFS); } -void kvmppc_unfixup_split_real(struct kvm_vcpu *vcpu); +static void kvmppc_unfixup_split_real(struct kvm_vcpu *vcpu) +{ + if (vcpu->arch.hflags & BOOK3S_HFLAG_SPLIT_HACK) { + ulong pc = kvmppc_get_pc(vcpu); + ulong lr = kvmppc_get_lr(vcpu); + if ((pc & SPLIT_HACK_MASK) == SPLIT_HACK_OFFS) + kvmppc_set_pc(vcpu, pc & ~SPLIT_HACK_MASK); + if ((lr & SPLIT_HACK_MASK) == SPLIT_HACK_OFFS) + kvmppc_set_lr(vcpu, lr & ~SPLIT_HACK_MASK); + vcpu->arch.hflags &= ~BOOK3S_HFLAG_SPLIT_HACK; + } +} + +static void kvmppc_inject_interrupt_pr(struct kvm_vcpu *vcpu, int vec, u64 srr1_flags) +{ + unsigned long msr, pc, new_msr, new_pc; + + kvmppc_unfixup_split_real(vcpu); + + msr = kvmppc_get_msr(vcpu); + pc = kvmppc_get_pc(vcpu); + new_msr = vcpu->arch.intr_msr; + new_pc = to_book3s(vcpu)->hior + vec; + +#ifdef CONFIG_PPC_BOOK3S_64 + /* If transactional, change to suspend mode on IRQ delivery */ + if (MSR_TM_TRANSACTIONAL(msr)) + new_msr |= MSR_TS_S; + else + new_msr |= msr & MSR_TS_MASK; +#endif + + kvmppc_set_srr0(vcpu, pc); + kvmppc_set_srr1(vcpu, (msr & SRR1_MSR_BITS) | srr1_flags); + kvmppc_set_pc(vcpu, new_pc); + kvmppc_set_msr(vcpu, new_msr); +} static void kvmppc_core_vcpu_load_pr(struct kvm_vcpu *vcpu, int cpu) { @@ -1761,6 +1797,7 @@ static struct kvm_vcpu *kvmppc_core_vcpu_create_pr(struct kvm *kvm, #else /* default to book3s_32 (750) */ vcpu->arch.pvr = 0x84202; + vcpu->arch.intr_msr = 0; #endif kvmppc_set_pvr_pr(vcpu, vcpu->arch.pvr); vcpu->arch.slb_nr = 64; @@ -2058,6 +2095,7 @@ static struct kvmppc_ops kvm_ops_pr = { .set_one_reg = kvmppc_set_one_reg_pr, .vcpu_load = kvmppc_core_vcpu_load_pr, .vcpu_put = kvmppc_core_vcpu_put_pr, + .inject_interrupt = kvmppc_inject_interrupt_pr, .set_msr = kvmppc_set_msr_pr, .vcpu_run = kvmppc_vcpu_run_pr, .vcpu_create = kvmppc_core_vcpu_create_pr, From patchwork Wed Oct 2 06:00:23 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 1170468 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=kvm-ppc-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="pcEV5/FQ"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 46jlqw2v30z9sR1 for ; Wed, 2 Oct 2019 16:01:00 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1725988AbfJBGA7 (ORCPT ); Wed, 2 Oct 2019 02:00:59 -0400 Received: from mail-pl1-f181.google.com ([209.85.214.181]:42023 "EHLO mail-pl1-f181.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727209AbfJBGA7 (ORCPT ); Wed, 2 Oct 2019 02:00:59 -0400 Received: by mail-pl1-f181.google.com with SMTP id e5so6650343pls.9 for ; Tue, 01 Oct 2019 23:00:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=CLrNTstP2vuMPY1gkgT7U4JkTKWsj3htw1ad+yH6Y2s=; b=pcEV5/FQg2oXJGDbEUMbzZLBAjJeCYvbOzrDx0EXvRGT3u5YPw5Rqf1Pi46gRqsICe LnMo9xEsuIUOPwEmXJZU1kSYf8dRAQ4F7Bje0iHGhEz9g1N2JWvxHsZb5/aQOkTSNfhA jsdnrMpXtKPtcmHbgKFDKaLknRIVyL0Gj4qiyg7pPBZLzBTg00V/LoJ+cwdaEPwIJObp HIYxOHkMRvw4FfXWHqSkG4ch6bnQDrVmuNMYKFWjAI7cTlDp+xXje316/qXVVZw0nRok mVmPVXKaLXFBwW7ims52dJacz3J0vipKWQ+4Gvf58e5OIVqhdeggDkrtdyjCRt2Am0Wd 8Gfw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=CLrNTstP2vuMPY1gkgT7U4JkTKWsj3htw1ad+yH6Y2s=; b=EL1pisrhGhiBuhzYF/GPZpyFeiczbXwREwBbqNNlr3rX869OhPFDB8Xc7KPoS98PIz rQDJbD8gSSgELFqbhzHvJjIVBY5ceuKYYEt/E1Vw8gLL+LjsloRDukTIa1VzYVPlKihT 0O7RnxOiCE0HpboFpqQ+NEJcljT2yx2bV/hyfjIvpVVS2+rlGUYLABlWyPtapOE/jekJ D9PVovkr586mkJDuR5Xr/7scJAf2vMJOXXv6ghLkxadkErROi8jW3KSICYM8uImcoATE 0ICEKmF1O++PiU8tt+FobrfG4Fs1TUdz/MwbxuHskvrzFaTGD8YSqgkgs/505B1wuYuh +WHw== X-Gm-Message-State: APjAAAW7HtTh/BEh5Q5K0Biqo955UHGUNI1faO2pzzQU5ka+doS5yeAb i2Y2fxnh3YavYR8z1OqowRX7SIT3 X-Google-Smtp-Source: APXvYqxelb/cjDI/iwbV1QThhJSfRVGFhd+9ccRt2HXhQatYS+4vBIoB2DKf4EC8Gn79S+belx1u2A== X-Received: by 2002:a17:902:bc47:: with SMTP id t7mr1823637plz.269.1569996057716; Tue, 01 Oct 2019 23:00:57 -0700 (PDT) Received: from bobo.ozlabs.ibm.com ([122.99.82.10]) by smtp.gmail.com with ESMTPSA id v12sm18660749pgr.31.2019.10.01.23.00.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Oct 2019 23:00:57 -0700 (PDT) From: Nicholas Piggin To: kvm-ppc@vger.kernel.org Cc: Nicholas Piggin Subject: [PATCH v2 3/5] KVM: PPC: Book3S HV: Reuse kvmppc_inject_interrupt for async guest delivery Date: Wed, 2 Oct 2019 16:00:23 +1000 Message-Id: <20191002060025.11644-4-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191002060025.11644-1-npiggin@gmail.com> References: <20191002060025.11644-1-npiggin@gmail.com> MIME-Version: 1.0 Sender: kvm-ppc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm-ppc@vger.kernel.org This consolidates the HV interrupt delivery logic into one place. Signed-off-by: Nicholas Piggin --- arch/powerpc/kvm/book3s.h | 3 ++ arch/powerpc/kvm/book3s_hv.c | 43 ------------------ arch/powerpc/kvm/book3s_hv_builtin.c | 67 ++++++++++++++++++++++------ 3 files changed, 56 insertions(+), 57 deletions(-) diff --git a/arch/powerpc/kvm/book3s.h b/arch/powerpc/kvm/book3s.h index 2ef1311a2a13..3a4613985949 100644 --- a/arch/powerpc/kvm/book3s.h +++ b/arch/powerpc/kvm/book3s.h @@ -32,4 +32,7 @@ extern void kvmppc_emulate_tabort(struct kvm_vcpu *vcpu, int ra_val); static inline void kvmppc_emulate_tabort(struct kvm_vcpu *vcpu, int ra_val) {} #endif +extern void kvmppc_set_msr_hv(struct kvm_vcpu *vcpu, u64 msr); +extern void kvmppc_inject_interrupt_hv(struct kvm_vcpu *vcpu, int vec, u64 srr1_flags); + #endif diff --git a/arch/powerpc/kvm/book3s_hv.c b/arch/powerpc/kvm/book3s_hv.c index 94a0a9911b27..c340d416dce3 100644 --- a/arch/powerpc/kvm/book3s_hv.c +++ b/arch/powerpc/kvm/book3s_hv.c @@ -133,7 +133,6 @@ static inline bool nesting_enabled(struct kvm *kvm) /* If set, the threads on each CPU core have to be in the same MMU mode */ static bool no_mixing_hpt_and_radix; -static void kvmppc_end_cede(struct kvm_vcpu *vcpu); static int kvmppc_hv_setup_htab_rma(struct kvm_vcpu *vcpu); /* @@ -338,39 +337,6 @@ static void kvmppc_core_vcpu_put_hv(struct kvm_vcpu *vcpu) spin_unlock_irqrestore(&vcpu->arch.tbacct_lock, flags); } -static void kvmppc_inject_interrupt_hv(struct kvm_vcpu *vcpu, int vec, u64 srr1_flags) -{ - unsigned long msr, pc, new_msr, new_pc; - - msr = kvmppc_get_msr(vcpu); - pc = kvmppc_get_pc(vcpu); - new_msr = vcpu->arch.intr_msr; - new_pc = vec; - - /* If transactional, change to suspend mode on IRQ delivery */ - if (MSR_TM_TRANSACTIONAL(msr)) - new_msr |= MSR_TS_S; - else - new_msr |= msr & MSR_TS_MASK; - - kvmppc_set_srr0(vcpu, pc); - kvmppc_set_srr1(vcpu, (msr & SRR1_MSR_BITS) | srr1_flags); - kvmppc_set_pc(vcpu, new_pc); - kvmppc_set_msr(vcpu, new_msr); -} - -static void kvmppc_set_msr_hv(struct kvm_vcpu *vcpu, u64 msr) -{ - /* - * Check for illegal transactional state bit combination - * and if we find it, force the TS field to a safe state. - */ - if ((msr & MSR_TS_MASK) == MSR_TS_MASK) - msr &= ~MSR_TS_MASK; - vcpu->arch.shregs.msr = msr; - kvmppc_end_cede(vcpu); -} - static void kvmppc_set_pvr_hv(struct kvm_vcpu *vcpu, u32 pvr) { vcpu->arch.pvr = pvr; @@ -2475,15 +2441,6 @@ static void kvmppc_set_timer(struct kvm_vcpu *vcpu) vcpu->arch.timer_running = 1; } -static void kvmppc_end_cede(struct kvm_vcpu *vcpu) -{ - vcpu->arch.ceded = 0; - if (vcpu->arch.timer_running) { - hrtimer_try_to_cancel(&vcpu->arch.dec_timer); - vcpu->arch.timer_running = 0; - } -} - extern int __kvmppc_vcore_entry(void); static void kvmppc_remove_runnable(struct kvmppc_vcore *vc, diff --git a/arch/powerpc/kvm/book3s_hv_builtin.c b/arch/powerpc/kvm/book3s_hv_builtin.c index 7c1909657b55..068bee941a71 100644 --- a/arch/powerpc/kvm/book3s_hv_builtin.c +++ b/arch/powerpc/kvm/book3s_hv_builtin.c @@ -755,6 +755,56 @@ void kvmhv_p9_restore_lpcr(struct kvm_split_mode *sip) local_paca->kvm_hstate.kvm_split_mode = NULL; } +static void kvmppc_end_cede(struct kvm_vcpu *vcpu) +{ + vcpu->arch.ceded = 0; + if (vcpu->arch.timer_running) { + hrtimer_try_to_cancel(&vcpu->arch.dec_timer); + vcpu->arch.timer_running = 0; + } +} + +void kvmppc_set_msr_hv(struct kvm_vcpu *vcpu, u64 msr) +{ + /* + * Check for illegal transactional state bit combination + * and if we find it, force the TS field to a safe state. + */ + if ((msr & MSR_TS_MASK) == MSR_TS_MASK) + msr &= ~MSR_TS_MASK; + vcpu->arch.shregs.msr = msr; + kvmppc_end_cede(vcpu); +} +EXPORT_SYMBOL_GPL(kvmppc_set_msr_hv); + +static void inject_interrupt(struct kvm_vcpu *vcpu, int vec, u64 srr1_flags) +{ + unsigned long msr, pc, new_msr, new_pc; + + msr = kvmppc_get_msr(vcpu); + pc = kvmppc_get_pc(vcpu); + new_msr = vcpu->arch.intr_msr; + new_pc = vec; + + /* If transactional, change to suspend mode on IRQ delivery */ + if (MSR_TM_TRANSACTIONAL(msr)) + new_msr |= MSR_TS_S; + else + new_msr |= msr & MSR_TS_MASK; + + kvmppc_set_srr0(vcpu, pc); + kvmppc_set_srr1(vcpu, (msr & SRR1_MSR_BITS) | srr1_flags); + kvmppc_set_pc(vcpu, new_pc); + vcpu->arch.shregs.msr = new_msr; +} + +void kvmppc_inject_interrupt_hv(struct kvm_vcpu *vcpu, int vec, u64 srr1_flags) +{ + inject_interrupt(vcpu, vec, srr1_flags); + kvmppc_end_cede(vcpu); +} +EXPORT_SYMBOL_GPL(kvmppc_inject_interrupt_hv); + /* * Is there a PRIV_DOORBELL pending for the guest (on POWER9)? * Can we inject a Decrementer or a External interrupt? @@ -762,7 +812,6 @@ void kvmhv_p9_restore_lpcr(struct kvm_split_mode *sip) void kvmppc_guest_entry_inject_int(struct kvm_vcpu *vcpu) { int ext; - unsigned long vec = 0; unsigned long lpcr; /* Insert EXTERNAL bit into LPCR at the MER bit position */ @@ -774,26 +823,16 @@ void kvmppc_guest_entry_inject_int(struct kvm_vcpu *vcpu) if (vcpu->arch.shregs.msr & MSR_EE) { if (ext) { - vec = BOOK3S_INTERRUPT_EXTERNAL; + inject_interrupt(vcpu, BOOK3S_INTERRUPT_EXTERNAL, 0); } else { long int dec = mfspr(SPRN_DEC); if (!(lpcr & LPCR_LD)) dec = (int) dec; if (dec < 0) - vec = BOOK3S_INTERRUPT_DECREMENTER; + inject_interrupt(vcpu, + BOOK3S_INTERRUPT_DECREMENTER, 0); } } - if (vec) { - unsigned long msr, old_msr = vcpu->arch.shregs.msr; - - kvmppc_set_srr0(vcpu, kvmppc_get_pc(vcpu)); - kvmppc_set_srr1(vcpu, old_msr); - kvmppc_set_pc(vcpu, vec); - msr = vcpu->arch.intr_msr; - if (MSR_TM_ACTIVE(old_msr)) - msr |= MSR_TS_S; - vcpu->arch.shregs.msr = msr; - } if (vcpu->arch.doorbell_request) { mtspr(SPRN_DPDES, 1); From patchwork Wed Oct 2 06:00:24 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 1170469 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=kvm-ppc-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="mSEzN+94"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 46jlqx5LFvz9sR6 for ; Wed, 2 Oct 2019 16:01:01 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727209AbfJBGBA (ORCPT ); Wed, 2 Oct 2019 02:01:00 -0400 Received: from mail-pg1-f196.google.com ([209.85.215.196]:33916 "EHLO mail-pg1-f196.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726538AbfJBGBA (ORCPT ); Wed, 2 Oct 2019 02:01:00 -0400 Received: by mail-pg1-f196.google.com with SMTP id y35so11300861pgl.1 for ; Tue, 01 Oct 2019 23:01:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=wGkCziIraBf0K2OQ69gCFDuWSmrxe04DD64QjeXrGeY=; b=mSEzN+94Y5U0W68FCr/mdoQYCuMHkMAU6wsSkV+sT2ZU9sYNKtVKR+E+ZBIrClwP6i /moQAnqL8ePsHcW94ijKZ+kNZD2lJiKWiKnV2eaVvTQtjeWBYmIDXvzSiUZizlvaxJm/ s470+l+QlAutrLqbZW9QYBRfn4e/1Ndg0otr5GcuOUAvnP2UZVe+qumfK0+wDBKkpoaM cNLpwpnZ3bgVpcN6gEPRKb1MmuVG/WIwlLxarN2H7+znJ+x8ImJB7WY5OXiIbhOc2snW zZDYhsO8EMWQkDxh9/CKRQHCPIZH56hSTz+uR+MRVaX4o5LIstxo6/7s5O8b1WoyP832 Lg0Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=wGkCziIraBf0K2OQ69gCFDuWSmrxe04DD64QjeXrGeY=; b=d5dyREoEkig2B/OdQTYZ7jD6UhSXEmYHFPf4+mq1ctEKpLh7lcLkujr/eneHxvdFj7 nkiqowQHGfc0Mh0OoaTHPiBlA66GJDYIzk5QC/TQ4kaYLj1JqKQwnnfVL3LL58Q9Iw2d qx33C5GZwY+KnTFdNyct1MmFXrB5TZ9KKRcXSC/Es9TmqrEuRy/9yflStp/RUofYy4Qb BZjo2WVuLJZJ977Osftj0i+TFpkayrA/cDf586VZalJ+/F7ynrbGTF4aGFGhP+59FdfA dWHhyK7Jo7HQQ/qiKVwNeiTBxnxIAN71oVUrAz/94V8UBhNjQaSrQR1lVFJnog/LniTN 2hWA== X-Gm-Message-State: APjAAAWhoU4joTtBWV3JFSwg7olQoTevI0Kcps8zdVsP2cXQ29Yd58Mw BIJcNZ8PO5EDZYyxILgLnIEJD4CY X-Google-Smtp-Source: APXvYqzUk96RZmeSqmbaXBWxPVxoeHdPLYp7RMicR/WOJZdbJjU8AiIPNI4vu0i4WgMeqGeblQU5lg== X-Received: by 2002:a63:f20d:: with SMTP id v13mr1884584pgh.175.1569996059556; Tue, 01 Oct 2019 23:00:59 -0700 (PDT) Received: from bobo.ozlabs.ibm.com ([122.99.82.10]) by smtp.gmail.com with ESMTPSA id v12sm18660749pgr.31.2019.10.01.23.00.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Oct 2019 23:00:59 -0700 (PDT) From: Nicholas Piggin To: kvm-ppc@vger.kernel.org Cc: Nicholas Piggin Subject: [PATCH v2 4/5] KVM: PPC: Book3S HV: Implement LPCR[AIL]=3 mode for injected interrupts Date: Wed, 2 Oct 2019 16:00:24 +1000 Message-Id: <20191002060025.11644-5-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191002060025.11644-1-npiggin@gmail.com> References: <20191002060025.11644-1-npiggin@gmail.com> MIME-Version: 1.0 Sender: kvm-ppc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm-ppc@vger.kernel.org kvmppc_inject_interrupt does not implement LPCR[AIL]!=0 modes, which can result in the guest receiving interrupts as if LPCR[AIL]=0 contrary to the ISA. In practice, Linux guests cope with this deviation, but it should be fixed. Signed-off-by: Nicholas Piggin --- arch/powerpc/kvm/book3s_hv_builtin.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/powerpc/kvm/book3s_hv_builtin.c b/arch/powerpc/kvm/book3s_hv_builtin.c index 068bee941a71..7cd3cf3d366b 100644 --- a/arch/powerpc/kvm/book3s_hv_builtin.c +++ b/arch/powerpc/kvm/book3s_hv_builtin.c @@ -792,6 +792,21 @@ static void inject_interrupt(struct kvm_vcpu *vcpu, int vec, u64 srr1_flags) else new_msr |= msr & MSR_TS_MASK; + /* + * Perform MSR and PC adjustment for LPCR[AIL]=3 if it is set and + * applicable. AIL=2 is not supported. + * + * AIL does not apply to SRESET, MCE, or HMI (which is never + * delivered to the guest), and does not apply if IR=0 or DR=0. + */ + if (vec != BOOK3S_INTERRUPT_SYSTEM_RESET && + vec != BOOK3S_INTERRUPT_MACHINE_CHECK && + (vcpu->arch.vcore->lpcr & LPCR_AIL) == LPCR_AIL_3 && + (msr & (MSR_IR|MSR_DR)) == (MSR_IR|MSR_DR) ) { + new_msr |= MSR_IR | MSR_DR; + new_pc += 0xC000000000004000ULL; + } + kvmppc_set_srr0(vcpu, pc); kvmppc_set_srr1(vcpu, (msr & SRR1_MSR_BITS) | srr1_flags); kvmppc_set_pc(vcpu, new_pc); From patchwork Wed Oct 2 06:00:25 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Nicholas Piggin X-Patchwork-Id: 1170470 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=kvm-ppc-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="O5FJm7yT"; dkim-atps=neutral Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 46jlqz3LVSz9sRX for ; Wed, 2 Oct 2019 16:01:03 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727244AbfJBGBD (ORCPT ); Wed, 2 Oct 2019 02:01:03 -0400 Received: from mail-pl1-f193.google.com ([209.85.214.193]:33000 "EHLO mail-pl1-f193.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726538AbfJBGBC (ORCPT ); Wed, 2 Oct 2019 02:01:02 -0400 Received: by mail-pl1-f193.google.com with SMTP id d22so6659030pls.0 for ; Tue, 01 Oct 2019 23:01:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=4bJEH2pRIC7IajnRMF6AY/PY3WP86bRI3VEm9hDq78I=; b=O5FJm7yTZPqmzf9daVnRIHHBNLqQL0duB1PgG/6ZSkOooE0c6In+PXamZ06JqwTQEE ciiQShwW0DckXlqU8kRP8ImnP5kG5yWp0Z7JqutLwFtS16hYhas8mfqvJgD1J6C6E2E+ na6sTkbt4zUERRjyZxJObYBUsNPYeTRd2t3sfbd1jcaHUiKEriluqZrhz5f5vyOgqWeh +XLLuKUxOuwfDr0MqbACOIREsQD+hiTSijEDfIUlfJVb8yiuzos2NMNM39dm9MRtxCOZ g+Hv1E/gLvqYXAdvBLWnmnZbmHHDLVoM7zeoOWe/dA9b0suZrmjuyWkLIBfn129VkYx/ Vz/w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=4bJEH2pRIC7IajnRMF6AY/PY3WP86bRI3VEm9hDq78I=; b=pTBEJG7dSa8cW+C3RTroSOn7lU+nhkWMIgFzeJak4wLf63vb0iGAS8luHs7MbTk/i0 SXLPM6mnbq2TNqhMxsGszZ38wP2OUl9sCH0IhCXfU8P458i2crpKUSDD74iDI2+j58Dn m2V/ly+trzQB7mVNJtKsbt8IwJlR1kmRmL03I1m8fe5i1eNRDJamp6TCTpE0S8M7lEMW ZSK+TtOhZZQhRJvyKMtyU0vZXq4CLABpqkR4CTiRRx4KOalWe/uyxrBDtXzSUcqM0OeE XQbuI4Z1D7YljrND/UDz0YijmJy2q/wz9MfNYEmaXo4nRDtL1cI6qfa+GHKKqGe5/DkY JH1w== X-Gm-Message-State: APjAAAVpFgBu3z2EZRDjtrPArkkrvaAiPpY2zKCziMCf89Quhd3d4hYf EGdhL6ONjvWf8ibw3C04nWS7hpWm X-Google-Smtp-Source: APXvYqwdr0a++XTul7n2gTpP+MXNmrwIclo8rotO+XmbQZ3RlU/HesC0NPWAamQW4cSw7GMEy8sOuA== X-Received: by 2002:a17:902:8a82:: with SMTP id p2mr1862112plo.112.1569996061624; Tue, 01 Oct 2019 23:01:01 -0700 (PDT) Received: from bobo.ozlabs.ibm.com ([122.99.82.10]) by smtp.gmail.com with ESMTPSA id v12sm18660749pgr.31.2019.10.01.23.00.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 01 Oct 2019 23:01:01 -0700 (PDT) From: Nicholas Piggin To: kvm-ppc@vger.kernel.org Cc: Nicholas Piggin Subject: [PATCH v2 5/5] KVM: PPC: Book3S HV: Reject mflags=2 (LPCR[AIL]=2) ADDR_TRANS_MODE mode Date: Wed, 2 Oct 2019 16:00:25 +1000 Message-Id: <20191002060025.11644-6-npiggin@gmail.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20191002060025.11644-1-npiggin@gmail.com> References: <20191002060025.11644-1-npiggin@gmail.com> MIME-Version: 1.0 Sender: kvm-ppc-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: kvm-ppc@vger.kernel.org AIL=2 mode has no known users, so is not well tested or supported. Disallow guests from selecting this mode because it may become deprecated in future versions of the architecture. This policy decision is not left to QEMU because KVM support is required for AIL=2 (when injecting interrupts). Signed-off-by: Nicholas Piggin --- arch/powerpc/kvm/book3s_hv.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/powerpc/kvm/book3s_hv.c b/arch/powerpc/kvm/book3s_hv.c index c340d416dce3..ec5c0379296a 100644 --- a/arch/powerpc/kvm/book3s_hv.c +++ b/arch/powerpc/kvm/book3s_hv.c @@ -779,6 +779,11 @@ static int kvmppc_h_set_mode(struct kvm_vcpu *vcpu, unsigned long mflags, vcpu->arch.dawr = value1; vcpu->arch.dawrx = value2; return H_SUCCESS; + case H_SET_MODE_RESOURCE_ADDR_TRANS_MODE: + /* KVM does not support mflags=2 (AIL=2) */ + if (mflags != 0 && mflags != 3) + return H_UNSUPPORTED_FLAG_START; + return H_TOO_HARD; default: return H_TOO_HARD; }