From patchwork Tue Oct 1 13:27:03 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ilya Leoshkevich X-Patchwork-Id: 1169939 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-509974-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="G8kKlXiL"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 46jKp91xHDz9s4Y for ; Tue, 1 Oct 2019 23:28:01 +1000 (AEST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:in-reply-to:references:mime-version :content-transfer-encoding:message-id; q=dns; s=default; b=coSDW +x9qyjxGISzwrGgIpIzeze65qFf1Euvj4jwNrBFlv4g+2+8CZ1V/x0+KW43t3KCM +ccf7GEbCcQkSJ3imjKD9/HHEgVxppb9MJgQsfEYnbE2dPcEI/QeBWBJrlRqjvg/ PTatE8FI/xwA51S89Um/bVP65kw+eIZjxO9T40= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:in-reply-to:references:mime-version :content-transfer-encoding:message-id; s=default; bh=2cJYbsnh28T NS3FIfcQdrIUihAI=; b=G8kKlXiLd7Ll/aeV8Z8VRwai+ZHzSNtYIrSWzcwn+pY tgi80hCA/taSRpsaQjph/lAIqKmJlfROwRkb0NgnlgAjn4m3Rz07lADdDaQuqHXE gUG2avx70GkkQ7d42+n7/xxJAtoq3d9Md0Ur0UZHhp+gElXziLiwFa71ReYXinHs = Received: (qmail 90431 invoked by alias); 1 Oct 2019 13:27:53 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 90421 invoked by uid 89); 1 Oct 2019 13:27:53 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-24.0 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.1 spammy= X-HELO: mx0a-001b2d01.pphosted.com Received: from mx0a-001b2d01.pphosted.com (HELO mx0a-001b2d01.pphosted.com) (148.163.156.1) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 01 Oct 2019 13:27:51 +0000 Received: from pps.filterd (m0187473.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x91DRTbj102216 for ; Tue, 1 Oct 2019 09:27:49 -0400 Received: from e06smtp05.uk.ibm.com (e06smtp05.uk.ibm.com [195.75.94.101]) by mx0a-001b2d01.pphosted.com with ESMTP id 2vbsjsp96h-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Tue, 01 Oct 2019 09:27:39 -0400 Received: from localhost by e06smtp05.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Tue, 1 Oct 2019 14:27:21 +0100 Received: from d06av21.portsmouth.uk.ibm.com (d06av21.portsmouth.uk.ibm.com [9.149.105.232]) by b06cxnps4076.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x91DRJZM47251522 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Tue, 1 Oct 2019 13:27:19 GMT Received: from d06av21.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 9FB2C52069; Tue, 1 Oct 2019 13:27:19 +0000 (GMT) Received: from white.boeblingen.de.ibm.com (unknown [9.152.96.81]) by d06av21.portsmouth.uk.ibm.com (Postfix) with ESMTP id 4CC1752059; Tue, 1 Oct 2019 13:27:19 +0000 (GMT) From: Ilya Leoshkevich To: gcc-patches@gcc.gnu.org Cc: richard.guenther@gmail.com, richard.sandiford@arm.com, segher@kernel.crashing.org, joseph@codesourcery.com, krebbel@linux.ibm.com, rdapp@linux.ibm.com, Ilya Leoshkevich Subject: [PATCH v4 1/7] Allow COND_EXPR and VEC_COND_EXPR condtions to trap Date: Tue, 1 Oct 2019 15:27:03 +0200 In-Reply-To: <20191001132709.87257-1-iii@linux.ibm.com> References: <20191001132709.87257-1-iii@linux.ibm.com> MIME-Version: 1.0 x-cbid: 19100113-0020-0000-0000-00000373652B X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19100113-0021-0000-0000-000021C9456A Message-Id: <20191001132709.87257-2-iii@linux.ibm.com> X-IsSubscribed: yes Right now gimplifier does not allow VEC_COND_EXPR's condition to trap and introduces a temporary if this could happen, for example, generating _5 = _4 > { 2.0e+0, 2.0e+0, 2.0e+0, 2.0e+0 }; _6 = VEC_COND_EXPR <_5, { -1, -1, -1, -1 }, { 0, 0, 0, 0 }>; from GENERIC VEC_COND_EXPR < (*b > { 2.0e+0, 2.0e+0, 2.0e+0, 2.0e+0 }) , { -1, -1, -1, -1 } , { 0, 0, 0, 0 } > This is not necessary and makes the resulting GIMPLE harder to analyze. Change the gimplifier so as to allow COND_EXPR and VEC_COND_EXPR conditions to trap. This patch takes special care to avoid introducing trapping comparisons in GIMPLE_COND. They are not allowed, because they would require 3 outgoing edges (then, else and EH), which is awkward to say the least. Therefore, computations of such conditions should live in their own basic blocks. gcc/ChangeLog: 2019-09-03 Ilya Leoshkevich PR target/77918 * gimple-expr.c (gimple_cond_get_ops_from_tree): Assert that the caller passes a non-trapping condition. (is_gimple_condexpr): Allow trapping conditions. (is_gimple_condexpr_1): New helper function. (is_gimple_condexpr_for_cond): New function, acts like old is_gimple_condexpr. * gimple-expr.h (is_gimple_condexpr_for_cond): New function. * gimple.c (gimple_could_trap_p_1): Handle COND_EXPR and VEC_COND_EXPR. Fix an issue with statements like i = (fp < 1.). * gimplify.c (gimplify_cond_expr): Use is_gimple_condexpr_for_cond. (gimplify_expr): Allow is_gimple_condexpr_for_cond. * tree-eh.c (operation_could_trap_p): Assert on COND_EXPR and VEC_COND_EXPR. (tree_could_trap_p): Handle COND_EXPR and VEC_COND_EXPR. * tree-ssa-forwprop.c (forward_propagate_into_gimple_cond): Use is_gimple_condexpr_for_cond, remove pointless tmp check (forward_propagate_into_cond): Remove pointless tmp check. --- gcc/gimple-expr.c | 25 +++++++++++++++++++++---- gcc/gimple-expr.h | 1 + gcc/gimple.c | 14 +++++++++++++- gcc/gimplify.c | 5 +++-- gcc/tree-eh.c | 8 ++++++++ gcc/tree-ssa-forwprop.c | 7 ++++--- 6 files changed, 50 insertions(+), 10 deletions(-) diff --git a/gcc/gimple-expr.c b/gcc/gimple-expr.c index 4082828e198..1738af186d7 100644 --- a/gcc/gimple-expr.c +++ b/gcc/gimple-expr.c @@ -574,6 +574,7 @@ gimple_cond_get_ops_from_tree (tree cond, enum tree_code *code_p, || TREE_CODE (cond) == TRUTH_NOT_EXPR || is_gimple_min_invariant (cond) || SSA_VAR_P (cond)); + gcc_checking_assert (!tree_could_throw_p (cond)); extract_ops_from_tree (cond, code_p, lhs_p, rhs_p); @@ -605,17 +606,33 @@ is_gimple_lvalue (tree t) || TREE_CODE (t) == BIT_FIELD_REF); } -/* Return true if T is a GIMPLE condition. */ +/* Helper for is_gimple_condexpr and is_gimple_condexpr_for_cond. */ -bool -is_gimple_condexpr (tree t) +static bool +is_gimple_condexpr_1 (tree t, bool allow_traps) { return (is_gimple_val (t) || (COMPARISON_CLASS_P (t) - && !tree_could_throw_p (t) + && (allow_traps || !tree_could_throw_p (t)) && is_gimple_val (TREE_OPERAND (t, 0)) && is_gimple_val (TREE_OPERAND (t, 1)))); } +/* Return true if T is a GIMPLE condition. */ + +bool +is_gimple_condexpr (tree t) +{ + return is_gimple_condexpr_1 (t, true); +} + +/* Like is_gimple_condexpr, but does not allow T to trap. */ + +bool +is_gimple_condexpr_for_cond (tree t) +{ + return is_gimple_condexpr_1 (t, false); +} + /* Return true if T is a gimple address. */ bool diff --git a/gcc/gimple-expr.h b/gcc/gimple-expr.h index 1ad1432bd17..0925aeb0f57 100644 --- a/gcc/gimple-expr.h +++ b/gcc/gimple-expr.h @@ -41,6 +41,7 @@ extern void gimple_cond_get_ops_from_tree (tree, enum tree_code *, tree *, tree *); extern bool is_gimple_lvalue (tree); extern bool is_gimple_condexpr (tree); +extern bool is_gimple_condexpr_for_cond (tree); extern bool is_gimple_address (const_tree); extern bool is_gimple_invariant_address (const_tree); extern bool is_gimple_ip_invariant_address (const_tree); diff --git a/gcc/gimple.c b/gcc/gimple.c index 8e828a5f169..a874c29454c 100644 --- a/gcc/gimple.c +++ b/gcc/gimple.c @@ -2149,10 +2149,22 @@ gimple_could_trap_p_1 (gimple *s, bool include_mem, bool include_stores) return false; case GIMPLE_ASSIGN: - t = gimple_expr_type (s); op = gimple_assign_rhs_code (s); + + /* For COND_EXPR and VEC_COND_EXPR only the condition may trap. */ + if (op == COND_EXPR || op == VEC_COND_EXPR) + return tree_could_trap_p (gimple_assign_rhs1 (s)); + + /* For comparisons we need to check rhs operand types instead of rhs type + (which is BOOLEAN_TYPE). */ + if (TREE_CODE_CLASS (op) == tcc_comparison) + t = TREE_TYPE (gimple_assign_rhs1 (s)); + else + t = gimple_expr_type (s); + if (get_gimple_rhs_class (op) == GIMPLE_BINARY_RHS) div = gimple_assign_rhs2 (s); + return (operation_could_trap_p (op, FLOAT_TYPE_P (t), (INTEGRAL_TYPE_P (t) && TYPE_OVERFLOW_TRAPS (t)), diff --git a/gcc/gimplify.c b/gcc/gimplify.c index 88d6571976f..836706961f3 100644 --- a/gcc/gimplify.c +++ b/gcc/gimplify.c @@ -4142,8 +4142,8 @@ gimplify_cond_expr (tree *expr_p, gimple_seq *pre_p, fallback_t fallback) /* Now do the normal gimplification. */ /* Gimplify condition. */ - ret = gimplify_expr (&TREE_OPERAND (expr, 0), pre_p, NULL, is_gimple_condexpr, - fb_rvalue); + ret = gimplify_expr (&TREE_OPERAND (expr, 0), pre_p, NULL, + is_gimple_condexpr_for_cond, fb_rvalue); if (ret == GS_ERROR) return GS_ERROR; gcc_assert (TREE_OPERAND (expr, 0) != NULL_TREE); @@ -12976,6 +12976,7 @@ gimplify_expr (tree *expr_p, gimple_seq *pre_p, gimple_seq *post_p, else if (gimple_test_f == is_gimple_val || gimple_test_f == is_gimple_call_addr || gimple_test_f == is_gimple_condexpr + || gimple_test_f == is_gimple_condexpr_for_cond || gimple_test_f == is_gimple_mem_rhs || gimple_test_f == is_gimple_mem_rhs_or_call || gimple_test_f == is_gimple_reg_rhs diff --git a/gcc/tree-eh.c b/gcc/tree-eh.c index 5bb07e49d28..b3722ba8839 100644 --- a/gcc/tree-eh.c +++ b/gcc/tree-eh.c @@ -2523,6 +2523,10 @@ operation_could_trap_p (enum tree_code op, bool fp_operation, bool honor_trapv, bool honor_snans = fp_operation && flag_signaling_nans != 0; bool handled; + /* This function cannot tell whether or not COND_EXPR and VEC_COND_EXPR could + trap, because that depends on the respective condition op. */ + gcc_assert (op != COND_EXPR && op != VEC_COND_EXPR); + if (TREE_CODE_CLASS (op) != tcc_comparison && TREE_CODE_CLASS (op) != tcc_unary && TREE_CODE_CLASS (op) != tcc_binary) @@ -2610,6 +2614,10 @@ tree_could_trap_p (tree expr) if (!expr) return false; + /* For COND_EXPR and VEC_COND_EXPR only the condition may trap. */ + if (TREE_CODE (expr) == COND_EXPR || TREE_CODE (expr) == VEC_COND_EXPR) + expr = TREE_OPERAND (expr, 0); + code = TREE_CODE (expr); t = TREE_TYPE (expr); diff --git a/gcc/tree-ssa-forwprop.c b/gcc/tree-ssa-forwprop.c index 221f140b356..0d1c066b354 100644 --- a/gcc/tree-ssa-forwprop.c +++ b/gcc/tree-ssa-forwprop.c @@ -527,9 +527,10 @@ forward_propagate_into_gimple_cond (gcond *stmt) tmp = forward_propagate_into_comparison_1 (stmt, code, boolean_type_node, rhs1, rhs2); - if (tmp) + if (tmp + && is_gimple_condexpr_for_cond (tmp)) { - if (dump_file && tmp) + if (dump_file) { fprintf (dump_file, " Replaced '"); print_gimple_expr (dump_file, stmt, 0); @@ -607,7 +608,7 @@ forward_propagate_into_cond (gimple_stmt_iterator *gsi_p) if (tmp && is_gimple_condexpr (tmp)) { - if (dump_file && tmp) + if (dump_file) { fprintf (dump_file, " Replaced '"); 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Tue, 1 Oct 2019 14:27:38 +0100 Received: from d06av21.portsmouth.uk.ibm.com (d06av21.portsmouth.uk.ibm.com [9.149.105.232]) by b06cxnps3075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x91DRaFP47841508 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Tue, 1 Oct 2019 13:27:36 GMT Received: from d06av21.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id C69C252063; Tue, 1 Oct 2019 13:27:36 +0000 (GMT) Received: from white.boeblingen.de.ibm.com (unknown [9.152.96.81]) by d06av21.portsmouth.uk.ibm.com (Postfix) with ESMTP id 73CF15206B; Tue, 1 Oct 2019 13:27:36 +0000 (GMT) From: Ilya Leoshkevich To: gcc-patches@gcc.gnu.org Cc: richard.guenther@gmail.com, richard.sandiford@arm.com, segher@kernel.crashing.org, joseph@codesourcery.com, krebbel@linux.ibm.com, rdapp@linux.ibm.com, Ilya Leoshkevich Subject: [PATCH v4 2/7] Introduce can_vcond_compare_p function Date: Tue, 1 Oct 2019 15:27:04 +0200 In-Reply-To: <20191001132709.87257-1-iii@linux.ibm.com> References: <20191001132709.87257-1-iii@linux.ibm.com> MIME-Version: 1.0 x-cbid: 19100113-0012-0000-0000-000003526829 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19100113-0013-0000-0000-0000218D0ED8 Message-Id: <20191001132709.87257-3-iii@linux.ibm.com> X-IsSubscribed: yes z13 supports only non-signaling vector comparisons. This means we cannot vectorize LT, LE, GT, GE and LTGT when compiling for z13. However, we cannot express this restriction today: the code only checks whether vcond$a$b optab exists, which does not contain information about the operation. Introduce a function that checks whether back-end supports vector comparisons with individual rtx codes by matching vcond expander's third argument with a fake comparison with the corresponding rtx code. gcc/ChangeLog: 2019-08-27 Ilya Leoshkevich PR target/77918 * optabs-tree.c (vcond_icode_p): New function. (vcond_eq_icode_p): New function. (expand_vec_cond_expr_p): Use vcond_icode_p and vcond_eq_icode_p. * optabs.c (can_vcond_compare_p): New function. (get_rtx_code): Use get_rtx_code_safe. (get_rtx_code_safe): New function. * optabs.h (can_vcond_compare_p): New function. (get_rtx_code_safe): Likewise. --- gcc/optabs-tree.c | 37 +++++++++++++++++++++++++++++++------ gcc/optabs.c | 38 ++++++++++++++++++++++++++++++++++---- gcc/optabs.h | 7 +++++++ 3 files changed, 72 insertions(+), 10 deletions(-) diff --git a/gcc/optabs-tree.c b/gcc/optabs-tree.c index 8157798cc71..7f505c9cdee 100644 --- a/gcc/optabs-tree.c +++ b/gcc/optabs-tree.c @@ -23,7 +23,10 @@ along with GCC; see the file COPYING3. If not see #include "coretypes.h" #include "target.h" #include "insn-codes.h" +#include "rtl.h" #include "tree.h" +#include "memmodel.h" +#include "optabs.h" #include "optabs-tree.h" #include "stor-layout.h" @@ -329,6 +332,28 @@ expand_vec_cmp_expr_p (tree value_type, tree mask_type, enum tree_code code) return false; } +/* Return true iff vcond_optab/vcondu_optab support the given tree + comparison. */ + +static bool +vcond_icode_p (tree value_type, tree cmp_op_type, enum tree_code code) +{ + return can_vcond_compare_p (get_rtx_code (code, TYPE_UNSIGNED (cmp_op_type)), + TYPE_MODE (value_type), TYPE_MODE (cmp_op_type)); +} + +/* Return true iff vcondeq_optab supports the given tree comparison. */ + +static bool +vcond_eq_icode_p (tree value_type, tree cmp_op_type, enum tree_code code) +{ + if (code != EQ_EXPR && code != NE_EXPR) + return false; + + return get_vcond_eq_icode (TYPE_MODE (value_type), TYPE_MODE (cmp_op_type)) + != CODE_FOR_nothing; +} + /* Return TRUE iff, appropriate vector insns are available for vector cond expr with vector type VALUE_TYPE and a comparison with operand vector types in CMP_OP_TYPE. */ @@ -347,14 +372,14 @@ expand_vec_cond_expr_p (tree value_type, tree cmp_op_type, enum tree_code code) || maybe_ne (GET_MODE_NUNITS (value_mode), GET_MODE_NUNITS (cmp_op_mode))) return false; - if (get_vcond_icode (TYPE_MODE (value_type), TYPE_MODE (cmp_op_type), - TYPE_UNSIGNED (cmp_op_type)) == CODE_FOR_nothing - && ((code != EQ_EXPR && code != NE_EXPR) - || get_vcond_eq_icode (TYPE_MODE (value_type), - TYPE_MODE (cmp_op_type)) == CODE_FOR_nothing)) + if (get_rtx_code_safe (code, TYPE_UNSIGNED (cmp_op_type)) + == LAST_AND_UNUSED_RTX_CODE) + /* This may happen, for example, if code == SSA_NAME, in which case we + cannot be certain whether a vector insn is available. */ return false; - return true; + return vcond_icode_p (value_type, cmp_op_type, code) + || vcond_eq_icode_p (value_type, cmp_op_type, code); } /* Use the current target and options to initialize diff --git a/gcc/optabs.c b/gcc/optabs.c index 35921e691f9..d759449846e 100644 --- a/gcc/optabs.c +++ b/gcc/optabs.c @@ -3819,6 +3819,25 @@ can_compare_p (enum rtx_code code, machine_mode mode, return 0; } +/* Return whether the backend can emit a vector comparison for code CODE, + comparing operands of mode CMP_OP_MODE and producing a result with + VALUE_MODE. */ + +bool +can_vcond_compare_p (enum rtx_code code, machine_mode value_mode, + machine_mode cmp_op_mode) +{ + enum insn_code icode; + bool unsigned_p = (code == LTU || code == LEU || code == GTU || code == GEU); + rtx reg1 = alloca_raw_REG (cmp_op_mode, LAST_VIRTUAL_REGISTER + 1); + rtx reg2 = alloca_raw_REG (cmp_op_mode, LAST_VIRTUAL_REGISTER + 2); + rtx test = alloca_rtx_fmt_ee (code, value_mode, reg1, reg2); + + return (icode = get_vcond_icode (value_mode, cmp_op_mode, unsigned_p)) + != CODE_FOR_nothing + && insn_operand_matches (icode, 3, test); +} + /* This function is called when we are going to emit a compare instruction that compares the values found in X and Y, using the rtl operator COMPARISON. @@ -5348,11 +5367,11 @@ gen_cond_trap (enum rtx_code code, rtx op1, rtx op2, rtx tcode) return insn; } -/* Return rtx code for TCODE. Use UNSIGNEDP to select signed - or unsigned operation code. */ +/* Return rtx code for TCODE or LAST_AND_UNUSED_RTX_CODE if it has no RTL + counterpart. Use UNSIGNEDP to select signed or unsigned operation code. */ enum rtx_code -get_rtx_code (enum tree_code tcode, bool unsignedp) +get_rtx_code_safe (enum tree_code tcode, bool unsignedp) { enum rtx_code code; switch (tcode) @@ -5410,11 +5429,22 @@ get_rtx_code (enum tree_code tcode, bool unsignedp) break; default: - gcc_unreachable (); + code = LAST_AND_UNUSED_RTX_CODE; + break; } return code; } +/* Like get_rtx_code_safe, but asserts when given unsupported tree codes. */ + +enum rtx_code +get_rtx_code (enum tree_code tcode, bool unsignedp) +{ + enum rtx_code code = get_rtx_code_safe (tcode, unsignedp); + gcc_assert (code != LAST_AND_UNUSED_RTX_CODE); + return code; +} + /* Return a comparison rtx of mode CMP_MODE for COND. Use UNSIGNEDP to select signed or unsigned operators. OPNO holds the index of the first comparison operand for insn ICODE. Do not generate the diff --git a/gcc/optabs.h b/gcc/optabs.h index 897bb5d4443..4cebe231191 100644 --- a/gcc/optabs.h +++ b/gcc/optabs.h @@ -242,6 +242,12 @@ enum can_compare_purpose (without splitting it into pieces). */ extern int can_compare_p (enum rtx_code, machine_mode, enum can_compare_purpose); + +/* Return whether the backend can emit a vector comparison for code CODE, + comparing operands of mode CMP_OP_MODE and producing a result with + VALUE_MODE. */ +extern bool can_vcond_compare_p (enum rtx_code, machine_mode, machine_mode); + extern rtx prepare_operand (enum insn_code, rtx, int, machine_mode, machine_mode, int); /* Emit a pair of rtl insns to compare two rtx's and to jump @@ -356,6 +362,7 @@ extern void expand_insn (enum insn_code icode, unsigned int nops, extern void expand_jump_insn (enum insn_code icode, unsigned int nops, class expand_operand *ops); +extern enum rtx_code get_rtx_code_safe (enum tree_code tcode, bool unsignedp); extern enum rtx_code get_rtx_code (enum tree_code tcode, bool unsignedp); #endif /* GCC_OPTABS_H */ From patchwork Tue Oct 1 13:27:05 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ilya Leoshkevich X-Patchwork-Id: 1169940 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-509975-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="kWovxAsA"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 46jKpP0B3pz9s4Y for ; Tue, 1 Oct 2019 23:28:12 +1000 (AEST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:in-reply-to:references:mime-version :content-transfer-encoding:message-id; q=dns; s=default; b=ZrIgF j9AwrhjCC82frwKGUpiukFvtKCae09ja5IeDJi16457rS3lgiZIyHlNMGzRbpDoF sSokLC+EtKDYYtudCdfbzaqjfb7QZfwpQAaVoFHbIxBmRq43iGwEUofNXmwsdab8 ioowb7IBPR5evLUlBN2EE/R7A3/F2qG8Uvs9no= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:in-reply-to:references:mime-version :content-transfer-encoding:message-id; s=default; bh=7xCMQ3egqo6 YD4GrByicXxPlj1g=; b=kWovxAsAFz0oFRJ/73otlO9dQM3yt9WfpNmuaq96OsU 5Ev2cimkyBd2wnpSW0r8Fg/QU50d/cyhrczNbiYxN0wNgLTp5ilL4f4XZtunxpLs G5+q3xRtTdhAdCgxIPinbLe7agwWiDQND6ZYP36zgNjp4YUlNkSr2x1QZOSDebSc = Received: (qmail 90826 invoked by alias); 1 Oct 2019 13:27:56 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 90768 invoked by uid 89); 1 Oct 2019 13:27:56 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-23.8 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, KAM_NUMSUBJECT, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.1 spammy= X-HELO: mx0a-001b2d01.pphosted.com Received: from mx0b-001b2d01.pphosted.com (HELO mx0a-001b2d01.pphosted.com) (148.163.158.5) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 01 Oct 2019 13:27:55 +0000 Received: from pps.filterd (m0098421.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x91DR45s043084 for ; Tue, 1 Oct 2019 09:27:53 -0400 Received: from e06smtp05.uk.ibm.com (e06smtp05.uk.ibm.com [195.75.94.101]) by mx0a-001b2d01.pphosted.com with ESMTP id 2vc69yue68-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Tue, 01 Oct 2019 09:27:52 -0400 Received: from localhost by e06smtp05.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Tue, 1 Oct 2019 14:27:47 +0100 Received: from d06av21.portsmouth.uk.ibm.com (d06av21.portsmouth.uk.ibm.com [9.149.105.232]) by b06cxnps3074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x91DRjZ221495824 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Tue, 1 Oct 2019 13:27:45 GMT Received: from d06av21.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id D0B2B52065; Tue, 1 Oct 2019 13:27:45 +0000 (GMT) Received: from white.boeblingen.de.ibm.com (unknown [9.152.96.81]) by d06av21.portsmouth.uk.ibm.com (Postfix) with ESMTP id 7D8A752059; Tue, 1 Oct 2019 13:27:45 +0000 (GMT) From: Ilya Leoshkevich To: gcc-patches@gcc.gnu.org Cc: richard.guenther@gmail.com, richard.sandiford@arm.com, segher@kernel.crashing.org, joseph@codesourcery.com, krebbel@linux.ibm.com, rdapp@linux.ibm.com, Ilya Leoshkevich Subject: [PATCH v4 3/7] S/390: Do not use signaling vector comparisons on z13 Date: Tue, 1 Oct 2019 15:27:05 +0200 In-Reply-To: <20191001132709.87257-1-iii@linux.ibm.com> References: <20191001132709.87257-1-iii@linux.ibm.com> MIME-Version: 1.0 x-cbid: 19100113-0020-0000-0000-00000373652E X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19100113-0021-0000-0000-000021C9456D Message-Id: <20191001132709.87257-4-iii@linux.ibm.com> X-IsSubscribed: yes z13 supports only non-signaling vector comparisons. This means we cannot vectorize LT, LE, GT, GE and LTGT when compiling for z13. Notify middle-end about this by using more restrictive operator predicate in vcond. gcc/ChangeLog: 2019-08-21 Ilya Leoshkevich PR target/77918 * config/s390/vector.md (vcond_comparison_operator): New predicate. (vcond): Use vcond_comparison_operator. --- gcc/config/s390/vector.md | 22 +++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/gcc/config/s390/vector.md b/gcc/config/s390/vector.md index 961d2c655e4..8a0b01f562b 100644 --- a/gcc/config/s390/vector.md +++ b/gcc/config/s390/vector.md @@ -614,10 +614,30 @@ operands[2] = GEN_INT (GET_MODE_NUNITS (mode) - 1); }) +(define_predicate "vcond_comparison_operator" + (match_operand 0 "comparison_operator") +{ + if (!HONOR_NANS (GET_MODE (XEXP (op, 0))) + && !HONOR_NANS (GET_MODE (XEXP (op, 1)))) + return true; + switch (GET_CODE (op)) + { + case LE: + case LT: + case GE: + case GT: + case LTGT: + /* Signaling vector comparisons are supported only on z14+. */ + return TARGET_Z14; + default: + return true; + } +}) + (define_expand "vcond" [(set (match_operand:V_HW 0 "register_operand" "") (if_then_else:V_HW - (match_operator 3 "comparison_operator" + (match_operator 3 "vcond_comparison_operator" [(match_operand:V_HW2 4 "register_operand" "") (match_operand:V_HW2 5 "nonmemory_operand" "")]) (match_operand:V_HW 1 "nonmemory_operand" "") From patchwork Tue Oct 1 13:27:06 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ilya Leoshkevich X-Patchwork-Id: 1169942 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-509977-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="k/OZAaHW"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 46jKpt0QBLz9s4Y for ; Tue, 1 Oct 2019 23:28:37 +1000 (AEST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:in-reply-to:references:mime-version :content-transfer-encoding:message-id; q=dns; s=default; b=bZTx6 S8rUjffoGENsnhHwr6Us5w68zLaT6JWcEMmJSQpWQANKI8AHLNcn8K6Cb/mnWJrB XaaigP3hGyA7FaSLv+mVijzy6GfZpEyQ0lInH8cKRTGHDIOhr5tTPQFqX6396hgo De2hPHi0elRu7Gq1M7EXEJKhP6GJoz5rDubvZk= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:in-reply-to:references:mime-version :content-transfer-encoding:message-id; s=default; bh=AxcrTGPa1yb 4+xd69i8daiOHM28=; b=k/OZAaHWtAgAtlKszc3hTS92KTyLfDZ0tActnqA56Gg GSYQNTz2M3LVAJDDdbNcr1CuwLm8KMsrNjjORh+K8psOltcj2lyVyDJd1zO3i1b+ ulwFIv3eQ93omxQC3WGH1djwA4/kVKKEweR5MnW0z0mq9MeF6SILffiab44OPk2U = Received: (qmail 91648 invoked by alias); 1 Oct 2019 13:28:03 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 91606 invoked by uid 89); 1 Oct 2019 13:28:02 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-24.2 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.1 spammy=HX-Languages-Length:1305 X-HELO: mx0a-001b2d01.pphosted.com Received: from mx0a-001b2d01.pphosted.com (HELO mx0a-001b2d01.pphosted.com) (148.163.156.1) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 01 Oct 2019 13:28:01 +0000 Received: from pps.filterd (m0098409.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x91DR7Dd124457 for ; Tue, 1 Oct 2019 09:28:00 -0400 Received: from e06smtp02.uk.ibm.com (e06smtp02.uk.ibm.com [195.75.94.98]) by mx0a-001b2d01.pphosted.com with ESMTP id 2vc5jumyxy-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Tue, 01 Oct 2019 09:27:59 -0400 Received: from localhost by e06smtp02.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted for from ; Tue, 1 Oct 2019 14:27:57 +0100 Received: from b06cxnps3074.portsmouth.uk.ibm.com (9.149.109.194) by e06smtp02.uk.ibm.com (192.168.101.132) with IBM ESMTP SMTP Gateway: Authorized Use Only! Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Tue, 1 Oct 2019 14:27:54 +0100 Received: from d06av21.portsmouth.uk.ibm.com (d06av21.portsmouth.uk.ibm.com [9.149.105.232]) by b06cxnps3074.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x91DRq0x43188472 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Tue, 1 Oct 2019 13:27:52 GMT Received: from d06av21.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 662AF52067; Tue, 1 Oct 2019 13:27:52 +0000 (GMT) Received: from white.boeblingen.de.ibm.com (unknown [9.152.96.81]) by d06av21.portsmouth.uk.ibm.com (Postfix) with ESMTP id F226852059; Tue, 1 Oct 2019 13:27:51 +0000 (GMT) From: Ilya Leoshkevich To: gcc-patches@gcc.gnu.org Cc: richard.guenther@gmail.com, richard.sandiford@arm.com, segher@kernel.crashing.org, joseph@codesourcery.com, krebbel@linux.ibm.com, rdapp@linux.ibm.com, Ilya Leoshkevich Subject: [PATCH v4 4/7] S/390: Implement vcond expander for V1TI,V1TF Date: Tue, 1 Oct 2019 15:27:06 +0200 In-Reply-To: <20191001132709.87257-1-iii@linux.ibm.com> References: <20191001132709.87257-1-iii@linux.ibm.com> MIME-Version: 1.0 x-cbid: 19100113-0008-0000-0000-0000031CC5A0 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19100113-0009-0000-0000-00004A3B7002 Message-Id: <20191001132709.87257-5-iii@linux.ibm.com> X-IsSubscribed: yes Currently gcc does not emit wf{c,k}* instructions when comparing long double values. Middle-end actually adds them in the first place, but then veclower pass replaces them with floating point register pair operations, because the corresponding expander is missing. gcc/ChangeLog: 2019-08-09 Ilya Leoshkevich PR target/77918 * config/s390/vector.md (V_HW): Add V1TI in order to make vcond$a$b generate vcondv1tiv1tf. --- gcc/config/s390/vector.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/gcc/config/s390/vector.md b/gcc/config/s390/vector.md index 8a0b01f562b..2c2c56f7835 100644 --- a/gcc/config/s390/vector.md +++ b/gcc/config/s390/vector.md @@ -29,7 +29,7 @@ ; All modes directly supported by the hardware having full vector reg size ; V_HW2 is duplicate of V_HW for having two iterators expanding ; independently e.g. vcond -(define_mode_iterator V_HW [V16QI V8HI V4SI V2DI V2DF (V4SF "TARGET_VXE") (V1TF "TARGET_VXE")]) +(define_mode_iterator V_HW [V16QI V8HI V4SI V2DI (V1TI "TARGET_VXE") V2DF (V4SF "TARGET_VXE") (V1TF "TARGET_VXE")]) (define_mode_iterator V_HW2 [V16QI V8HI V4SI V2DI V2DF (V4SF "TARGET_VXE") (V1TF "TARGET_VXE")]) (define_mode_iterator V_HW_64 [V2DI V2DF]) From patchwork Tue Oct 1 13:27:07 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ilya Leoshkevich X-Patchwork-Id: 1169943 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-509978-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="Ui+BP0kM"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 46jKq73jqKz9s4Y for ; Tue, 1 Oct 2019 23:28:51 +1000 (AEST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:in-reply-to:references:mime-version :content-transfer-encoding:message-id; q=dns; s=default; b=pTw3+ G5wzSNtQTEsZlh9zNetXsD/d2OQ0eppD2mTzg34sfXdEaV8mlrE7/yOfFAhrqAZy tjX4RnCuQ+6z594siDyXV2wxXKon2mMhpYSSOjrKaVNsOctbV55czq/fv6GztfRU 0sEvQPTyheR4NGtF2wtBn77Xij0e1DGk+Xs8tA= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:in-reply-to:references:mime-version :content-transfer-encoding:message-id; s=default; bh=656I9BXckd4 PvQ5eEJsJch3EujM=; b=Ui+BP0kM74zzW8CAGTkU0bPdCQqKIy9AzK1Cm73U9yy v95yUuFA+96mqLKzGMdSdAvc+DmeWg6TXNwyCN2Z3ZKx5lIvtius65DSFYLc5hjK UND3R/fBIVDokP3IDxDKwNB5nQ/uqRkrO4DjErbOF3X/0EVokjsRvZG6k4MN3cgQ = Received: (qmail 93073 invoked by alias); 1 Oct 2019 13:28:14 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 93011 invoked by uid 89); 1 Oct 2019 13:28:14 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-24.2 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.1 spammy= X-HELO: mx0a-001b2d01.pphosted.com Received: from mx0a-001b2d01.pphosted.com (HELO mx0a-001b2d01.pphosted.com) (148.163.156.1) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 01 Oct 2019 13:28:12 +0000 Received: from pps.filterd (m0098410.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x91DR86R047249 for ; Tue, 1 Oct 2019 09:28:10 -0400 Received: from e06smtp01.uk.ibm.com (e06smtp01.uk.ibm.com [195.75.94.97]) by mx0a-001b2d01.pphosted.com with ESMTP id 2vc6r6tcbf-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Tue, 01 Oct 2019 09:28:10 -0400 Received: from localhost by e06smtp01.uk.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Tue, 1 Oct 2019 14:28:06 +0100 Received: from d06av21.portsmouth.uk.ibm.com (d06av21.portsmouth.uk.ibm.com [9.149.105.232]) by b06cxnps3075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x91DS4bG54460528 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Tue, 1 Oct 2019 13:28:04 GMT Received: from d06av21.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 910B252067; Tue, 1 Oct 2019 13:28:04 +0000 (GMT) Received: from white.boeblingen.de.ibm.com (unknown [9.152.96.81]) by d06av21.portsmouth.uk.ibm.com (Postfix) with ESMTP id 3DC3E52065; Tue, 1 Oct 2019 13:28:04 +0000 (GMT) From: Ilya Leoshkevich To: gcc-patches@gcc.gnu.org Cc: richard.guenther@gmail.com, richard.sandiford@arm.com, segher@kernel.crashing.org, joseph@codesourcery.com, krebbel@linux.ibm.com, rdapp@linux.ibm.com, Ilya Leoshkevich Subject: [PATCH v4 5/7] S/390: Remove code duplication in vec_* comparison expanders Date: Tue, 1 Oct 2019 15:27:07 +0200 In-Reply-To: <20191001132709.87257-1-iii@linux.ibm.com> References: <20191001132709.87257-1-iii@linux.ibm.com> MIME-Version: 1.0 x-cbid: 19100113-4275-0000-0000-0000036CE42C X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19100113-4276-0000-0000-0000387F6EB6 Message-Id: <20191001132709.87257-6-iii@linux.ibm.com> X-IsSubscribed: yes s390.md uses a lot of near-identical expanders that perform dispatching to other expanders based on operand types. Since the following patch would require even more of these, avoid copy-pasting the code by generating these expanders using an iterator. gcc/ChangeLog: 2019-08-09 Ilya Leoshkevich PR target/77918 * config/s390/s390.c (s390_expand_vec_compare): Use gen_vec_cmpordered and gen_vec_cmpunordered. * config/s390/vector.md (vec_cmpuneq, vec_cmpltgt, vec_ordered, vec_unordered): Delete. (vec_ordered): Rename to vec_cmpordered. (vec_unordered): Rename to vec_cmpunordered. (VEC_CMP_EXPAND): New iterator for the generic dispatcher. (vec_cmp): Generic dispatcher. --- gcc/config/s390/s390.c | 4 +-- gcc/config/s390/vector.md | 67 +++++++-------------------------------- 2 files changed, 13 insertions(+), 58 deletions(-) diff --git a/gcc/config/s390/s390.c b/gcc/config/s390/s390.c index 1764c3450e6..062cbd8099d 100644 --- a/gcc/config/s390/s390.c +++ b/gcc/config/s390/s390.c @@ -6523,10 +6523,10 @@ s390_expand_vec_compare (rtx target, enum rtx_code cond, emit_insn (gen_vec_cmpltgt (target, cmp_op1, cmp_op2)); return; case ORDERED: - emit_insn (gen_vec_ordered (target, cmp_op1, cmp_op2)); + emit_insn (gen_vec_cmpordered (target, cmp_op1, cmp_op2)); return; case UNORDERED: - emit_insn (gen_vec_unordered (target, cmp_op1, cmp_op2)); + emit_insn (gen_vec_cmpunordered (target, cmp_op1, cmp_op2)); return; default: break; } diff --git a/gcc/config/s390/vector.md b/gcc/config/s390/vector.md index 2c2c56f7835..15b0e7f1802 100644 --- a/gcc/config/s390/vector.md +++ b/gcc/config/s390/vector.md @@ -1492,22 +1492,6 @@ operands[3] = gen_reg_rtx (mode); }) -(define_expand "vec_cmpuneq" - [(match_operand 0 "register_operand" "") - (match_operand 1 "register_operand" "") - (match_operand 2 "register_operand" "")] - "TARGET_VX" -{ - if (GET_MODE (operands[1]) == V4SFmode) - emit_insn (gen_vec_cmpuneqv4sf (operands[0], operands[1], operands[2])); - else if (GET_MODE (operands[1]) == V2DFmode) - emit_insn (gen_vec_cmpuneqv2df (operands[0], operands[1], operands[2])); - else - gcc_unreachable (); - - DONE; -}) - ; LTGT a <> b -> a > b | b > a (define_expand "vec_cmpltgt" [(set (match_operand: 0 "register_operand" "=v") @@ -1520,24 +1504,8 @@ operands[3] = gen_reg_rtx (mode); }) -(define_expand "vec_cmpltgt" - [(match_operand 0 "register_operand" "") - (match_operand 1 "register_operand" "") - (match_operand 2 "register_operand" "")] - "TARGET_VX" -{ - if (GET_MODE (operands[1]) == V4SFmode) - emit_insn (gen_vec_cmpltgtv4sf (operands[0], operands[1], operands[2])); - else if (GET_MODE (operands[1]) == V2DFmode) - emit_insn (gen_vec_cmpltgtv2df (operands[0], operands[1], operands[2])); - else - gcc_unreachable (); - - DONE; -}) - ; ORDERED (a, b): a >= b | b > a -(define_expand "vec_ordered" +(define_expand "vec_cmpordered" [(set (match_operand: 0 "register_operand" "=v") (ge: (match_operand:VFT 1 "register_operand" "v") (match_operand:VFT 2 "register_operand" "v"))) @@ -1548,45 +1516,32 @@ operands[3] = gen_reg_rtx (mode); }) -(define_expand "vec_ordered" - [(match_operand 0 "register_operand" "") - (match_operand 1 "register_operand" "") - (match_operand 2 "register_operand" "")] - "TARGET_VX" -{ - if (GET_MODE (operands[1]) == V4SFmode) - emit_insn (gen_vec_orderedv4sf (operands[0], operands[1], operands[2])); - else if (GET_MODE (operands[1]) == V2DFmode) - emit_insn (gen_vec_orderedv2df (operands[0], operands[1], operands[2])); - else - gcc_unreachable (); - - DONE; -}) - ; UNORDERED (a, b): !ORDERED (a, b) -(define_expand "vec_unordered" +(define_expand "vec_cmpunordered" [(match_operand: 0 "register_operand" "=v") (match_operand:VFT 1 "register_operand" "v") (match_operand:VFT 2 "register_operand" "v")] "TARGET_VX" { - emit_insn (gen_vec_ordered (operands[0], operands[1], operands[2])); + emit_insn (gen_vec_cmpordered (operands[0], operands[1], operands[2])); emit_insn (gen_rtx_SET (operands[0], gen_rtx_NOT (mode, operands[0]))); DONE; }) -(define_expand "vec_unordered" +(define_code_iterator VEC_CMP_EXPAND + [uneq ltgt ordered unordered]) + +(define_expand "vec_cmp" [(match_operand 0 "register_operand" "") - (match_operand 1 "register_operand" "") - (match_operand 2 "register_operand" "")] + (VEC_CMP_EXPAND (match_operand 1 "register_operand" "") + (match_operand 2 "register_operand" ""))] "TARGET_VX" { if (GET_MODE (operands[1]) == V4SFmode) - emit_insn (gen_vec_unorderedv4sf (operands[0], operands[1], operands[2])); + emit_insn (gen_vec_cmpv4sf (operands[0], operands[1], operands[2])); else if (GET_MODE (operands[1]) == V2DFmode) - emit_insn (gen_vec_unorderedv2df (operands[0], operands[1], operands[2])); + emit_insn (gen_vec_cmpv2df (operands[0], operands[1], operands[2])); else gcc_unreachable (); From patchwork Tue Oct 1 13:27:08 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ilya Leoshkevich X-Patchwork-Id: 1169944 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Tue, 1 Oct 2019 14:28:32 +0100 Received: from d06av21.portsmouth.uk.ibm.com (d06av21.portsmouth.uk.ibm.com [9.149.105.232]) by b06avi18626390.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x91DS2wQ28770574 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Tue, 1 Oct 2019 13:28:02 GMT Received: from d06av21.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 14E105206C; Tue, 1 Oct 2019 13:28:31 +0000 (GMT) Received: from white.boeblingen.de.ibm.com (unknown [9.152.96.81]) by d06av21.portsmouth.uk.ibm.com (Postfix) with ESMTP id B1DF652059; Tue, 1 Oct 2019 13:28:30 +0000 (GMT) From: Ilya Leoshkevich To: gcc-patches@gcc.gnu.org Cc: richard.guenther@gmail.com, richard.sandiford@arm.com, segher@kernel.crashing.org, joseph@codesourcery.com, krebbel@linux.ibm.com, rdapp@linux.ibm.com, Ilya Leoshkevich Subject: [PATCH v4 6/7] S/390: Use signaling FP comparison instructions Date: Tue, 1 Oct 2019 15:27:08 +0200 In-Reply-To: <20191001132709.87257-1-iii@linux.ibm.com> References: <20191001132709.87257-1-iii@linux.ibm.com> MIME-Version: 1.0 x-cbid: 19100113-0028-0000-0000-000003A453B7 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19100113-0029-0000-0000-000024668128 Message-Id: <20191001132709.87257-7-iii@linux.ibm.com> X-IsSubscribed: yes dg-torture.exp=inf-compare-1.c is failing, because (qNaN > +Inf) comparison is compiled to CDB instruction, which does not signal an invalid operation exception. KDB should have been used instead. This patch introduces a new CCmode and a new pattern in order to generate signaling instructions in this and similar cases. gcc/ChangeLog: 2019-08-09 Ilya Leoshkevich PR target/77918 * config/s390/2827.md: Add new opcodes. * config/s390/2964.md: Likewise. * config/s390/3906.md: Likewise. * config/s390/8561.md: Likewise. * config/s390/s390-builtins.def (s390_vfchesb): Use the new vec_cmpgev4sf_quiet_nocc. (s390_vfchedb): Use the new vec_cmpgev2df_quiet_nocc. (s390_vfchsb): Use the new vec_cmpgtv4sf_quiet_nocc. (s390_vfchdb): Use the new vec_cmpgtv2df_quiet_nocc. (vec_cmplev4sf): Use the new vec_cmplev4sf_quiet_nocc. (vec_cmplev2df): Use the new vec_cmplev2df_quiet_nocc. (vec_cmpltv4sf): Use the new vec_cmpltv4sf_quiet_nocc. (vec_cmpltv2df): Use the new vec_cmpltv2df_quiet_nocc. * config/s390/s390-modes.def (CCSFPS): New mode. * config/s390/s390.c (s390_match_ccmode_set): Support CCSFPS. (s390_select_ccmode): Return CCSFPS for LT, LE, GT, GE and LTGT. (s390_branch_condition_mask): Reuse CCS for CCSFPS. (s390_expand_vec_compare): Use non-signaling patterns where necessary. (s390_reverse_condition): Support CCSFPS. * config/s390/s390.md (*cmp_ccsfps): New pattern. * config/s390/vector.md: (VFCMP_HW_OP): Remove. (asm_fcmp_op): Likewise. (*smaxv2df3_vx): Use pattern for quiet comparison. (*sminv2df3_vx): Likewise. (*vec_cmp_nocc): Remove. (*vec_cmpeq_quiet_nocc): New pattern. (vec_cmpgt_quiet_nocc): Likewise. (vec_cmplt_quiet_nocc): New expander. (vec_cmpge_quiet_nocc): New pattern. (vec_cmple_quiet_nocc): New expander. (*vec_cmpeq_signaling_nocc): New pattern. (*vec_cmpgt_signaling_nocc): Likewise. (*vec_cmpgt_signaling_finite_nocc): Likewise. (*vec_cmpge_signaling_nocc): Likewise. (*vec_cmpge_signaling_finite_nocc): Likewise. (vec_cmpungt): New expander. (vec_cmpunge): Likewise. (vec_cmpuneq): Use quiet patterns. (vec_cmpltgt): Allow only on z14+. (vec_cmpordered): Use quiet patterns. (vec_cmpunordered): Likewise. (VEC_CMP_EXPAND): Add ungt and unge. gcc/testsuite/ChangeLog: 2019-08-09 Ilya Leoshkevich * gcc.target/s390/vector/vec-scalar-cmp-1.c: Adjust expectations. --- gcc/config/s390/2827.md | 14 +- gcc/config/s390/2964.md | 13 +- gcc/config/s390/3906.md | 17 +- gcc/config/s390/8561.md | 19 +- gcc/config/s390/s390-builtins.def | 16 +- gcc/config/s390/s390-modes.def | 8 + gcc/config/s390/s390.c | 34 ++-- gcc/config/s390/s390.md | 14 ++ gcc/config/s390/vector.md | 171 +++++++++++++++--- .../gcc.target/s390/vector/vec-scalar-cmp-1.c | 8 +- 10 files changed, 240 insertions(+), 74 deletions(-) diff --git a/gcc/config/s390/2827.md b/gcc/config/s390/2827.md index 3f63f82284d..aafe8e27339 100644 --- a/gcc/config/s390/2827.md +++ b/gcc/config/s390/2827.md @@ -44,7 +44,7 @@ (define_insn_reservation "zEC12_normal_fp" 8 (and (eq_attr "cpu" "zEC12") - (eq_attr "mnemonic" "lnebr,sdbr,sebr,clfxtr,adbr,aebr,celfbr,clfebr,lpebr,msebr,lndbr,clfdbr,cebr,maebr,ltebr,clfdtr,cdlgbr,cxlftr,lpdbr,cdfbr,lcebr,clfxbr,msdbr,cdbr,madbr,meebr,clgxbr,clgdtr,ledbr,cegbr,cdlftr,cdlgtr,mdbr,clgebr,ltdbr,cdlfbr,cdgbr,clgxtr,lcdbr,celgbr,clgdbr,ldebr,cefbr,fidtr,fixtr,madb,msdb,mseb,fiebra,fidbra,aeb,mdb,seb,cdb,tcdb,sdb,adb,tceb,maeb,ceb,meeb,ldeb")) "nothing") + (eq_attr "mnemonic" "lnebr,sdbr,sebr,clfxtr,adbr,aebr,celfbr,clfebr,lpebr,msebr,lndbr,clfdbr,cebr,maebr,ltebr,clfdtr,cdlgbr,cxlftr,lpdbr,cdfbr,lcebr,clfxbr,msdbr,cdbr,madbr,meebr,clgxbr,clgdtr,ledbr,cegbr,cdlftr,cdlgtr,mdbr,clgebr,ltdbr,cdlfbr,cdgbr,clgxtr,lcdbr,celgbr,clgdbr,ldebr,cefbr,fidtr,fixtr,madb,msdb,mseb,fiebra,fidbra,aeb,mdb,seb,cdb,tcdb,sdb,adb,tceb,maeb,ceb,meeb,ldeb,keb,kebr,kdb,kdbr")) "nothing") (define_insn_reservation "zEC12_cgdbr" 2 (and (eq_attr "cpu" "zEC12") @@ -426,6 +426,10 @@ (and (eq_attr "cpu" "zEC12") (eq_attr "mnemonic" "cxbr")) "nothing") +(define_insn_reservation "zEC12_kxbr" 18 + (and (eq_attr "cpu" "zEC12") + (eq_attr "mnemonic" "kxbr")) "nothing") + (define_insn_reservation "zEC12_ddbr" 36 (and (eq_attr "cpu" "zEC12") (eq_attr "mnemonic" "ddbr")) "nothing") @@ -578,10 +582,18 @@ (and (eq_attr "cpu" "zEC12") (eq_attr "mnemonic" "cdtr")) "nothing") +(define_insn_reservation "zEC12_kdtr" 11 + (and (eq_attr "cpu" "zEC12") + (eq_attr "mnemonic" "kdtr")) "nothing") + (define_insn_reservation "zEC12_cxtr" 14 (and (eq_attr "cpu" "zEC12") (eq_attr "mnemonic" "cxtr")) "nothing") +(define_insn_reservation "zEC12_kxtr" 14 + (and (eq_attr "cpu" "zEC12") + (eq_attr "mnemonic" "kxtr")) "nothing") + (define_insn_reservation "zEC12_slbg" 3 (and (eq_attr "cpu" "zEC12") (eq_attr "mnemonic" "slbg")) "nothing") diff --git a/gcc/config/s390/2964.md b/gcc/config/s390/2964.md index a7897bcf58a..4396e3ba1c0 100644 --- a/gcc/config/s390/2964.md +++ b/gcc/config/s390/2964.md @@ -69,7 +69,7 @@ ng,ni,niy,ntstg,ny,o,og,oi,oiy,oy,s,sar,sdb,seb,sfpc,sg,sgf,sh,shy,sl,\ slb,slbg,slg,slgf,sly,sqdb,sqeb,st,stc,stcy,std,stdy,ste,stey,stg,stgrl,\ sth,sthrl,sthy,stoc,stocg,strl,strv,strvg,strvh,sty,sy,tabort,tm,tmy,vl,\ vlbb,vleb,vlef,vleg,vleh,vll,vllezb,vllezf,vllezg,vllezh,vllezlf,vlrepb,\ -vlrepf,vlrepg,vlreph,vst,vstl,x,xg,xi,xiy,xy") +vlrepf,vlrepg,vlreph,vst,vstl,x,xg,xi,xiy,xy,kdb") (const_int 1)] (const_int 0))) (define_attr "z13_unit_vfu" "" @@ -109,7 +109,8 @@ vuplhh,vuplhw,vupllb,vupllf,vupllh,vx,vzero,wcdgb,wcdlgb,wcgdb,wclgdb,wfadb,\ wfasb,wfaxb,wfcdb,wfcedb,wfcesb,wfcexbs,wfchdb,wfchedb,wfchesb,wfchexb,\ wfchexbs,wfchsb,wfchxb,wfchxbs,wfcsb,wfisb,wfixb,wflcdb,wflcsb,wflcxb,wflld,\ wflndb,wflnsb,wflnxb,wflpdb,wflpsb,wflpxb,wfmadb,wfmasb,wfmaxb,wfmdb,wfmsb,\ -wfmsdb,wfmssb,wfmsxb,wfmxb,wfsdb,wfssb,wfsxb,wldeb,wledb") +wfmsdb,wfmssb,wfmsxb,wfmxb,wfsdb,wfssb,wfsxb,wldeb,wledb,kebr,kdb,kdbr,kxbr,\ +kdtr,kxtr,wfkdb,wfksb") (const_int 1)] (const_int 0))) (define_attr "z13_cracked" "" @@ -131,7 +132,7 @@ stmg,stmy,tbegin,tbeginc") cxtr,dlgr,dlr,dr,dsgfr,dsgr,dxbr,dxtr,fixbr,fixbra,fixtr,flogr,lcxbr,lnxbr,\ lpxbr,ltxbr,ltxtr,lxdb,lxdbr,lxdtr,lxeb,lxebr,m,madb,maeb,maebr,mfy,ml,mlg,\ mlgr,mlr,mr,msdb,mseb,msebr,mvc,mxbr,mxtr,oc,sfpc,slb,slbg,slbgr,slbr,\ -sqxbr,sxbr,sxtr,tabort,tcxb,tdcxt,tend,xc") +sqxbr,sxbr,sxtr,tabort,tcxb,tdcxt,tend,xc,kxbr,kxtr") (const_int 1)] (const_int 0))) (define_attr "z13_endgroup" "" @@ -198,7 +199,7 @@ vchlhs,vfcedbs,vfcesbs,vfchdbs,vfchedbs,vfchesbs,vfchsbs,vfeeb,vfeef,vfeeh,\ vfeneb,vfenef,vfeneh,vfenezb,vfenezf,vfenezh,vftcidb,vftcisb,vistrb,vistrf,\ vistrh,vllezb,vllezf,vllezg,vllezh,vllezlf,vlrepb,vlrepf,vlrepg,vlreph,vlvgp,\ vpklsfs,vpklsgs,vpklshs,vpksfs,vpksgs,vpkshs,vslb,vsrab,vsrlb,wfcdb,wfcexbs,\ -wfchexbs,wfchxbs,wfcsb")) "nothing") +wfchexbs,wfchxbs,wfcsb,kebr,kdb,kdbr,wfkdb,wfksb")) "nothing") (define_insn_reservation "z13_3" 3 (and (eq_attr "cpu" "z13") @@ -232,7 +233,7 @@ wfmdb,wfmsb,wfmsdb,wfmssb,wfmsxb,wfmxb,wfsdb,wfssb,wfsxb,wldeb,wledb")) "nothing (and (eq_attr "cpu" "z13") (eq_attr "mnemonic" "adtr,cdtr,fidtr,ldetr,msg,msgr,sdtr,tdcdt,tdcet,\ vcdgb,vcdlgb,vcgdb,vclgdb,vfadb,vfasb,vfidb,vfisb,vfmadb,vfmasb,vfmdb,vfmsb,\ -vfmsdb,vfmssb,vfsdb,vfssb,vldeb,vledb")) "nothing") +vfmsdb,vfmssb,vfsdb,vfssb,vldeb,vledb,kdtr")) "nothing") (define_insn_reservation "z13_8" 8 (and (eq_attr "cpu" "z13") @@ -254,7 +255,7 @@ celgbr,flogr,m,madb,maeb,maebr,mfy,ml,mlr,mr,msdb,mseb,msebr")) "nothing") (define_insn_reservation "z13_12" 12 (and (eq_attr "cpu" "z13") (eq_attr "mnemonic" "cfdbr,cfebr,cgdbr,cgebr,clfdbr,clfebr,clgdbr,\ -clgebr,cxbr,cxtr,mlg,mlgr,tcxb,tdcxt")) "nothing") +clgebr,cxbr,cxtr,mlg,mlgr,tcxb,tdcxt,kxbr,kxtr")) "nothing") (define_insn_reservation "z13_13" 13 (and (eq_attr "cpu" "z13") diff --git a/gcc/config/s390/3906.md b/gcc/config/s390/3906.md index 8cb4565ee22..1212d8b61f1 100644 --- a/gcc/config/s390/3906.md +++ b/gcc/config/s390/3906.md @@ -71,7 +71,7 @@ sgh,sh,shy,sl,slb,slbg,slg,slgf,sly,sqdb,sqeb,st,stc,stcy,std,stdy,ste,\ stey,stg,stgrl,sth,sthrl,sthy,stoc,stocg,strl,strv,strvg,strvh,sty,sy,\ tabort,tm,tmy,vl,vlbb,vleb,vlef,vleg,vleh,vll,vllezb,vllezf,vllezg,vllezh,\ vllezlf,vlrepb,vlrepf,vlrepg,vlreph,vlrl,vlrlr,vst,vstl,vstrl,vstrlr,x,xg,xi,\ -xiy,xy") +xiy,xy,kdb") (const_int 1)] (const_int 0))) (define_attr "z14_unit_vfu" "" @@ -113,7 +113,8 @@ wfadb,wfasb,wfaxb,wfcdb,wfcedb,wfcesb,wfcexbs,wfchdb,wfchedb,wfchesb,\ wfchexb,wfchexbs,wfchsb,wfchxb,wfchxbs,wfcsb,wfisb,wfixb,wflcdb,wflcsb,wflcxb,\ wflld,wflndb,wflnsb,wflnxb,wflpdb,wflpsb,wflpxb,wfmadb,wfmasb,wfmaxb,\ wfmaxxb,wfmdb,wfminxb,wfmsb,wfmsdb,wfmssb,wfmsxb,wfmxb,wfnmaxb,wfnmsxb,wfsdb,\ -wfssb,wfsxb,wldeb,wledb") +wfssb,wfsxb,wldeb,wledb,kebr,kdb,kdbr,kxbr,kdtr,kxtr,wfkdb,wfksb,vfkesb,\ +vfkedb,vfkhsb,vfkhdb,wfkhxb,vfkhesb,vfkhedb,wfkhexb") (const_int 1)] (const_int 0))) (define_attr "z14_cracked" "" @@ -135,7 +136,7 @@ stmg,stmy,tbegin,tbeginc") cxtr,dlgr,dlr,dr,dsgfr,dsgr,dxbr,dxtr,fixbr,fixbra,fixtr,flogr,lcxbr,lnxbr,\ lpxbr,ltxbr,ltxtr,lxdb,lxdbr,lxdtr,lxeb,lxebr,m,madb,maeb,maebr,mfy,mg,mgrk,\ ml,mlg,mlgr,mlr,mr,msdb,mseb,msebr,mvc,mxbr,mxtr,oc,ppa,sfpc,slb,slbg,\ -slbgr,slbr,sqxbr,sxbr,sxtr,tabort,tcxb,tdcxt,tend,xc") +slbgr,slbr,sqxbr,sxbr,sxtr,tabort,tcxb,tdcxt,tend,xc,kxbr,kxtr") (const_int 1)] (const_int 0))) (define_attr "z14_endgroup" "" @@ -192,7 +193,8 @@ vrepig,vrepih,vsb,vsbiq,vscbib,vscbif,vscbig,vscbih,vscbiq,vsegb,vsegf,vsegh,\ vsel,vsf,vsg,vsh,vsl,vslb,vsldb,vsq,vsra,vsrab,vsrl,vsrlb,vuphb,vuphf,\ vuphh,vuplb,vuplf,vuplhb,vuplhf,vuplhh,vuplhw,vupllb,vupllf,vupllh,vx,vzero,\ wfcedb,wfcesb,wfchdb,wfchedb,wfchesb,wfchexb,wfchsb,wfchxb,wflcdb,wflcsb,\ -wflcxb,wflndb,wflnsb,wflnxb,wflpdb,wflpsb,wflpxb,wfmaxxb,wfminxb,xi,xiy")) "nothing") +wflcxb,wflndb,wflnsb,wflnxb,wflpdb,wflpsb,wflpxb,wfmaxxb,wfminxb,xi,xiy,\ +vfkesb,vfkedb,vfkhsb,vfkhdb,wfkhxb,vfkhesb,vfkhedb,wfkhexb")) "nothing") (define_insn_reservation "z14_2" 2 (and (eq_attr "cpu" "z14") @@ -204,7 +206,7 @@ vchlhs,vfcedbs,vfcesbs,vfchdbs,vfchedbs,vfchesbs,vfchsbs,vfeeb,vfeef,vfeeh,\ vfeneb,vfenef,vfeneh,vfenezb,vfenezf,vfenezh,vftcidb,vftcisb,vistrb,vistrf,\ vistrh,vlgvf,vlgvg,vlgvh,vllezb,vllezf,vllezg,vllezh,vllezlf,vlrepb,vlrepf,\ vlrepg,vlreph,vlrl,vlvgp,vpklsfs,vpklsgs,vpklshs,vpksfs,vpksgs,vpkshs,wfcdb,\ -wfcexbs,wfchexbs,wfchxbs,wfcsb")) "nothing") +wfcexbs,wfchexbs,wfchxbs,wfcsb,kebr,kdb,kdbr,wfkdb,wfksb")) "nothing") (define_insn_reservation "z14_3" 3 (and (eq_attr "cpu" "z14") @@ -238,7 +240,8 @@ wfmasb,wfmdb,wfmsb,wfmsdb,wfmssb,wfsdb,wfssb,wldeb,wledb")) "nothing") (define_insn_reservation "z14_7" 7 (and (eq_attr "cpu" "z14") (eq_attr "mnemonic" "adtr,cdtr,fidtr,ldetr,msgrkc,sdtr,tdcdt,tdcet,\ -vfasb,vfisb,vfmasb,vfmsb,vfmssb,vfnmssb,vfssb,vgef,vgeg,wflld")) "nothing") +vfasb,vfisb,vfmasb,vfmsb,vfmssb,vfnmssb,vfssb,vgef,vgeg,wflld,kdtr")) +"nothing") (define_insn_reservation "z14_8" 8 (and (eq_attr "cpu" "z14") @@ -261,7 +264,7 @@ celgbr,madb,maeb,maebr,msdb,mseb,msebr,vscef,vsceg")) "nothing") (define_insn_reservation "z14_12" 12 (and (eq_attr "cpu" "z14") (eq_attr "mnemonic" "cfdbr,cfebr,cgdbr,cgebr,clfdbr,clfebr,clgdbr,\ -clgebr,cxbr,cxtr,tcxb,tdcxt")) "nothing") +clgebr,cxbr,cxtr,tcxb,tdcxt,kxbr,kxtr")) "nothing") (define_insn_reservation "z14_13" 13 (and (eq_attr "cpu" "z14") diff --git a/gcc/config/s390/8561.md b/gcc/config/s390/8561.md index e5a345f4dba..91a92b6bc5c 100644 --- a/gcc/config/s390/8561.md +++ b/gcc/config/s390/8561.md @@ -70,7 +70,7 @@ sar,sdb,seb,sfpc,sg,sgf,sgh,sh,shy,sl,slb,slbg,slg,slgf,sly,sqdb,sqeb,st,\ stc,stcy,std,stdy,ste,stey,stg,stgrl,sth,sthrl,sthy,stoc,stocg,strl,strv,\ strvg,strvh,sty,sy,tabort,tm,tmy,vl,vlbb,vleb,vlef,vleg,vleh,vll,vllezb,\ vllezf,vllezg,vllezh,vllezlf,vlrepb,vlrepf,vlrepg,vlreph,vlrl,vlrlr,vst,\ -vstef,vsteg,vstl,vstrl,vstrlr,x,xg,xi,xiy,xy") +vstef,vsteg,vstl,vstrl,vstrlr,x,xg,xi,xiy,xy,keb,kdb") (const_int 1)] (const_int 0))) (define_attr "arch13_unit_vfu" "" @@ -112,7 +112,9 @@ vupllf,vupllh,vx,vzero,wfadb,wfasb,wfaxb,wfcdb,wfcedb,wfcesb,wfcexb,wfcexbs,\ wfchdb,wfchedb,wfchesb,wfchexb,wfchexbs,wfchsb,wfchxb,wfchxbs,wfcsb,wfidb,\ wfisb,wfixb,wflcdb,wflcsb,wflcxb,wflld,wflndb,wflnsb,wflnxb,wflpdb,wflpsb,\ wflpxb,wfmadb,wfmasb,wfmaxb,wfmaxxb,wfmdb,wfminxb,wfmsb,wfmsdb,wfmssb,wfmsxb,\ -wfmxb,wfnmaxb,wfnmsxb,wfsdb,wfssb,wfsxb,wldeb,wledb") +wfmxb,wfnmaxb,wfnmsxb,wfsdb,wfssb,wfsxb,wldeb,wledb,keb,kebr,kdb,kdbr,kxbr,\ +kdtr,kxtr,wfkdb,wfksb,vfkesb,vfkedb,wfkexb,vfkhsb,vfkhdb,wfkhxb,vfkhesb,\ +vfkhedb,wfkhexb") (const_int 1)] (const_int 0))) (define_attr "arch13_cracked" "" @@ -134,7 +136,7 @@ stam,stm,stmg,stmy,tbegin,tbeginc") cxtr,dlgr,dlr,dr,dsgfr,dsgr,dxbr,dxtr,fixbr,fixbra,fixtr,flogr,lcxbr,lnxbr,\ lpxbr,ltxbr,ltxtr,lxdb,lxdbr,lxdtr,lxeb,lxebr,m,madb,maeb,maebr,mfy,mg,mgrk,\ ml,mlg,mlgr,mlr,mr,msdb,mseb,msebr,mvc,mxbr,mxtr,nc,oc,ppa,sfpc,slb,slbg,\ -slbgr,slbr,sqxbr,sxbr,sxtr,tabort,tcxb,tdcxt,tend,xc") +slbgr,slbr,sqxbr,sxbr,sxtr,tabort,tcxb,tdcxt,tend,xc,kxbr,kxtr") (const_int 1)] (const_int 0))) (define_attr "arch13_endgroup" "" @@ -194,7 +196,8 @@ vsel,vsf,vsg,vsh,vsl,vslb,vsldb,vsq,vsra,vsrab,vsrl,vsrlb,vuphb,vuphf,\ vuphh,vuplb,vuplf,vuplhb,vuplhf,vuplhh,vuplhw,vupllb,vupllf,vupllh,vx,vzero,\ wfcedb,wfcesb,wfcexb,wfchdb,wfchedb,wfchesb,wfchexb,wfchsb,wfchxb,wflcdb,\ wflcsb,wflcxb,wflndb,wflnsb,wflnxb,wflpdb,wflpsb,wflpxb,wfmaxxb,wfminxb,xi,\ -xiy")) "nothing") +xiy,vfkesb,vfkedb,wfkexb,vfkhsb,vfkhdb,wfkhxb,vfkhesb,vfkhedb,wfkhexb")) +"nothing") (define_insn_reservation "arch13_2" 2 (and (eq_attr "cpu" "arch13") @@ -206,7 +209,8 @@ vchlhs,vfcedbs,vfcesbs,vfchdbs,vfchedbs,vfchesbs,vfchsbs,vfeeb,vfeef,vfeeh,\ vfeneb,vfenef,vfeneh,vfenezb,vfenezf,vfenezh,vftcidb,vftcisb,vistrb,vistrf,\ vistrh,vlgvb,vlgvf,vlgvg,vlgvh,vllezb,vllezf,vllezg,vllezh,vllezlf,vlrepb,\ vlrepf,vlrepg,vlreph,vlrl,vlvgp,vpklsfs,vpklsgs,vpklshs,vpksfs,vpksgs,vpkshs,\ -wfcdb,wfcexbs,wfchexbs,wfchxbs,wfcsb")) "nothing") +wfcdb,wfcexbs,wfchexbs,wfchxbs,wfcsb,keb,kebr,kdb,kdbr,wfkdb,wfksb")) +"nothing") (define_insn_reservation "arch13_3" 3 (and (eq_attr "cpu" "arch13") @@ -240,7 +244,7 @@ wfmasb,wfmdb,wfmsb,wfmsdb,wfmssb,wfsdb,wfssb,wldeb,wledb")) "nothing") (define_insn_reservation "arch13_7" 7 (and (eq_attr "cpu" "arch13") (eq_attr "mnemonic" "adtr,cdtr,fidtr,ldetr,ltdtr,msgrkc,sdtr,tdcdt,\ -tdcet,vgef,vgeg")) "nothing") +tdcet,vgef,vgeg,kdtr")) "nothing") (define_insn_reservation "arch13_8" 8 (and (eq_attr "cpu" "arch13") @@ -263,7 +267,8 @@ clgebr,mg,mgrk,mlg,mlgr")) "nothing") (define_insn_reservation "arch13_12" 12 (and (eq_attr "cpu" "arch13") -(eq_attr "mnemonic" "cxbr,cxftr,cxlftr,cxtr,tcxb,tdcxt")) "nothing") +(eq_attr "mnemonic" "cxbr,cxftr,cxlftr,cxtr,tcxb,tdcxt,kxbr,kxtr")) +"nothing") (define_insn_reservation "arch13_13" 13 (and (eq_attr "cpu" "arch13") diff --git a/gcc/config/s390/s390-builtins.def b/gcc/config/s390/s390-builtins.def index cfc69651b0d..013cac0206a 100644 --- a/gcc/config/s390/s390-builtins.def +++ b/gcc/config/s390/s390-builtins.def @@ -1495,8 +1495,8 @@ B_DEF (vec_cmpgev4si, vec_cmpgev4si, 0, B_DEF (vec_cmpgeuv4si, vec_cmpgeuv4si, 0, B_INT | B_VX, 0, BT_FN_V4SI_UV4SI_UV4SI) B_DEF (vec_cmpgev2di, vec_cmpgev2di, 0, B_INT | B_VX, 0, BT_FN_V2DI_UV2DI_UV2DI) B_DEF (vec_cmpgeuv2di, vec_cmpgeuv2di, 0, B_INT | B_VX, 0, BT_FN_V2DI_UV2DI_UV2DI) -B_DEF (s390_vfchesb, vec_cmpgev4sf, 0, B_VXE, 0, BT_FN_V4SI_V4SF_V4SF) -B_DEF (s390_vfchedb, vec_cmpgev2df, 0, B_VX, 0, BT_FN_V2DI_V2DF_V2DF) +B_DEF (s390_vfchesb, vec_cmpgev4sf_quiet_nocc,0, B_VXE, 0, BT_FN_V4SI_V4SF_V4SF) +B_DEF (s390_vfchedb, vec_cmpgev2df_quiet_nocc,0, B_VX, 0, BT_FN_V2DI_V2DF_V2DF) OB_DEF (s390_vec_cmpgt, s390_vec_cmpgt_s8, s390_vec_cmpgt_dbl, B_VX, BT_FN_OV4SI_OV4SI_OV4SI) OB_DEF_VAR (s390_vec_cmpgt_s8, s390_vchb, 0, 0, BT_OV_BV16QI_V16QI_V16QI) @@ -1518,8 +1518,8 @@ B_DEF (s390_vchf, vec_cmpgtv4si, 0, B_DEF (s390_vchlf, vec_cmpgtuv4si, 0, B_VX, 0, BT_FN_V4SI_UV4SI_UV4SI) B_DEF (s390_vchg, vec_cmpgtv2di, 0, B_VX, 0, BT_FN_V2DI_V2DI_V2DI) B_DEF (s390_vchlg, vec_cmpgtuv2di, 0, B_VX, 0, BT_FN_V2DI_UV2DI_UV2DI) -B_DEF (s390_vfchsb, vec_cmpgtv4sf, 0, B_VXE, 0, BT_FN_V4SI_V4SF_V4SF) -B_DEF (s390_vfchdb, vec_cmpgtv2df, 0, B_VX, 0, BT_FN_V2DI_V2DF_V2DF) +B_DEF (s390_vfchsb, vec_cmpgtv4sf_quiet_nocc,0, B_VXE, 0, BT_FN_V4SI_V4SF_V4SF) +B_DEF (s390_vfchdb, vec_cmpgtv2df_quiet_nocc,0, B_VX, 0, BT_FN_V2DI_V2DF_V2DF) OB_DEF (s390_vec_cmple, s390_vec_cmple_s8, s390_vec_cmple_dbl, B_VX, BT_FN_OV4SI_OV4SI_OV4SI) OB_DEF_VAR (s390_vec_cmple_s8, vec_cmplev16qi, 0, 0, BT_OV_BV16QI_V16QI_V16QI) @@ -1541,8 +1541,8 @@ B_DEF (vec_cmplev4si, vec_cmplev4si, 0, B_DEF (vec_cmpleuv4si, vec_cmpleuv4si, 0, B_INT | B_VX, 0, BT_FN_V4SI_UV4SI_UV4SI) B_DEF (vec_cmplev2di, vec_cmplev2di, 0, B_INT | B_VX, 0, BT_FN_V2DI_UV2DI_UV2DI) B_DEF (vec_cmpleuv2di, vec_cmpleuv2di, 0, B_INT | B_VX, 0, BT_FN_V2DI_UV2DI_UV2DI) -B_DEF (vec_cmplev4sf, vec_cmplev4sf, 0, B_INT | B_VXE, 0, BT_FN_V4SI_V4SF_V4SF) -B_DEF (vec_cmplev2df, vec_cmplev2df, 0, B_INT | B_VX, 0, BT_FN_V2DI_V2DF_V2DF) +B_DEF (vec_cmplev4sf, vec_cmplev4sf_quiet_nocc,0, B_INT | B_VXE, 0, BT_FN_V4SI_V4SF_V4SF) +B_DEF (vec_cmplev2df, vec_cmplev2df_quiet_nocc,0, B_INT | B_VX, 0, BT_FN_V2DI_V2DF_V2DF) OB_DEF (s390_vec_cmplt, s390_vec_cmplt_s8, s390_vec_cmplt_dbl, B_VX, BT_FN_OV4SI_OV4SI_OV4SI) OB_DEF_VAR (s390_vec_cmplt_s8, vec_cmpltv16qi, 0, 0, BT_OV_BV16QI_V16QI_V16QI) @@ -1564,8 +1564,8 @@ B_DEF (vec_cmpltv4si, vec_cmpltv4si, 0, B_DEF (vec_cmpltuv4si, vec_cmpltuv4si, 0, B_INT | B_VX, 0, BT_FN_V4SI_UV4SI_UV4SI) B_DEF (vec_cmpltv2di, vec_cmpltv2di, 0, B_INT | B_VX, 0, BT_FN_V2DI_UV2DI_UV2DI) B_DEF (vec_cmpltuv2di, vec_cmpltuv2di, 0, B_INT | B_VX, 0, BT_FN_V2DI_UV2DI_UV2DI) -B_DEF (vec_cmpltv4sf, vec_cmpltv4sf, 0, B_INT | B_VXE, 0, BT_FN_V4SI_V4SF_V4SF) -B_DEF (vec_cmpltv2df, vec_cmpltv2df, 0, B_INT | B_VX, 0, BT_FN_V2DI_V2DF_V2DF) +B_DEF (vec_cmpltv4sf, vec_cmpltv4sf_quiet_nocc,0, B_INT | B_VXE, 0, BT_FN_V4SI_V4SF_V4SF) +B_DEF (vec_cmpltv2df, vec_cmpltv2df_quiet_nocc,0, B_INT | B_VX, 0, BT_FN_V2DI_V2DF_V2DF) OB_DEF (s390_vec_cntlz, s390_vec_cntlz_s8, s390_vec_cntlz_u64, B_VX, BT_FN_OV4SI_OV4SI) OB_DEF_VAR (s390_vec_cntlz_s8, s390_vclzb, 0, 0, BT_OV_UV16QI_V16QI) diff --git a/gcc/config/s390/s390-modes.def b/gcc/config/s390/s390-modes.def index 7b7c1141449..2d9cd9b5945 100644 --- a/gcc/config/s390/s390-modes.def +++ b/gcc/config/s390/s390-modes.def @@ -52,6 +52,8 @@ CCS: EQ LT GT UNORDERED (LTGFR, LTGR, LTR, ICM/Y, ADB/R, AEB/R, SDB/R, SEB/R, SRAG, SRA, SRDA) CCSR: EQ GT LT UNORDERED (CGF/R, CH/Y) +CCSFPS: EQ GT LT UNORDERED (KEB/R, KDB/R, KXBR, KDTR, + KXTR, WFK) Condition codes resulting from add with overflow @@ -140,6 +142,11 @@ around. The following both modes can be considered as CCS and CCU modes with exchanged operands. +CCSFPS + +This mode is used for signaling rtxes: LT, LE, GT, GE and LTGT. + + CCL1, CCL2 These modes represent the result of overflow checks. @@ -226,6 +233,7 @@ CC_MODE (CCU); CC_MODE (CCUR); CC_MODE (CCS); CC_MODE (CCSR); +CC_MODE (CCSFPS); CC_MODE (CCT); CC_MODE (CCT1); CC_MODE (CCT2); diff --git a/gcc/config/s390/s390.c b/gcc/config/s390/s390.c index 062cbd8099d..0820d4c0f20 100644 --- a/gcc/config/s390/s390.c +++ b/gcc/config/s390/s390.c @@ -1376,6 +1376,7 @@ s390_match_ccmode_set (rtx set, machine_mode req_mode) case E_CCZ1mode: case E_CCSmode: case E_CCSRmode: + case E_CCSFPSmode: case E_CCUmode: case E_CCURmode: case E_CCOmode: @@ -1559,6 +1560,12 @@ s390_select_ccmode (enum rtx_code code, rtx op0, rtx op1) else return CCAPmode; } + + /* Fall through. */ + case LTGT: + if (HONOR_NANS (op0) || HONOR_NANS (op1)) + return CCSFPSmode; + /* Fall through. */ case UNORDERED: case ORDERED: @@ -1567,7 +1574,6 @@ s390_select_ccmode (enum rtx_code code, rtx op0, rtx op1) case UNLT: case UNGE: case UNGT: - case LTGT: if ((GET_CODE (op0) == SIGN_EXTEND || GET_CODE (op0) == ZERO_EXTEND) && GET_CODE (op1) != CONST_INT) return CCSRmode; @@ -2082,6 +2088,7 @@ s390_branch_condition_mask (rtx code) break; case E_CCSmode: + case E_CCSFPSmode: switch (GET_CODE (code)) { case EQ: return CC0; @@ -6504,18 +6511,23 @@ s390_expand_vec_compare (rtx target, enum rtx_code cond, { /* NE a != b -> !(a == b) */ case NE: cond = EQ; neg_p = true; break; - /* UNGT a u> b -> !(b >= a) */ - case UNGT: cond = GE; neg_p = true; swap_p = true; break; - /* UNGE a u>= b -> !(b > a) */ - case UNGE: cond = GT; neg_p = true; swap_p = true; break; - /* LE: a <= b -> b >= a */ + case UNGT: + emit_insn (gen_vec_cmpungt (target, cmp_op1, cmp_op2)); + return; + case UNGE: + emit_insn (gen_vec_cmpunge (target, cmp_op1, cmp_op2)); + return; case LE: cond = GE; swap_p = true; break; - /* UNLE: a u<= b -> !(a > b) */ - case UNLE: cond = GT; neg_p = true; break; + /* UNLE: (a u<= b) -> (b u>= a). */ + case UNLE: + emit_insn (gen_vec_cmpunge (target, cmp_op2, cmp_op1)); + return; /* LT: a < b -> b > a */ case LT: cond = GT; swap_p = true; break; - /* UNLT: a u< b -> !(a >= b) */ - case UNLT: cond = GE; neg_p = true; break; + /* UNLT: (a u< b) -> (b u> a). */ + case UNLT: + emit_insn (gen_vec_cmpungt (target, cmp_op2, cmp_op1)); + return; case UNEQ: emit_insn (gen_vec_cmpuneq (target, cmp_op1, cmp_op2)); return; @@ -6678,7 +6690,7 @@ s390_reverse_condition (machine_mode mode, enum rtx_code code) { /* Reversal of FP compares takes care -- an ordered compare becomes an unordered compare and vice versa. */ - if (mode == CCVFALLmode || mode == CCVFANYmode) + if (mode == CCVFALLmode || mode == CCVFANYmode || mode == CCSFPSmode) return reverse_condition_maybe_unordered (code); else if (mode == CCVIALLmode || mode == CCVIANYmode) return reverse_condition (code); diff --git a/gcc/config/s390/s390.md b/gcc/config/s390/s390.md index e4516f6c378..bf3e051dbae 100644 --- a/gcc/config/s390/s390.md +++ b/gcc/config/s390/s390.md @@ -1424,6 +1424,20 @@ (set_attr "cpu_facility" "*,*,vx,vxe") (set_attr "enabled" "*,,,")]) +(define_insn "*cmp_ccsfps" + [(set (reg CC_REGNUM) + (compare (match_operand:FP 0 "register_operand" "f,f,v,v") + (match_operand:FP 1 "general_operand" "f,R,v,v")))] + "s390_match_ccmode (insn, CCSFPSmode) && TARGET_HARD_FLOAT" + "@ + kr\t%0,%1 + kb\t%0,%1 + wfkdb\t%0,%1 + wfksb\t%0,%1" + [(set_attr "op_type" "RRE,RXE,VRR,VRR") + (set_attr "cpu_facility" "*,*,vx,vxe") + (set_attr "enabled" "*,,,")]) + ; Compare and Branch instructions ; cij, cgij, crj, cgrj, cfi, cgfi, cr, cgr diff --git a/gcc/config/s390/vector.md b/gcc/config/s390/vector.md index 15b0e7f1802..f3a7dcc6f31 100644 --- a/gcc/config/s390/vector.md +++ b/gcc/config/s390/vector.md @@ -168,10 +168,6 @@ (define_mode_attr vec_halfnumelts [(V4SF "V2SF") (V4SI "V2SI")]) -; The comparisons not setting CC iterate over the rtx code. -(define_code_iterator VFCMP_HW_OP [eq gt ge]) -(define_code_attr asm_fcmp_op [(eq "e") (gt "h") (ge "he")]) - ; Comparison operators on int and fp compares which are directly @@ -1377,7 +1373,8 @@ "#" "&& 1" [(set (match_dup 3) - (gt:V2DI (match_dup 1) (match_dup 2))) + (not:V2DI + (unge:V2DI (match_dup 2) (match_dup 1)))) (set (match_dup 0) (if_then_else:V2DF (eq (match_dup 3) (match_dup 4)) @@ -1412,7 +1409,8 @@ "#" "&& 1" [(set (match_dup 3) - (gt:V2DI (match_dup 1) (match_dup 2))) + (not:V2DI + (unge:V2DI (match_dup 2) (match_dup 1)))) (set (match_dup 0) (if_then_else:V2DF (eq (match_dup 3) (match_dup 4)) @@ -1466,27 +1464,134 @@ ;; Floating point compares ;; -; EQ, GT, GE -; vfcesb, vfcedb, wfcexb, vfchsb, vfchdb, wfchxb, vfchesb, vfchedb, wfchexb -(define_insn "*vec_cmp_nocc" - [(set (match_operand: 0 "register_operand" "=v") - (VFCMP_HW_OP: (match_operand:VFT 1 "register_operand" "v") - (match_operand:VFT 2 "register_operand" "v")))] - "TARGET_VX" - "fcb\t%v0,%v1,%v2" +; vfcesb, vfcedb, wfcexb: non-signaling "==" comparison (a == b) +(define_insn "*vec_cmpeq_quiet_nocc" + [(set (match_operand: 0 "register_operand" "=v") + (eq: (match_operand:VFT 1 "register_operand" "v") + (match_operand:VFT 2 "register_operand" "v")))] + "TARGET_VX" + "fceb\t%v0,%v1,%v2" + [(set_attr "op_type" "VRR")]) + +; vfchsb, vfchdb, wfchxb: non-signaling > comparison (!(b u>= a)) +(define_insn "vec_cmpgt_quiet_nocc" + [(set (match_operand: 0 "register_operand" "=v") + (not: + (unge: (match_operand:VFT 2 "register_operand" "v") + (match_operand:VFT 1 "register_operand" "v"))))] + "TARGET_VX" + "fchb\t%v0,%v1,%v2" + [(set_attr "op_type" "VRR")]) + +(define_expand "vec_cmplt_quiet_nocc" + [(set (match_operand: 0 "register_operand" "=v") + (not: + (unge: (match_operand:VFT 1 "register_operand" "v") + (match_operand:VFT 2 "register_operand" "v"))))] + "TARGET_VX") + +; vfchesb, vfchedb, wfchexb: non-signaling >= comparison (!(a u< b)) +(define_insn "vec_cmpge_quiet_nocc" + [(set (match_operand: 0 "register_operand" "=v") + (not: + (unlt: (match_operand:VFT 1 "register_operand" "v") + (match_operand:VFT 2 "register_operand" "v"))))] + "TARGET_VX" + "fcheb\t%v0,%v1,%v2" + [(set_attr "op_type" "VRR")]) + +(define_expand "vec_cmple_quiet_nocc" + [(set (match_operand: 0 "register_operand" "=v") + (not: + (unlt: (match_operand:VFT 2 "register_operand" "v") + (match_operand:VFT 1 "register_operand" "v"))))] + "TARGET_VX") + +; vfkesb, vfkedb, wfkexb: signaling == comparison ((a >= b) & (b >= a)) +(define_insn "*vec_cmpeq_signaling_nocc" + [(set (match_operand: 0 "register_operand" "=v") + (and: + (ge: (match_operand:VFT 1 "register_operand" "v") + (match_operand:VFT 2 "register_operand" "v")) + (ge: (match_dup 2) + (match_dup 1))))] + "TARGET_VXE" + "fkeb\t%v0,%v1,%v2" + [(set_attr "op_type" "VRR")]) + +; vfkhsb, vfkhdb, wfkhxb: signaling > comparison (a > b) +(define_insn "*vec_cmpgt_signaling_nocc" + [(set (match_operand: 0 "register_operand" "=v") + (gt: (match_operand:VFT 1 "register_operand" "v") + (match_operand:VFT 2 "register_operand" "v")))] + "TARGET_VXE" + "fkhb\t%v0,%v1,%v2" + [(set_attr "op_type" "VRR")]) + +(define_insn "*vec_cmpgt_signaling_finite_nocc" + [(set (match_operand: 0 "register_operand" "=v") + (gt: (match_operand:VFT 1 "register_operand" "v") + (match_operand:VFT 2 "register_operand" "v")))] + "TARGET_VX && !TARGET_VXE && flag_finite_math_only" + "fchb\t%v0,%v1,%v2" + [(set_attr "op_type" "VRR")]) + +; vfkhesb, vfkhedb, wfkhexb: signaling >= comparison (a >= b) +(define_insn "*vec_cmpge_signaling_nocc" + [(set (match_operand: 0 "register_operand" "=v") + (ge: (match_operand:VFT 1 "register_operand" "v") + (match_operand:VFT 2 "register_operand" "v")))] + "TARGET_VXE" + "fkheb\t%v0,%v1,%v2" + [(set_attr "op_type" "VRR")]) + +(define_insn "*vec_cmpge_signaling_finite_nocc" + [(set (match_operand: 0 "register_operand" "=v") + (ge: (match_operand:VFT 1 "register_operand" "v") + (match_operand:VFT 2 "register_operand" "v")))] + "TARGET_VX && !TARGET_VXE && flag_finite_math_only" + "fcheb\t%v0,%v1,%v2" [(set_attr "op_type" "VRR")]) ; Expanders for not directly supported comparisons +; Signaling comparisons must be expressed via signaling rtxes only, +; and quiet comparisons must be expressed via quiet rtxes only. + +; UNGT a u> b -> !!(b u< a) +(define_expand "vec_cmpungt" + [(set (match_operand: 0 "register_operand" "=v") + (not: + (unlt: (match_operand:VFT 2 "register_operand" "v") + (match_operand:VFT 1 "register_operand" "v")))) + (set (match_dup 0) + (not: (match_dup 0)))] + "TARGET_VX") -; UNEQ a u== b -> !(a > b | b > a) +; UNGE a u>= b -> !!(a u>= b) +(define_expand "vec_cmpunge" + [(set (match_operand: 0 "register_operand" "=v") + (not: + (unge: (match_operand:VFT 1 "register_operand" "v") + (match_operand:VFT 2 "register_operand" "v")))) + (set (match_dup 0) + (not: (match_dup 0)))] + "TARGET_VX") + +; UNEQ a u== b -> !(!(a u>= b) | !(b u>= a)) (define_expand "vec_cmpuneq" - [(set (match_operand: 0 "register_operand" "=v") - (gt: (match_operand:VFT 1 "register_operand" "v") - (match_operand:VFT 2 "register_operand" "v"))) - (set (match_dup 3) - (gt: (match_dup 2) (match_dup 1))) - (set (match_dup 0) (ior: (match_dup 0) (match_dup 3))) - (set (match_dup 0) (not: (match_dup 0)))] + [(set (match_operand: 0 "register_operand" "=v") + (not: + (unge: (match_operand:VFT 1 "register_operand" "v") + (match_operand:VFT 2 "register_operand" "v")))) + (set (match_dup 3) + (not: + (unge: (match_dup 2) + (match_dup 1)))) + (set (match_dup 0) + (ior: (match_dup 0) + (match_dup 3))) + (set (match_dup 0) + (not: (match_dup 0)))] "TARGET_VX" { operands[3] = gen_reg_rtx (mode); @@ -1499,18 +1604,24 @@ (match_operand:VFT 2 "register_operand" "v"))) (set (match_dup 3) (gt: (match_dup 2) (match_dup 1))) (set (match_dup 0) (ior: (match_dup 0) (match_dup 3)))] - "TARGET_VX" + "TARGET_VXE" { operands[3] = gen_reg_rtx (mode); }) -; ORDERED (a, b): a >= b | b > a +; ORDERED (a, b): !(a u< b) | !(a u>= b) (define_expand "vec_cmpordered" - [(set (match_operand: 0 "register_operand" "=v") - (ge: (match_operand:VFT 1 "register_operand" "v") - (match_operand:VFT 2 "register_operand" "v"))) - (set (match_dup 3) (gt: (match_dup 2) (match_dup 1))) - (set (match_dup 0) (ior: (match_dup 0) (match_dup 3)))] + [(set (match_operand: 0 "register_operand" "=v") + (not: + (unlt: (match_operand:VFT 1 "register_operand" "v") + (match_operand:VFT 2 "register_operand" "v")))) + (set (match_dup 3) + (not: + (unge: (match_dup 1) + (match_dup 2)))) + (set (match_dup 0) + (ior: (match_dup 0) + (match_dup 3)))] "TARGET_VX" { operands[3] = gen_reg_rtx (mode); @@ -1530,7 +1641,7 @@ }) (define_code_iterator VEC_CMP_EXPAND - [uneq ltgt ordered unordered]) + [ungt unge uneq ltgt ordered unordered]) (define_expand "vec_cmp" [(match_operand 0 "register_operand" "") diff --git a/gcc/testsuite/gcc.target/s390/vector/vec-scalar-cmp-1.c b/gcc/testsuite/gcc.target/s390/vector/vec-scalar-cmp-1.c index ea51d0c86af..073d574aa5e 100644 --- a/gcc/testsuite/gcc.target/s390/vector/vec-scalar-cmp-1.c +++ b/gcc/testsuite/gcc.target/s390/vector/vec-scalar-cmp-1.c @@ -34,7 +34,7 @@ gt (double a, double b) return a > b; } -/* { dg-final { scan-assembler "gt:\n\[^:\]*\twfcdb\t%v\[0-9\]*,%v\[0-9\]*\n\t\[^:\]+\tlochinh\t%r2,0" } } */ +/* { dg-final { scan-assembler "gt:\n\[^:\]*\twfkdb\t%v\[0-9\]*,%v\[0-9\]*\n\t\[^:\]+\tlochinh\t%r2,0" } } */ int ge (double a, double b) @@ -45,7 +45,7 @@ ge (double a, double b) return a >= b; } -/* { dg-final { scan-assembler "ge:\n\[^:\]*\twfcdb\t%v\[0-9\]*,%v\[0-9\]*\n\t\[^:\]+\tlochinhe\t%r2,0" } } */ +/* { dg-final { scan-assembler "ge:\n\[^:\]*\twfkdb\t%v\[0-9\]*,%v\[0-9\]*\n\t\[^:\]+\tlochinhe\t%r2,0" } } */ int lt (double a, double b) @@ -56,7 +56,7 @@ lt (double a, double b) return a < b; } -/* { dg-final { scan-assembler "lt:\n\[^:\]*\twfcdb\t%v\[0-9\]*,%v\[0-9\]*\n\t\[^:\]+\tlochinl\t%r2,0" } } */ +/* { dg-final { scan-assembler "lt:\n\[^:\]*\twfkdb\t%v\[0-9\]*,%v\[0-9\]*\n\t\[^:\]+\tlochinl\t%r2,0" } } */ int le (double a, double b) @@ -67,4 +67,4 @@ le (double a, double b) return a <= b; } -/* { dg-final { scan-assembler "le:\n\[^:\]*\twfcdb\t%v\[0-9\]*,%v\[0-9\]*\n\t\[^:\]+\tlochinle\t%r2,0" } } */ +/* { dg-final { scan-assembler "le:\n\[^:\]*\twfkdb\t%v\[0-9\]*,%v\[0-9\]*\n\t\[^:\]+\tlochinle\t%r2,0" } } */ From patchwork Tue Oct 1 13:27:09 2019 Content-Type: text/plain; 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Tue, 1 Oct 2019 14:29:05 +0100 Received: from d06av21.portsmouth.uk.ibm.com (d06av21.portsmouth.uk.ibm.com [9.149.105.232]) by b06cxnps4075.portsmouth.uk.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x91DT32959703364 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Tue, 1 Oct 2019 13:29:03 GMT Received: from d06av21.portsmouth.uk.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 803955206D; Tue, 1 Oct 2019 13:29:03 +0000 (GMT) Received: from white.boeblingen.de.ibm.com (unknown [9.152.96.81]) by d06av21.portsmouth.uk.ibm.com (Postfix) with ESMTP id 28CE552065; Tue, 1 Oct 2019 13:29:03 +0000 (GMT) From: Ilya Leoshkevich To: gcc-patches@gcc.gnu.org Cc: richard.guenther@gmail.com, richard.sandiford@arm.com, segher@kernel.crashing.org, joseph@codesourcery.com, krebbel@linux.ibm.com, rdapp@linux.ibm.com, Ilya Leoshkevich Subject: [PATCH v4 7/7] S/390: Test signaling FP comparison instructions Date: Tue, 1 Oct 2019 15:27:09 +0200 In-Reply-To: <20191001132709.87257-1-iii@linux.ibm.com> References: <20191001132709.87257-1-iii@linux.ibm.com> MIME-Version: 1.0 x-cbid: 19100113-0008-0000-0000-0000031CC5AD X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19100113-0009-0000-0000-00004A3B7012 Message-Id: <20191001132709.87257-8-iii@linux.ibm.com> X-IsSubscribed: yes gcc/testsuite/ChangeLog: 2019-08-09 Ilya Leoshkevich PR target/77918 * gcc.target/s390/s390.exp: Enable Fortran tests. * gcc.target/s390/zvector/autovec-double-quiet-eq.c: New test. * gcc.target/s390/zvector/autovec-double-quiet-ge.c: New test. * gcc.target/s390/zvector/autovec-double-quiet-gt.c: New test. * gcc.target/s390/zvector/autovec-double-quiet-le.c: New test. * gcc.target/s390/zvector/autovec-double-quiet-lt.c: New test. * gcc.target/s390/zvector/autovec-double-quiet-ordered.c: New test. * gcc.target/s390/zvector/autovec-double-quiet-uneq.c: New test. * gcc.target/s390/zvector/autovec-double-quiet-unordered.c: New test. * gcc.target/s390/zvector/autovec-double-signaling-eq-z13-finite.c: New test. * gcc.target/s390/zvector/autovec-double-signaling-eq-z13.c: New test. * gcc.target/s390/zvector/autovec-double-signaling-eq.c: New test. * gcc.target/s390/zvector/autovec-double-signaling-ge-z13-finite.c: New test. * gcc.target/s390/zvector/autovec-double-signaling-ge-z13.c: New test. * gcc.target/s390/zvector/autovec-double-signaling-ge.c: New test. * gcc.target/s390/zvector/autovec-double-signaling-gt-z13-finite.c: New test. * gcc.target/s390/zvector/autovec-double-signaling-gt-z13.c: New test. * gcc.target/s390/zvector/autovec-double-signaling-gt.c: New test. * gcc.target/s390/zvector/autovec-double-signaling-le-z13-finite.c: New test. * gcc.target/s390/zvector/autovec-double-signaling-le-z13.c: New test. * gcc.target/s390/zvector/autovec-double-signaling-le.c: New test. * gcc.target/s390/zvector/autovec-double-signaling-lt-z13-finite.c: New test. * gcc.target/s390/zvector/autovec-double-signaling-lt-z13.c: New test. * gcc.target/s390/zvector/autovec-double-signaling-lt.c: New test. * gcc.target/s390/zvector/autovec-double-signaling-ltgt-z13-finite.c: New test. * gcc.target/s390/zvector/autovec-double-signaling-ltgt-z13.c: New test. * gcc.target/s390/zvector/autovec-double-signaling-ltgt.c: New test. * gcc.target/s390/zvector/autovec-double-smax-z13.F90: New test. * gcc.target/s390/zvector/autovec-double-smax.F90: New test. * gcc.target/s390/zvector/autovec-double-smin-z13.F90: New test. * gcc.target/s390/zvector/autovec-double-smin.F90: New test. * gcc.target/s390/zvector/autovec-float-quiet-eq.c: New test. * gcc.target/s390/zvector/autovec-float-quiet-ge.c: New test. * gcc.target/s390/zvector/autovec-float-quiet-gt.c: New test. * gcc.target/s390/zvector/autovec-float-quiet-le.c: New test. * gcc.target/s390/zvector/autovec-float-quiet-lt.c: New test. * gcc.target/s390/zvector/autovec-float-quiet-ordered.c: New test. * gcc.target/s390/zvector/autovec-float-quiet-uneq.c: New test. * gcc.target/s390/zvector/autovec-float-quiet-unordered.c: New test. * gcc.target/s390/zvector/autovec-float-signaling-eq.c: New test. * gcc.target/s390/zvector/autovec-float-signaling-ge.c: New test. * gcc.target/s390/zvector/autovec-float-signaling-gt.c: New test. * gcc.target/s390/zvector/autovec-float-signaling-le.c: New test. * gcc.target/s390/zvector/autovec-float-signaling-lt.c: New test. * gcc.target/s390/zvector/autovec-float-signaling-ltgt.c: New test. * gcc.target/s390/zvector/autovec-fortran.h: New test. * gcc.target/s390/zvector/autovec-long-double-signaling-ge.c: New test. * gcc.target/s390/zvector/autovec-long-double-signaling-gt.c: New test. * gcc.target/s390/zvector/autovec-long-double-signaling-le.c: New test. * gcc.target/s390/zvector/autovec-long-double-signaling-lt.c: New test. * gcc.target/s390/zvector/autovec.h: New test. --- gcc/testsuite/gcc.target/s390/s390.exp | 8 ++++ .../s390/zvector/autovec-double-quiet-eq.c | 8 ++++ .../s390/zvector/autovec-double-quiet-ge.c | 8 ++++ .../s390/zvector/autovec-double-quiet-gt.c | 8 ++++ .../s390/zvector/autovec-double-quiet-le.c | 8 ++++ .../s390/zvector/autovec-double-quiet-lt.c | 8 ++++ .../zvector/autovec-double-quiet-ordered.c | 10 +++++ .../s390/zvector/autovec-double-quiet-uneq.c | 10 +++++ .../zvector/autovec-double-quiet-unordered.c | 11 +++++ .../autovec-double-signaling-eq-z13-finite.c | 10 +++++ .../zvector/autovec-double-signaling-eq-z13.c | 9 ++++ .../zvector/autovec-double-signaling-eq.c | 11 +++++ .../autovec-double-signaling-ge-z13-finite.c | 10 +++++ .../zvector/autovec-double-signaling-ge-z13.c | 9 ++++ .../zvector/autovec-double-signaling-ge.c | 8 ++++ .../autovec-double-signaling-gt-z13-finite.c | 10 +++++ .../zvector/autovec-double-signaling-gt-z13.c | 9 ++++ .../zvector/autovec-double-signaling-gt.c | 8 ++++ .../autovec-double-signaling-le-z13-finite.c | 10 +++++ .../zvector/autovec-double-signaling-le-z13.c | 9 ++++ .../zvector/autovec-double-signaling-le.c | 8 ++++ .../autovec-double-signaling-lt-z13-finite.c | 10 +++++ .../zvector/autovec-double-signaling-lt-z13.c | 9 ++++ .../zvector/autovec-double-signaling-lt.c | 8 ++++ ...autovec-double-signaling-ltgt-z13-finite.c | 9 ++++ .../autovec-double-signaling-ltgt-z13.c | 9 ++++ .../zvector/autovec-double-signaling-ltgt.c | 9 ++++ .../s390/zvector/autovec-double-smax-z13.F90 | 11 +++++ .../s390/zvector/autovec-double-smax.F90 | 8 ++++ .../s390/zvector/autovec-double-smin-z13.F90 | 11 +++++ .../s390/zvector/autovec-double-smin.F90 | 8 ++++ .../s390/zvector/autovec-float-quiet-eq.c | 8 ++++ .../s390/zvector/autovec-float-quiet-ge.c | 8 ++++ .../s390/zvector/autovec-float-quiet-gt.c | 8 ++++ .../s390/zvector/autovec-float-quiet-le.c | 8 ++++ .../s390/zvector/autovec-float-quiet-lt.c | 8 ++++ .../zvector/autovec-float-quiet-ordered.c | 10 +++++ .../s390/zvector/autovec-float-quiet-uneq.c | 10 +++++ .../zvector/autovec-float-quiet-unordered.c | 11 +++++ .../s390/zvector/autovec-float-signaling-eq.c | 11 +++++ .../s390/zvector/autovec-float-signaling-ge.c | 8 ++++ .../s390/zvector/autovec-float-signaling-gt.c | 8 ++++ .../s390/zvector/autovec-float-signaling-le.c | 8 ++++ .../s390/zvector/autovec-float-signaling-lt.c | 8 ++++ .../zvector/autovec-float-signaling-ltgt.c | 9 ++++ .../gcc.target/s390/zvector/autovec-fortran.h | 7 ++++ .../autovec-long-double-signaling-ge.c | 8 ++++ .../autovec-long-double-signaling-gt.c | 8 ++++ .../autovec-long-double-signaling-le.c | 8 ++++ .../autovec-long-double-signaling-lt.c | 8 ++++ .../gcc.target/s390/zvector/autovec.h | 41 +++++++++++++++++++ 51 files changed, 485 insertions(+) create mode 100644 gcc/testsuite/gcc.target/s390/zvector/autovec-double-quiet-eq.c create mode 100644 gcc/testsuite/gcc.target/s390/zvector/autovec-double-quiet-ge.c create mode 100644 gcc/testsuite/gcc.target/s390/zvector/autovec-double-quiet-gt.c create mode 100644 gcc/testsuite/gcc.target/s390/zvector/autovec-double-quiet-le.c create mode 100644 gcc/testsuite/gcc.target/s390/zvector/autovec-double-quiet-lt.c create mode 100644 gcc/testsuite/gcc.target/s390/zvector/autovec-double-quiet-ordered.c create mode 100644 gcc/testsuite/gcc.target/s390/zvector/autovec-double-quiet-uneq.c create mode 100644 gcc/testsuite/gcc.target/s390/zvector/autovec-double-quiet-unordered.c create mode 100644 gcc/testsuite/gcc.target/s390/zvector/autovec-double-signaling-eq-z13-finite.c create mode 100644 gcc/testsuite/gcc.target/s390/zvector/autovec-double-signaling-eq-z13.c create mode 100644 gcc/testsuite/gcc.target/s390/zvector/autovec-double-signaling-eq.c create mode 100644 gcc/testsuite/gcc.target/s390/zvector/autovec-double-signaling-ge-z13-finite.c create mode 100644 gcc/testsuite/gcc.target/s390/zvector/autovec-double-signaling-ge-z13.c create mode 100644 gcc/testsuite/gcc.target/s390/zvector/autovec-double-signaling-ge.c create mode 100644 gcc/testsuite/gcc.target/s390/zvector/autovec-double-signaling-gt-z13-finite.c create mode 100644 gcc/testsuite/gcc.target/s390/zvector/autovec-double-signaling-gt-z13.c create mode 100644 gcc/testsuite/gcc.target/s390/zvector/autovec-double-signaling-gt.c create mode 100644 gcc/testsuite/gcc.target/s390/zvector/autovec-double-signaling-le-z13-finite.c create mode 100644 gcc/testsuite/gcc.target/s390/zvector/autovec-double-signaling-le-z13.c create mode 100644 gcc/testsuite/gcc.target/s390/zvector/autovec-double-signaling-le.c create mode 100644 gcc/testsuite/gcc.target/s390/zvector/autovec-double-signaling-lt-z13-finite.c create mode 100644 gcc/testsuite/gcc.target/s390/zvector/autovec-double-signaling-lt-z13.c create mode 100644 gcc/testsuite/gcc.target/s390/zvector/autovec-double-signaling-lt.c create mode 100644 gcc/testsuite/gcc.target/s390/zvector/autovec-double-signaling-ltgt-z13-finite.c create mode 100644 gcc/testsuite/gcc.target/s390/zvector/autovec-double-signaling-ltgt-z13.c create mode 100644 gcc/testsuite/gcc.target/s390/zvector/autovec-double-signaling-ltgt.c create mode 100644 gcc/testsuite/gcc.target/s390/zvector/autovec-double-smax-z13.F90 create mode 100644 gcc/testsuite/gcc.target/s390/zvector/autovec-double-smax.F90 create mode 100644 gcc/testsuite/gcc.target/s390/zvector/autovec-double-smin-z13.F90 create mode 100644 gcc/testsuite/gcc.target/s390/zvector/autovec-double-smin.F90 create mode 100644 gcc/testsuite/gcc.target/s390/zvector/autovec-float-quiet-eq.c create mode 100644 gcc/testsuite/gcc.target/s390/zvector/autovec-float-quiet-ge.c create mode 100644 gcc/testsuite/gcc.target/s390/zvector/autovec-float-quiet-gt.c create mode 100644 gcc/testsuite/gcc.target/s390/zvector/autovec-float-quiet-le.c create mode 100644 gcc/testsuite/gcc.target/s390/zvector/autovec-float-quiet-lt.c create mode 100644 gcc/testsuite/gcc.target/s390/zvector/autovec-float-quiet-ordered.c create mode 100644 gcc/testsuite/gcc.target/s390/zvector/autovec-float-quiet-uneq.c create mode 100644 gcc/testsuite/gcc.target/s390/zvector/autovec-float-quiet-unordered.c create mode 100644 gcc/testsuite/gcc.target/s390/zvector/autovec-float-signaling-eq.c create mode 100644 gcc/testsuite/gcc.target/s390/zvector/autovec-float-signaling-ge.c create mode 100644 gcc/testsuite/gcc.target/s390/zvector/autovec-float-signaling-gt.c create mode 100644 gcc/testsuite/gcc.target/s390/zvector/autovec-float-signaling-le.c create mode 100644 gcc/testsuite/gcc.target/s390/zvector/autovec-float-signaling-lt.c create mode 100644 gcc/testsuite/gcc.target/s390/zvector/autovec-float-signaling-ltgt.c create mode 100644 gcc/testsuite/gcc.target/s390/zvector/autovec-fortran.h create mode 100644 gcc/testsuite/gcc.target/s390/zvector/autovec-long-double-signaling-ge.c create mode 100644 gcc/testsuite/gcc.target/s390/zvector/autovec-long-double-signaling-gt.c create mode 100644 gcc/testsuite/gcc.target/s390/zvector/autovec-long-double-signaling-le.c create mode 100644 gcc/testsuite/gcc.target/s390/zvector/autovec-long-double-signaling-lt.c create mode 100644 gcc/testsuite/gcc.target/s390/zvector/autovec.h diff --git a/gcc/testsuite/gcc.target/s390/s390.exp b/gcc/testsuite/gcc.target/s390/s390.exp index 86f7e4398eb..925eb568832 100644 --- a/gcc/testsuite/gcc.target/s390/s390.exp +++ b/gcc/testsuite/gcc.target/s390/s390.exp @@ -27,6 +27,7 @@ if ![istarget s390*-*-*] then { # Load support procs. load_lib gcc-dg.exp load_lib target-supports.exp +load_lib gfortran-dg.exp # Return 1 if the the assembler understands .machine and .machinemode. The # target attribute needs that feature to work. @@ -193,6 +194,10 @@ global DEFAULT_CFLAGS if ![info exists DEFAULT_CFLAGS] then { set DEFAULT_CFLAGS " -ansi -pedantic-errors" } +global DEFAULT_FFLAGS +if ![info exists DEFAULT_FFLAGS] then { + set DEFAULT_FFLAGS " -pedantic-errors" +} # Initialize `dg'. dg-init @@ -209,6 +214,9 @@ dg-runtest [lsort [prune [glob -nocomplain $srcdir/$subdir/*.{c,S}] \ dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*vector*/*.{c,S}]] \ "" $DEFAULT_CFLAGS +gfortran-dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/*vector*/*.F90]] \ + "" $DEFAULT_FFLAGS + dg-runtest [lsort [glob -nocomplain $srcdir/$subdir/target-attribute/*.{c,S}]] \ "" $DEFAULT_CFLAGS diff --git a/gcc/testsuite/gcc.target/s390/zvector/autovec-double-quiet-eq.c b/gcc/testsuite/gcc.target/s390/zvector/autovec-double-quiet-eq.c new file mode 100644 index 00000000000..dad138770c8 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/zvector/autovec-double-quiet-eq.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=z13 -mzvector" } */ + +#include "autovec.h" + +AUTOVEC_DOUBLE (QUIET_EQ); + +/* { dg-final { scan-assembler {\n\tvfcedb\t} } } */ diff --git a/gcc/testsuite/gcc.target/s390/zvector/autovec-double-quiet-ge.c b/gcc/testsuite/gcc.target/s390/zvector/autovec-double-quiet-ge.c new file mode 100644 index 00000000000..9fddb62573f --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/zvector/autovec-double-quiet-ge.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=z13 -mzvector" } */ + +#include "autovec.h" + +AUTOVEC_DOUBLE (QUIET_GE); + +/* { dg-final { scan-assembler {\n\tvfchedb\t} } } */ diff --git a/gcc/testsuite/gcc.target/s390/zvector/autovec-double-quiet-gt.c b/gcc/testsuite/gcc.target/s390/zvector/autovec-double-quiet-gt.c new file mode 100644 index 00000000000..eb512f84c47 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/zvector/autovec-double-quiet-gt.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=z13 -mzvector" } */ + +#include "autovec.h" + +AUTOVEC_DOUBLE (QUIET_GT); + +/* { dg-final { scan-assembler {\n\tvfchdb\t} } } */ diff --git a/gcc/testsuite/gcc.target/s390/zvector/autovec-double-quiet-le.c b/gcc/testsuite/gcc.target/s390/zvector/autovec-double-quiet-le.c new file mode 100644 index 00000000000..c049f8b7dee --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/zvector/autovec-double-quiet-le.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=z13 -mzvector" } */ + +#include "autovec.h" + +AUTOVEC_DOUBLE (QUIET_LE); + +/* { dg-final { scan-assembler {\n\tvfchedb\t} } } */ diff --git a/gcc/testsuite/gcc.target/s390/zvector/autovec-double-quiet-lt.c b/gcc/testsuite/gcc.target/s390/zvector/autovec-double-quiet-lt.c new file mode 100644 index 00000000000..b6f7702ecd0 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/zvector/autovec-double-quiet-lt.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=z13 -mzvector" } */ + +#include "autovec.h" + +AUTOVEC_DOUBLE (QUIET_LT); + +/* { dg-final { scan-assembler {\n\tvfchdb\t} } } */ diff --git a/gcc/testsuite/gcc.target/s390/zvector/autovec-double-quiet-ordered.c b/gcc/testsuite/gcc.target/s390/zvector/autovec-double-quiet-ordered.c new file mode 100644 index 00000000000..bf8ebd4ab6a --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/zvector/autovec-double-quiet-ordered.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=z13 -mzvector" } */ + +#include "autovec.h" + +AUTOVEC_DOUBLE (QUIET_ORDERED); + +/* { dg-final { scan-assembler {\n\tvfchedb\t} } } */ +/* { dg-final { scan-assembler {\n\tvfchdb\t} } } */ +/* { dg-final { scan-assembler {\n\tvo\t} } } */ diff --git a/gcc/testsuite/gcc.target/s390/zvector/autovec-double-quiet-uneq.c b/gcc/testsuite/gcc.target/s390/zvector/autovec-double-quiet-uneq.c new file mode 100644 index 00000000000..421fb5e7ba5 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/zvector/autovec-double-quiet-uneq.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=z13 -mzvector" } */ + +#include "autovec.h" + +AUTOVEC_DOUBLE (QUIET_UNEQ); + +/* { dg-final { scan-assembler-times {\n\tvfchdb\t} 2 } } */ +/* { dg-final { scan-assembler {\n\tvo\t} } } */ +/* { dg-final { scan-assembler {\n\tvx\t} } } */ diff --git a/gcc/testsuite/gcc.target/s390/zvector/autovec-double-quiet-unordered.c b/gcc/testsuite/gcc.target/s390/zvector/autovec-double-quiet-unordered.c new file mode 100644 index 00000000000..c42f7930ad8 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/zvector/autovec-double-quiet-unordered.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=z13 -mzvector" } */ + +#include "autovec.h" + +AUTOVEC_DOUBLE (QUIET_UNORDERED); + +/* { dg-final { scan-assembler {\n\tvfchedb\t} } } */ +/* { dg-final { scan-assembler {\n\tvfchdb\t} } } */ +/* combine prefers to reorder vsel args instead of using vno. */ +/* { dg-final { scan-assembler {\n\tvo\t} } } */ diff --git a/gcc/testsuite/gcc.target/s390/zvector/autovec-double-signaling-eq-z13-finite.c b/gcc/testsuite/gcc.target/s390/zvector/autovec-double-signaling-eq-z13-finite.c new file mode 100644 index 00000000000..e3d42eaf3ad --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/zvector/autovec-double-signaling-eq-z13-finite.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=z13 -mzvector -ffinite-math-only" } */ + +#include "autovec.h" + +AUTOVEC_DOUBLE (SIGNALING_EQ); + +/* We can use non-signaling vector comparison instructions with + -ffinite-math-only. */ +/* { dg-final { scan-assembler {\n\tvfcedb\t} } } */ diff --git a/gcc/testsuite/gcc.target/s390/zvector/autovec-double-signaling-eq-z13.c b/gcc/testsuite/gcc.target/s390/zvector/autovec-double-signaling-eq-z13.c new file mode 100644 index 00000000000..f6110328891 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/zvector/autovec-double-signaling-eq-z13.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=z13 -mzvector" } */ + +#include "autovec.h" + +AUTOVEC_DOUBLE (SIGNALING_EQ); + +/* z13 does not have signaling vector comparison instructions. */ +/* { dg-final { scan-assembler {\n\tkdbr\t} } } */ diff --git a/gcc/testsuite/gcc.target/s390/zvector/autovec-double-signaling-eq.c b/gcc/testsuite/gcc.target/s390/zvector/autovec-double-signaling-eq.c new file mode 100644 index 00000000000..32088cb55b4 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/zvector/autovec-double-signaling-eq.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=z14 -mzvector" } */ + +#include "autovec.h" + +AUTOVEC_DOUBLE (SIGNALING_EQ); + +/* The vectorizer produces <= and ==, which rtl passes cannot turn into vfkedb + yet. */ +/* { dg-final { scan-assembler {\n\tvfcedb\t} } } */ +/* { dg-final { scan-assembler {\n\tvfkhedb\t} } } */ diff --git a/gcc/testsuite/gcc.target/s390/zvector/autovec-double-signaling-ge-z13-finite.c b/gcc/testsuite/gcc.target/s390/zvector/autovec-double-signaling-ge-z13-finite.c new file mode 100644 index 00000000000..b301d1b739b --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/zvector/autovec-double-signaling-ge-z13-finite.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=z13 -mzvector -ffinite-math-only" } */ + +#include "autovec.h" + +AUTOVEC_DOUBLE (SIGNALING_GE); + +/* We can use non-signaling vector comparison instructions with + -ffinite-math-only. */ +/* { dg-final { scan-assembler {\n\tvfchedb\t} } } */ diff --git a/gcc/testsuite/gcc.target/s390/zvector/autovec-double-signaling-ge-z13.c b/gcc/testsuite/gcc.target/s390/zvector/autovec-double-signaling-ge-z13.c new file mode 100644 index 00000000000..ee83f3405c8 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/zvector/autovec-double-signaling-ge-z13.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=z13 -mzvector" } */ + +#include "autovec.h" + +AUTOVEC_DOUBLE (SIGNALING_GE); + +/* z13 does not have signaling vector comparison instructions. */ +/* { dg-final { scan-assembler {\n\tkdb\t} } } */ diff --git a/gcc/testsuite/gcc.target/s390/zvector/autovec-double-signaling-ge.c b/gcc/testsuite/gcc.target/s390/zvector/autovec-double-signaling-ge.c new file mode 100644 index 00000000000..bcb4c868a15 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/zvector/autovec-double-signaling-ge.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=z14 -mzvector" } */ + +#include "autovec.h" + +AUTOVEC_DOUBLE (SIGNALING_GE); + +/* { dg-final { scan-assembler {\n\tvfkhedb\t} } } */ diff --git a/gcc/testsuite/gcc.target/s390/zvector/autovec-double-signaling-gt-z13-finite.c b/gcc/testsuite/gcc.target/s390/zvector/autovec-double-signaling-gt-z13-finite.c new file mode 100644 index 00000000000..c49764447f3 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/zvector/autovec-double-signaling-gt-z13-finite.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=z13 -mzvector -ffinite-math-only" } */ + +#include "autovec.h" + +AUTOVEC_DOUBLE (SIGNALING_GT); + +/* We can use non-signaling vector comparison instructions with + -ffinite-math-only. */ +/* { dg-final { scan-assembler {\n\tvfchdb\t} } } */ diff --git a/gcc/testsuite/gcc.target/s390/zvector/autovec-double-signaling-gt-z13.c b/gcc/testsuite/gcc.target/s390/zvector/autovec-double-signaling-gt-z13.c new file mode 100644 index 00000000000..6b9c11997a6 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/zvector/autovec-double-signaling-gt-z13.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=z13 -mzvector" } */ + +#include "autovec.h" + +AUTOVEC_DOUBLE (SIGNALING_GT); + +/* z13 does not have signaling vector comparison instructions. */ +/* { dg-final { scan-assembler {\n\tkdb\t} } } */ diff --git a/gcc/testsuite/gcc.target/s390/zvector/autovec-double-signaling-gt.c b/gcc/testsuite/gcc.target/s390/zvector/autovec-double-signaling-gt.c new file mode 100644 index 00000000000..e423ed0f78c --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/zvector/autovec-double-signaling-gt.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=z14 -mzvector" } */ + +#include "autovec.h" + +AUTOVEC_DOUBLE (SIGNALING_GT); + +/* { dg-final { scan-assembler {\n\tvfkhdb\t} } } */ diff --git a/gcc/testsuite/gcc.target/s390/zvector/autovec-double-signaling-le-z13-finite.c b/gcc/testsuite/gcc.target/s390/zvector/autovec-double-signaling-le-z13-finite.c new file mode 100644 index 00000000000..7fa559b5701 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/zvector/autovec-double-signaling-le-z13-finite.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=z13 -mzvector -ffinite-math-only" } */ + +#include "autovec.h" + +AUTOVEC_DOUBLE (SIGNALING_LE); + +/* We can use non-signaling vector comparison instructions with + -ffinite-math-only. */ +/* { dg-final { scan-assembler {\n\tvfchedb\t} } } */ diff --git a/gcc/testsuite/gcc.target/s390/zvector/autovec-double-signaling-le-z13.c b/gcc/testsuite/gcc.target/s390/zvector/autovec-double-signaling-le-z13.c new file mode 100644 index 00000000000..a80ac20b905 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/zvector/autovec-double-signaling-le-z13.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=z13 -mzvector" } */ + +#include "autovec.h" + +AUTOVEC_DOUBLE (SIGNALING_LE); + +/* z13 does not have signaling vector comparison instructions. */ +/* { dg-final { scan-assembler {\n\tkdb\t} } } */ diff --git a/gcc/testsuite/gcc.target/s390/zvector/autovec-double-signaling-le.c b/gcc/testsuite/gcc.target/s390/zvector/autovec-double-signaling-le.c new file mode 100644 index 00000000000..b97bebaaf8f --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/zvector/autovec-double-signaling-le.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=z14 -mzvector" } */ + +#include "autovec.h" + +AUTOVEC_DOUBLE (SIGNALING_LE); + +/* { dg-final { scan-assembler {\n\tvfkhedb\t} } } */ diff --git a/gcc/testsuite/gcc.target/s390/zvector/autovec-double-signaling-lt-z13-finite.c b/gcc/testsuite/gcc.target/s390/zvector/autovec-double-signaling-lt-z13-finite.c new file mode 100644 index 00000000000..3305a98379c --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/zvector/autovec-double-signaling-lt-z13-finite.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=z13 -mzvector -ffinite-math-only" } */ + +#include "autovec.h" + +AUTOVEC_DOUBLE (SIGNALING_LT); + +/* We can use non-signaling vector comparison instructions with + -ffinite-math-only. */ +/* { dg-final { scan-assembler {\n\tvfchdb\t} } } */ diff --git a/gcc/testsuite/gcc.target/s390/zvector/autovec-double-signaling-lt-z13.c b/gcc/testsuite/gcc.target/s390/zvector/autovec-double-signaling-lt-z13.c new file mode 100644 index 00000000000..8b398a28c37 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/zvector/autovec-double-signaling-lt-z13.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=z13 -mzvector" } */ + +#include "autovec.h" + +AUTOVEC_DOUBLE (SIGNALING_LT); + +/* z13 does not have signaling vector comparison instructions. */ +/* { dg-final { scan-assembler {\n\tkdb\t} } } */ diff --git a/gcc/testsuite/gcc.target/s390/zvector/autovec-double-signaling-lt.c b/gcc/testsuite/gcc.target/s390/zvector/autovec-double-signaling-lt.c new file mode 100644 index 00000000000..b01272d00a5 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/zvector/autovec-double-signaling-lt.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=z14 -mzvector" } */ + +#include "autovec.h" + +AUTOVEC_DOUBLE (SIGNALING_LT); + +/* { dg-final { scan-assembler {\n\tvfkhdb\t} } } */ diff --git a/gcc/testsuite/gcc.target/s390/zvector/autovec-double-signaling-ltgt-z13-finite.c b/gcc/testsuite/gcc.target/s390/zvector/autovec-double-signaling-ltgt-z13-finite.c new file mode 100644 index 00000000000..76730d70968 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/zvector/autovec-double-signaling-ltgt-z13-finite.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=z13 -mzvector -ffinite-math-only" } */ + +#include "autovec.h" + +AUTOVEC_DOUBLE (SIGNALING_LTGT); + +/* ltgt is the same as eq with -ffinite-math-only. */ +/* { dg-final { scan-assembler {\n\tvfcedb\t} } } */ diff --git a/gcc/testsuite/gcc.target/s390/zvector/autovec-double-signaling-ltgt-z13.c b/gcc/testsuite/gcc.target/s390/zvector/autovec-double-signaling-ltgt-z13.c new file mode 100644 index 00000000000..d466697499a --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/zvector/autovec-double-signaling-ltgt-z13.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=z13 -mzvector" } */ + +#include "autovec.h" + +AUTOVEC_DOUBLE (SIGNALING_LTGT); + +/* z13 does not have signaling vector comparison instructions. */ +/* { dg-final { scan-assembler {\n\tkdb\t} } } */ diff --git a/gcc/testsuite/gcc.target/s390/zvector/autovec-double-signaling-ltgt.c b/gcc/testsuite/gcc.target/s390/zvector/autovec-double-signaling-ltgt.c new file mode 100644 index 00000000000..645f299a9fc --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/zvector/autovec-double-signaling-ltgt.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=z14 -mzvector" } */ + +#include "autovec.h" + +AUTOVEC_DOUBLE (SIGNALING_LTGT); + +/* { dg-final { scan-assembler-times {\n\tvfkhdb\t} 2 } } */ +/* { dg-final { scan-assembler {\n\tvo\t} } } */ diff --git a/gcc/testsuite/gcc.target/s390/zvector/autovec-double-smax-z13.F90 b/gcc/testsuite/gcc.target/s390/zvector/autovec-double-smax-z13.F90 new file mode 100644 index 00000000000..b114082df59 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/zvector/autovec-double-smax-z13.F90 @@ -0,0 +1,11 @@ +! { dg-do compile } +! { dg-options "-ffree-line-length-256 -O3 -march=z13 -mzvector" } + +#include "autovec-fortran.h" + +AUTOVEC_FORTRAN (max) + +! Fortran's max does not specify whether or not an exception should be raised in +! face of qNaNs, and neither does gcc's smax. Vectorize max using quiet +! comparison, because that's the only one we have on z13. +! { dg-final { scan-assembler {\n\tvfchdb\t} } } diff --git a/gcc/testsuite/gcc.target/s390/zvector/autovec-double-smax.F90 b/gcc/testsuite/gcc.target/s390/zvector/autovec-double-smax.F90 new file mode 100644 index 00000000000..1698ec4f4db --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/zvector/autovec-double-smax.F90 @@ -0,0 +1,8 @@ +! { dg-do compile } +! { dg-options "-ffree-line-length-256 -O3 -march=z14 -mzvector" } + +#include "autovec-fortran.h" + +AUTOVEC_FORTRAN (max) + +! { dg-final { scan-assembler {\n\tvfmaxdb\t} } } diff --git a/gcc/testsuite/gcc.target/s390/zvector/autovec-double-smin-z13.F90 b/gcc/testsuite/gcc.target/s390/zvector/autovec-double-smin-z13.F90 new file mode 100644 index 00000000000..fc56e9d6879 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/zvector/autovec-double-smin-z13.F90 @@ -0,0 +1,11 @@ +! { dg-do compile } +! { dg-options "-ffree-line-length-256 -O3 -march=z13 -mzvector" } + +#include "autovec-fortran.h" + +AUTOVEC_FORTRAN (min) + +! Fortran's min does not specify whether or not an exception should be raised in +! face of qNaNs, and neither does gcc's smin. Vectorize min using quiet +! comparison, because that's the only one we have on z13. +! { dg-final { scan-assembler {\n\tvfchdb\t} } } diff --git a/gcc/testsuite/gcc.target/s390/zvector/autovec-double-smin.F90 b/gcc/testsuite/gcc.target/s390/zvector/autovec-double-smin.F90 new file mode 100644 index 00000000000..0dd1a33bb84 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/zvector/autovec-double-smin.F90 @@ -0,0 +1,8 @@ +! { dg-do compile } +! { dg-options "-ffree-line-length-256 -O3 -march=z14 -mzvector" } + +#include "autovec-fortran.h" + +AUTOVEC_FORTRAN (min) + +! { dg-final { scan-assembler {\n\tvfmindb\t} } } diff --git a/gcc/testsuite/gcc.target/s390/zvector/autovec-float-quiet-eq.c b/gcc/testsuite/gcc.target/s390/zvector/autovec-float-quiet-eq.c new file mode 100644 index 00000000000..c74927dd028 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/zvector/autovec-float-quiet-eq.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=z14 -mzvector" } */ + +#include "autovec.h" + +AUTOVEC_FLOAT (QUIET_EQ); + +/* { dg-final { scan-assembler {\n\tvfcesb\t} } } */ diff --git a/gcc/testsuite/gcc.target/s390/zvector/autovec-float-quiet-ge.c b/gcc/testsuite/gcc.target/s390/zvector/autovec-float-quiet-ge.c new file mode 100644 index 00000000000..4c7cb09eed5 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/zvector/autovec-float-quiet-ge.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=z14 -mzvector" } */ + +#include "autovec.h" + +AUTOVEC_FLOAT (QUIET_GE); + +/* { dg-final { scan-assembler {\n\tvfchesb\t} } } */ diff --git a/gcc/testsuite/gcc.target/s390/zvector/autovec-float-quiet-gt.c b/gcc/testsuite/gcc.target/s390/zvector/autovec-float-quiet-gt.c new file mode 100644 index 00000000000..dd787929b9f --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/zvector/autovec-float-quiet-gt.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=z14 -mzvector" } */ + +#include "autovec.h" + +AUTOVEC_FLOAT (QUIET_GT); + +/* { dg-final { scan-assembler {\n\tvfchsb\t} } } */ diff --git a/gcc/testsuite/gcc.target/s390/zvector/autovec-float-quiet-le.c b/gcc/testsuite/gcc.target/s390/zvector/autovec-float-quiet-le.c new file mode 100644 index 00000000000..5bd1e3e98e7 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/zvector/autovec-float-quiet-le.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=z14 -mzvector" } */ + +#include "autovec.h" + +AUTOVEC_FLOAT (QUIET_LE); + +/* { dg-final { scan-assembler {\n\tvfchesb\t} } } */ diff --git a/gcc/testsuite/gcc.target/s390/zvector/autovec-float-quiet-lt.c b/gcc/testsuite/gcc.target/s390/zvector/autovec-float-quiet-lt.c new file mode 100644 index 00000000000..4938dcfb430 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/zvector/autovec-float-quiet-lt.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=z14 -mzvector" } */ + +#include "autovec.h" + +AUTOVEC_FLOAT (QUIET_LT); + +/* { dg-final { scan-assembler {\n\tvfchsb\t} } } */ diff --git a/gcc/testsuite/gcc.target/s390/zvector/autovec-float-quiet-ordered.c b/gcc/testsuite/gcc.target/s390/zvector/autovec-float-quiet-ordered.c new file mode 100644 index 00000000000..222e9efb5f5 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/zvector/autovec-float-quiet-ordered.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=z14 -mzvector" } */ + +#include "autovec.h" + +AUTOVEC_FLOAT (QUIET_UNORDERED); + +/* { dg-final { scan-assembler {\n\tvfchesb\t} } } */ +/* { dg-final { scan-assembler {\n\tvfchsb\t} } } */ +/* { dg-final { scan-assembler {\n\tvo\t} } } */ diff --git a/gcc/testsuite/gcc.target/s390/zvector/autovec-float-quiet-uneq.c b/gcc/testsuite/gcc.target/s390/zvector/autovec-float-quiet-uneq.c new file mode 100644 index 00000000000..ab5dcac9c34 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/zvector/autovec-float-quiet-uneq.c @@ -0,0 +1,10 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=z14 -mzvector" } */ + +#include "autovec.h" + +AUTOVEC_FLOAT (QUIET_UNEQ); + +/* { dg-final { scan-assembler-times {\n\tvfchsb\t} 2 } } */ +/* { dg-final { scan-assembler {\n\tvo\t} } } */ +/* { dg-final { scan-assembler {\n\tvx\t} } } */ diff --git a/gcc/testsuite/gcc.target/s390/zvector/autovec-float-quiet-unordered.c b/gcc/testsuite/gcc.target/s390/zvector/autovec-float-quiet-unordered.c new file mode 100644 index 00000000000..c800dce2d7b --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/zvector/autovec-float-quiet-unordered.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=z14 -mzvector" } */ + +#include "autovec.h" + +AUTOVEC_FLOAT (QUIET_UNORDERED); + +/* { dg-final { scan-assembler {\n\tvfchesb\t} } } */ +/* { dg-final { scan-assembler {\n\tvfchsb\t} } } */ +/* combine prefers to reorder vsel args instead of using vno. */ +/* { dg-final { scan-assembler {\n\tvo\t} } } */ diff --git a/gcc/testsuite/gcc.target/s390/zvector/autovec-float-signaling-eq.c b/gcc/testsuite/gcc.target/s390/zvector/autovec-float-signaling-eq.c new file mode 100644 index 00000000000..ce3271c918c --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/zvector/autovec-float-signaling-eq.c @@ -0,0 +1,11 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=z14 -mzvector" } */ + +#include "autovec.h" + +AUTOVEC_FLOAT (SIGNALING_EQ); + +/* The vectorizer produces <= and ==, which rtl passes cannot turn into vfkesb + yet. */ +/* { dg-final { scan-assembler {\n\tvfcesb\t} } } */ +/* { dg-final { scan-assembler {\n\tvfkhesb\t} } } */ diff --git a/gcc/testsuite/gcc.target/s390/zvector/autovec-float-signaling-ge.c b/gcc/testsuite/gcc.target/s390/zvector/autovec-float-signaling-ge.c new file mode 100644 index 00000000000..0f98c5467e8 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/zvector/autovec-float-signaling-ge.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=z14 -mzvector" } */ + +#include "autovec.h" + +AUTOVEC_FLOAT (SIGNALING_GE); + +/* { dg-final { scan-assembler {\n\tvfkhesb\t} } } */ diff --git a/gcc/testsuite/gcc.target/s390/zvector/autovec-float-signaling-gt.c b/gcc/testsuite/gcc.target/s390/zvector/autovec-float-signaling-gt.c new file mode 100644 index 00000000000..762c4c2030c --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/zvector/autovec-float-signaling-gt.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=z14 -mzvector" } */ + +#include "autovec.h" + +AUTOVEC_FLOAT (SIGNALING_GT); + +/* { dg-final { scan-assembler {\n\tvfkhsb\t} } } */ diff --git a/gcc/testsuite/gcc.target/s390/zvector/autovec-float-signaling-le.c b/gcc/testsuite/gcc.target/s390/zvector/autovec-float-signaling-le.c new file mode 100644 index 00000000000..ccf0c5c24d1 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/zvector/autovec-float-signaling-le.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=z14 -mzvector" } */ + +#include "autovec.h" + +AUTOVEC_FLOAT (SIGNALING_LE); + +/* { dg-final { scan-assembler {\n\tvfkhesb\t} } } */ diff --git a/gcc/testsuite/gcc.target/s390/zvector/autovec-float-signaling-lt.c b/gcc/testsuite/gcc.target/s390/zvector/autovec-float-signaling-lt.c new file mode 100644 index 00000000000..b428e5fc52e --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/zvector/autovec-float-signaling-lt.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=z14 -mzvector" } */ + +#include "autovec.h" + +AUTOVEC_FLOAT (SIGNALING_LT); + +/* { dg-final { scan-assembler {\n\tvfkhsb\t} } } */ diff --git a/gcc/testsuite/gcc.target/s390/zvector/autovec-float-signaling-ltgt.c b/gcc/testsuite/gcc.target/s390/zvector/autovec-float-signaling-ltgt.c new file mode 100644 index 00000000000..bf15242a4d7 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/zvector/autovec-float-signaling-ltgt.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=z14 -mzvector" } */ + +#include "autovec.h" + +AUTOVEC_FLOAT (SIGNALING_LTGT); + +/* { dg-final { scan-assembler-times {\n\tvfkhsb\t} 2 } } */ +/* { dg-final { scan-assembler {\n\tvo\t} } } */ diff --git a/gcc/testsuite/gcc.target/s390/zvector/autovec-fortran.h b/gcc/testsuite/gcc.target/s390/zvector/autovec-fortran.h new file mode 100644 index 00000000000..8e44cb2dd31 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/zvector/autovec-fortran.h @@ -0,0 +1,7 @@ +#define AUTOVEC_FORTRAN(OP) subroutine f (r, x, y); \ + real(kind=kind (1.0d0)) :: r(1000000), x(1000000), y(1000000); \ + integer :: i; \ + do i = 1, 1000000; \ + r(i) = OP (x(i), y(i)); \ + end do; \ +end diff --git a/gcc/testsuite/gcc.target/s390/zvector/autovec-long-double-signaling-ge.c b/gcc/testsuite/gcc.target/s390/zvector/autovec-long-double-signaling-ge.c new file mode 100644 index 00000000000..684a6a9b2e2 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/zvector/autovec-long-double-signaling-ge.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=z14 -mzvector" } */ + +#include "autovec.h" + +AUTOVEC_LONG_DOUBLE (SIGNALING_GE); + +/* { dg-final { scan-assembler {\n\twfkhexb\t} } } */ diff --git a/gcc/testsuite/gcc.target/s390/zvector/autovec-long-double-signaling-gt.c b/gcc/testsuite/gcc.target/s390/zvector/autovec-long-double-signaling-gt.c new file mode 100644 index 00000000000..76ade12c7f8 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/zvector/autovec-long-double-signaling-gt.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=z14 -mzvector" } */ + +#include "autovec.h" + +AUTOVEC_LONG_DOUBLE (SIGNALING_GT); + +/* { dg-final { scan-assembler {\n\twfkhxb\t} } } */ diff --git a/gcc/testsuite/gcc.target/s390/zvector/autovec-long-double-signaling-le.c b/gcc/testsuite/gcc.target/s390/zvector/autovec-long-double-signaling-le.c new file mode 100644 index 00000000000..a15960ec86a --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/zvector/autovec-long-double-signaling-le.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=z14 -mzvector" } */ + +#include "autovec.h" + +AUTOVEC_LONG_DOUBLE (SIGNALING_LE); + +/* { dg-final { scan-assembler {\n\twfkhexb\t} } } */ diff --git a/gcc/testsuite/gcc.target/s390/zvector/autovec-long-double-signaling-lt.c b/gcc/testsuite/gcc.target/s390/zvector/autovec-long-double-signaling-lt.c new file mode 100644 index 00000000000..046d5487af8 --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/zvector/autovec-long-double-signaling-lt.c @@ -0,0 +1,8 @@ +/* { dg-do compile } */ +/* { dg-options "-O3 -march=z14 -mzvector" } */ + +#include "autovec.h" + +AUTOVEC_LONG_DOUBLE (SIGNALING_LT); + +/* { dg-final { scan-assembler {\n\twfkhxb\t} } } */ diff --git a/gcc/testsuite/gcc.target/s390/zvector/autovec.h b/gcc/testsuite/gcc.target/s390/zvector/autovec.h new file mode 100644 index 00000000000..d04e5d7e00e --- /dev/null +++ b/gcc/testsuite/gcc.target/s390/zvector/autovec.h @@ -0,0 +1,41 @@ +#ifndef AUTOVEC_H +#define AUTOVEC_H 1 + +#define QUIET_EQ(x, y) ((x) == (y)) +#define QUIET_GE __builtin_isgreaterequal +#define QUIET_GT __builtin_isgreater +#define QUIET_LE __builtin_islessequal +#define QUIET_LT __builtin_isless +#define QUIET_ORDERED(x, y) (!__builtin_isunordered ((x), (y))) +#define QUIET_UNEQ(x, y) (__builtin_isless ((x), (y)) \ + || __builtin_isgreater ((x), (y))) +#define QUIET_UNORDERED __builtin_isunordered +#define SIGNALING_EQ(x, y) (((x) <= (y)) && ((x) >= (y))) +#define SIGNALING_GE(x, y) ((x) >= (y)) +#define SIGNALING_GT(x, y) ((x) > (y)) +#define SIGNALING_LE(x, y) ((x) <= (y)) +#define SIGNALING_LT(x, y) ((x) < (y)) +#define SIGNALING_LTGT(x, y) (((x) < (y)) || ((x) > (y))) + +#define AUTOVEC(RESULT_TYPE, OP_TYPE, OP) void \ +f (RESULT_TYPE *r, const OP_TYPE *x, const OP_TYPE *y) \ +{ \ + int i; \ +\ + for (i = 0; i < 1000000; i++) \ + { \ + OP_TYPE xi = x[i], yi = y[i]; \ +\ + r[i] = OP (xi, yi); \ + } \ +} + +#define AUTOVEC_DOUBLE(OP) AUTOVEC (long, double, OP) + +#define AUTOVEC_FLOAT(OP) AUTOVEC (int, float, OP) + +typedef __int128 v1ti __attribute__ ((vector_size (16))); +typedef long double v1tf __attribute__ ((vector_size (16))); +#define AUTOVEC_LONG_DOUBLE(OP) AUTOVEC (v1ti, v1tf, OP) + +#endif