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Thu, 26 Sep 2019 09:35:14 -0400 (EDT) From: Andrew Jeffery To: joel@jms.id.au Subject: [PATCH linux dev-5.3 01/15] pinctrl: aspeed-g6: Sort pins for sanity Date: Thu, 26 Sep 2019 23:05:54 +0930 Message-Id: <20190926133608.30566-2-andrew@aj.id.au> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190926133608.30566-1-andrew@aj.id.au> References: <20190926133608.30566-1-andrew@aj.id.au> MIME-Version: 1.0 X-BeenThere: openbmc@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development list for OpenBMC List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrew Jeffery , johnny_huang@aspeedtech.com, openbmc@lists.ozlabs.org Errors-To: openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "openbmc" Some pins crept in that weren't ordered in the list. Signed-off-by: Andrew Jeffery --- drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c index 648ddb7f038a..ff208b7c75a8 100644 --- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c @@ -1574,6 +1574,8 @@ static struct pinctrl_pin_desc aspeed_g6_pins[ASPEED_G6_NR_PINS] = { ASPEED_PINCTRL_PIN(A3), ASPEED_PINCTRL_PIN(AA11), ASPEED_PINCTRL_PIN(AA12), + ASPEED_PINCTRL_PIN(AA16), + ASPEED_PINCTRL_PIN(AA17), ASPEED_PINCTRL_PIN(AA23), ASPEED_PINCTRL_PIN(AA24), ASPEED_PINCTRL_PIN(AA25), @@ -1585,6 +1587,8 @@ static struct pinctrl_pin_desc aspeed_g6_pins[ASPEED_G6_NR_PINS] = { ASPEED_PINCTRL_PIN(AB11), ASPEED_PINCTRL_PIN(AB12), ASPEED_PINCTRL_PIN(AB15), + ASPEED_PINCTRL_PIN(AB16), + ASPEED_PINCTRL_PIN(AB17), ASPEED_PINCTRL_PIN(AB18), ASPEED_PINCTRL_PIN(AB19), ASPEED_PINCTRL_PIN(AB22), @@ -1602,6 +1606,7 @@ static struct pinctrl_pin_desc aspeed_g6_pins[ASPEED_G6_NR_PINS] = { ASPEED_PINCTRL_PIN(AC11), ASPEED_PINCTRL_PIN(AC12), ASPEED_PINCTRL_PIN(AC15), + ASPEED_PINCTRL_PIN(AC16), ASPEED_PINCTRL_PIN(AC17), ASPEED_PINCTRL_PIN(AC18), ASPEED_PINCTRL_PIN(AC19), @@ -1619,6 +1624,7 @@ static struct pinctrl_pin_desc aspeed_g6_pins[ASPEED_G6_NR_PINS] = { ASPEED_PINCTRL_PIN(AD12), ASPEED_PINCTRL_PIN(AD14), ASPEED_PINCTRL_PIN(AD15), + ASPEED_PINCTRL_PIN(AD16), ASPEED_PINCTRL_PIN(AD19), ASPEED_PINCTRL_PIN(AD20), ASPEED_PINCTRL_PIN(AD22), @@ -1634,8 +1640,11 @@ static struct pinctrl_pin_desc aspeed_g6_pins[ASPEED_G6_NR_PINS] = { ASPEED_PINCTRL_PIN(AE12), ASPEED_PINCTRL_PIN(AE14), ASPEED_PINCTRL_PIN(AE15), + ASPEED_PINCTRL_PIN(AE16), ASPEED_PINCTRL_PIN(AE18), ASPEED_PINCTRL_PIN(AE19), + ASPEED_PINCTRL_PIN(AE25), + ASPEED_PINCTRL_PIN(AE26), ASPEED_PINCTRL_PIN(AE7), ASPEED_PINCTRL_PIN(AE8), ASPEED_PINCTRL_PIN(AF10), @@ -1643,6 +1652,8 @@ static struct pinctrl_pin_desc aspeed_g6_pins[ASPEED_G6_NR_PINS] = { ASPEED_PINCTRL_PIN(AF12), ASPEED_PINCTRL_PIN(AF14), ASPEED_PINCTRL_PIN(AF15), + ASPEED_PINCTRL_PIN(AF24), + ASPEED_PINCTRL_PIN(AF25), ASPEED_PINCTRL_PIN(AF7), ASPEED_PINCTRL_PIN(AF8), ASPEED_PINCTRL_PIN(AF9), @@ -1792,17 +1803,6 @@ static struct pinctrl_pin_desc aspeed_g6_pins[ASPEED_G6_NR_PINS] = { ASPEED_PINCTRL_PIN(Y3), ASPEED_PINCTRL_PIN(Y4), ASPEED_PINCTRL_PIN(Y5), - ASPEED_PINCTRL_PIN(AB16), - ASPEED_PINCTRL_PIN(AA17), - ASPEED_PINCTRL_PIN(AB17), - ASPEED_PINCTRL_PIN(AE16), - ASPEED_PINCTRL_PIN(AC16), - ASPEED_PINCTRL_PIN(AA16), - ASPEED_PINCTRL_PIN(AD16), - ASPEED_PINCTRL_PIN(AF25), - ASPEED_PINCTRL_PIN(AE26), - ASPEED_PINCTRL_PIN(AE25), - ASPEED_PINCTRL_PIN(AF24), }; static const struct aspeed_pin_group aspeed_g6_groups[] = { From patchwork Thu Sep 26 13:35:55 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Jeffery X-Patchwork-Id: 1167920 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 46fGL26P3pz9sPK for ; Thu, 26 Sep 2019 23:41:30 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=aj.id.au Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=aj.id.au header.i=@aj.id.au header.b="WGJwBsfF"; dkim=fail reason="signature verification failed" (2048-bit key; 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Thu, 26 Sep 2019 09:35:17 -0400 (EDT) From: Andrew Jeffery To: joel@jms.id.au Subject: [PATCH linux dev-5.3 02/15] pinctrl: aspeed-g6: Fix I2C14 SDA description Date: Thu, 26 Sep 2019 23:05:55 +0930 Message-Id: <20190926133608.30566-3-andrew@aj.id.au> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190926133608.30566-1-andrew@aj.id.au> References: <20190926133608.30566-1-andrew@aj.id.au> MIME-Version: 1.0 X-BeenThere: openbmc@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development list for OpenBMC List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrew Jeffery , johnny_huang@aspeedtech.com, openbmc@lists.ozlabs.org Errors-To: openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "openbmc" The I2C function the pin participated in was incorrectly named SDA14 which lead to a failure to mux: [ 6.884344] No function I2C14 found on pin 7 (7). Found signal(s) MACLINK4, SDA14, GPIOA7 for function(s) MACLINK4, SDA14, GPIOA7 Fixes: 58dc52ad00a0 ("pinctrl: aspeed: Add AST2600 pinmux support") Signed-off-by: Andrew Jeffery --- drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c index ff208b7c75a8..9079655cc818 100644 --- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c @@ -87,7 +87,7 @@ FUNC_GROUP_DECL(MACLINK3, L23); #define K25 7 SIG_EXPR_LIST_DECL_SESG(K25, MACLINK4, MACLINK4, SIG_DESC_SET(SCU410, 7)); -SIG_EXPR_LIST_DECL_SESG(K25, SDA14, SDA14, SIG_DESC_SET(SCU4B0, 7)); +SIG_EXPR_LIST_DECL_SESG(K25, SDA14, I2C14, SIG_DESC_SET(SCU4B0, 7)); PIN_DECL_2(K25, GPIOA7, MACLINK4, SDA14); FUNC_GROUP_DECL(MACLINK4, K25); From patchwork Thu Sep 26 13:35:56 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Jeffery X-Patchwork-Id: 1167922 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 46fGN43Pkpz9sCJ for ; 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Thu, 26 Sep 2019 09:35:19 -0400 (EDT) From: Andrew Jeffery To: joel@jms.id.au Subject: [PATCH linux dev-5.3 03/15] pinctrl: aspeed-g6: Fix I3C3/I3C4 pinmux configuration Date: Thu, 26 Sep 2019 23:05:56 +0930 Message-Id: <20190926133608.30566-4-andrew@aj.id.au> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190926133608.30566-1-andrew@aj.id.au> References: <20190926133608.30566-1-andrew@aj.id.au> MIME-Version: 1.0 X-BeenThere: openbmc@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development list for OpenBMC List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrew Jeffery , johnny_huang@aspeedtech.com, openbmc@lists.ozlabs.org Errors-To: openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "openbmc" From: Johnny Huang The documentation to configure I3C3/FSI1 and I3C4/FSI2 was initially unclear. Fixes: 58dc52ad00a0 ("pinctrl: aspeed: Add AST2600 pinmux support") Signed-off-by: Johnny Huang [AJ: Tweak commit message, resolve rebase conflicts] Signed-off-by: Andrew Jeffery --- drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c | 24 ++++++++-------------- 1 file changed, 8 insertions(+), 16 deletions(-) diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c index 9079655cc818..68b066594461 100644 --- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c @@ -1513,18 +1513,14 @@ FUNC_GROUP_DECL(VB, Y1, Y2, Y3, Y4); * following 4 pins */ #define AF25 244 -SIG_EXPR_LIST_DECL_SEMG(AF25, I3C3SCL, I3C3, I3C3, SIG_DESC_SET(SCU438, 20), - SIG_DESC_SET(SCU4D8, 20)); -SIG_EXPR_LIST_DECL_SESG(AF25, FSI1CLK, FSI1, SIG_DESC_CLEAR(SCU438, 20), - SIG_DESC_SET(SCU4D8, 20)); +SIG_EXPR_LIST_DECL_SEMG(AF25, I3C3SCL, I3C3, I3C3, SIG_DESC_SET(SCU438, 20)); +SIG_EXPR_LIST_DECL_SESG(AF25, FSI1CLK, FSI1, SIG_DESC_SET(SCU4D8, 20)); PIN_DECL_(AF25, SIG_EXPR_LIST_PTR(AF25, I3C3SCL), SIG_EXPR_LIST_PTR(AF25, FSI1CLK)); #define AE26 245 -SIG_EXPR_LIST_DECL_SEMG(AE26, I3C3SDA, I3C3, I3C3, SIG_DESC_SET(SCU438, 21), - SIG_DESC_SET(SCU4D8, 21)); -SIG_EXPR_LIST_DECL_SESG(AE26, FSI1DATA, FSI1, SIG_DESC_CLEAR(SCU438, 21), - SIG_DESC_SET(SCU4D8, 21)); +SIG_EXPR_LIST_DECL_SEMG(AE26, I3C3SDA, I3C3, I3C3, SIG_DESC_SET(SCU438, 21)); +SIG_EXPR_LIST_DECL_SESG(AE26, FSI1DATA, FSI1, SIG_DESC_SET(SCU4D8, 21)); PIN_DECL_(AE26, SIG_EXPR_LIST_PTR(AE26, I3C3SDA), SIG_EXPR_LIST_PTR(AE26, FSI1DATA)); @@ -1533,18 +1529,14 @@ FUNC_DECL_2(I3C3, HVI3C3, I3C3); FUNC_GROUP_DECL(FSI1, AF25, AE26); #define AE25 246 -SIG_EXPR_LIST_DECL_SEMG(AE25, I3C4SCL, I3C4, I3C4, SIG_DESC_SET(SCU438, 22), - SIG_DESC_SET(SCU4D8, 22)); -SIG_EXPR_LIST_DECL_SESG(AE25, FSI2CLK, FSI2, SIG_DESC_CLEAR(SCU438, 22), - SIG_DESC_SET(SCU4D8, 22)); +SIG_EXPR_LIST_DECL_SEMG(AE25, I3C4SCL, I3C4, I3C4, SIG_DESC_SET(SCU438, 22)); +SIG_EXPR_LIST_DECL_SESG(AE25, FSI2CLK, FSI2, SIG_DESC_SET(SCU4D8, 22)); PIN_DECL_(AE25, SIG_EXPR_LIST_PTR(AE25, I3C4SCL), SIG_EXPR_LIST_PTR(AE25, FSI2CLK)); #define AF24 247 -SIG_EXPR_LIST_DECL_SEMG(AF24, I3C4SDA, I3C4, I3C4, SIG_DESC_SET(SCU438, 23), - SIG_DESC_SET(SCU4D8, 23)); -SIG_EXPR_LIST_DECL_SESG(AF24, FSI2DATA, FSI2, SIG_DESC_CLEAR(SCU438, 23), - SIG_DESC_SET(SCU4D8, 23)); +SIG_EXPR_LIST_DECL_SEMG(AF24, I3C4SDA, I3C4, I3C4, SIG_DESC_SET(SCU438, 23)); +SIG_EXPR_LIST_DECL_SESG(AF24, FSI2DATA, FSI2, SIG_DESC_SET(SCU4D8, 23)); PIN_DECL_(AF24, SIG_EXPR_LIST_PTR(AF24, I3C4SDA), SIG_EXPR_LIST_PTR(AF24, FSI2DATA)); From patchwork Thu Sep 26 13:35:57 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Jeffery X-Patchwork-Id: 1167924 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 46fGPv5ckYz9sN1 for ; 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Thu, 26 Sep 2019 09:35:22 -0400 (EDT) From: Andrew Jeffery To: joel@jms.id.au Subject: [PATCH linux dev-5.3 04/15] pinctrl: aspeed-g6: Fix UART13 group pinmux Date: Thu, 26 Sep 2019 23:05:57 +0930 Message-Id: <20190926133608.30566-5-andrew@aj.id.au> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190926133608.30566-1-andrew@aj.id.au> References: <20190926133608.30566-1-andrew@aj.id.au> MIME-Version: 1.0 X-BeenThere: openbmc@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development list for OpenBMC List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrew Jeffery , johnny_huang@aspeedtech.com, openbmc@lists.ozlabs.org Errors-To: openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "openbmc" From: Johnny Huang When UART13G1 be set, pinmux settings in SCU4B8 should be clear. Fixes: 58dc52ad00a0 ("pinctrl: aspeed: Add AST2600 pinmux support") Signed-off-by: Johnny Huang [AJ: Tweak commit message] Signed-off-by: Andrew Jeffery --- drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c index 68b066594461..dc17cf3d3549 100644 --- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c @@ -1262,13 +1262,13 @@ GROUP_DECL(SPI1, AB11, AC11, AA11); #define AD11 206 SIG_EXPR_LIST_DECL_SEMG(AD11, SPI1DQ2, QSPI1, SPI1, SIG_DESC_SET(SCU438, 14)); SIG_EXPR_LIST_DECL_SEMG(AD11, TXD13, UART13G1, UART13, - SIG_DESC_SET(SCU438, 14)); + SIG_DESC_CLEAR(SCU4B8, 2), SIG_DESC_SET(SCU4D8, 14)); PIN_DECL_2(AD11, GPIOZ6, SPI1DQ2, TXD13); #define AF10 207 SIG_EXPR_LIST_DECL_SEMG(AF10, SPI1DQ3, QSPI1, SPI1, SIG_DESC_SET(SCU438, 15)); SIG_EXPR_LIST_DECL_SEMG(AF10, RXD13, UART13G1, UART13, - SIG_DESC_SET(SCU438, 15)); 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Thu, 26 Sep 2019 09:35:24 -0400 (EDT) From: Andrew Jeffery To: joel@jms.id.au Subject: [PATCH linux dev-5.3 05/15] pinctrl: aspeed-g6: Rename SD3 to EMMC and rework pin groups Date: Thu, 26 Sep 2019 23:05:58 +0930 Message-Id: <20190926133608.30566-6-andrew@aj.id.au> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190926133608.30566-1-andrew@aj.id.au> References: <20190926133608.30566-1-andrew@aj.id.au> MIME-Version: 1.0 X-BeenThere: openbmc@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development list for OpenBMC List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrew Jeffery , johnny_huang@aspeedtech.com, openbmc@lists.ozlabs.org Errors-To: openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "openbmc" From: Johnny Huang AST2600 EMMC support 3 types DAT bus sizes (1, 4 and 8-bit), corresponding to 3 groups: EMMCG1, EMMCG4 and EMMCG8 Signed-off-by: Johnny Huang Signed-off-by: Andrew Jeffery --- drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c | 72 ++++++++++------------ drivers/pinctrl/aspeed/pinmux-aspeed.h | 1 + 2 files changed, 33 insertions(+), 40 deletions(-) diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c index dc17cf3d3549..c6800d220920 100644 --- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c @@ -1440,74 +1440,72 @@ FUNC_GROUP_DECL(RGMII2, D4, C2, C1, D3, E4, F5, D2, E3, D1, F4, E2, E1); FUNC_GROUP_DECL(RMII2, D4, C2, C1, D3, D2, D1, F4, E2, E1); #define AB4 232 -SIG_EXPR_LIST_DECL_SESG(AB4, SD3CLK, SD3, SIG_DESC_SET(SCU400, 24)); -PIN_DECL_1(AB4, GPIO18D0, SD3CLK); +SIG_EXPR_LIST_DECL_SEMG(AB4, EMMCCLK, EMMCG1, EMMC, SIG_DESC_SET(SCU400, 24)); +PIN_DECL_1(AB4, GPIO18D0, EMMCCLK); #define AA4 233 -SIG_EXPR_LIST_DECL_SESG(AA4, SD3CMD, SD3, SIG_DESC_SET(SCU400, 25)); -PIN_DECL_1(AA4, GPIO18D1, SD3CMD); +SIG_EXPR_LIST_DECL_SEMG(AA4, EMMCCMD, EMMCG1, EMMC, SIG_DESC_SET(SCU400, 25)); +PIN_DECL_1(AA4, GPIO18D1, EMMCCMD); #define AC4 234 -SIG_EXPR_LIST_DECL_SESG(AC4, SD3DAT0, SD3, SIG_DESC_SET(SCU400, 26)); -PIN_DECL_1(AC4, GPIO18D2, SD3DAT0); +SIG_EXPR_LIST_DECL_SEMG(AC4, EMMCDAT0, EMMCG1, EMMC, SIG_DESC_SET(SCU400, 26)); +PIN_DECL_1(AC4, GPIO18D2, EMMCDAT0); #define AA5 235 -SIG_EXPR_LIST_DECL_SESG(AA5, SD3DAT1, SD3, SIG_DESC_SET(SCU400, 27)); -PIN_DECL_1(AA5, GPIO18D3, SD3DAT1); +SIG_EXPR_LIST_DECL_SEMG(AA5, EMMCDAT1, EMMCG4, EMMC, SIG_DESC_SET(SCU400, 27)); +PIN_DECL_1(AA5, GPIO18D3, EMMCDAT1); #define Y5 236 -SIG_EXPR_LIST_DECL_SESG(Y5, SD3DAT2, SD3, SIG_DESC_SET(SCU400, 28)); -PIN_DECL_1(Y5, GPIO18D4, SD3DAT2); +SIG_EXPR_LIST_DECL_SEMG(Y5, EMMCDAT2, EMMCG4, EMMC, SIG_DESC_SET(SCU400, 28)); +PIN_DECL_1(Y5, GPIO18D4, EMMCDAT2); #define AB5 237 -SIG_EXPR_LIST_DECL_SESG(AB5, SD3DAT3, SD3, SIG_DESC_SET(SCU400, 29)); -PIN_DECL_1(AB5, GPIO18D5, SD3DAT3); +SIG_EXPR_LIST_DECL_SEMG(AB5, EMMCDAT3, EMMCG4, EMMC, SIG_DESC_SET(SCU400, 29)); +PIN_DECL_1(AB5, GPIO18D5, EMMCDAT3); #define AB6 238 -SIG_EXPR_LIST_DECL_SESG(AB6, SD3CD, SD3, SIG_DESC_SET(SCU400, 30)); -PIN_DECL_1(AB6, GPIO18D6, SD3CD); +SIG_EXPR_LIST_DECL_SEMG(AB6, EMMCCD, EMMCG1, EMMC, SIG_DESC_SET(SCU400, 30)); +PIN_DECL_1(AB6, GPIO18D6, EMMCCD); #define AC5 239 -SIG_EXPR_LIST_DECL_SESG(AC5, SD3WP, SD3, SIG_DESC_SET(SCU400, 31)); -PIN_DECL_1(AC5, GPIO18D7, SD3WP); +SIG_EXPR_LIST_DECL_SEMG(AC5, EMMCWP, EMMCG1, EMMC, SIG_DESC_SET(SCU400, 31)); +PIN_DECL_1(AC5, GPIO18D7, EMMCWP); -FUNC_GROUP_DECL(SD3, AB4, AA4, AC4, AA5, Y5, AB5, AB6, AC5); +GROUP_DECL(EMMCG1, AB4, AA4, AC4, AB6, AC5); +GROUP_DECL(EMMCG4, AB4, AA4, AC4, AA5, Y5, AB5, AB6, AC5); #define Y1 240 SIG_EXPR_LIST_DECL_SEMG(Y1, FWSPIDCS, FWSPID, FWSPID, SIG_DESC_SET(SCU500, 3)); SIG_EXPR_LIST_DECL_SESG(Y1, VBCS, VB, SIG_DESC_SET(SCU500, 5)); -SIG_EXPR_LIST_DECL_SESG(Y1, SD3DAT4, SD3DAT4, SIG_DESC_SET(SCU404, 0)); -PIN_DECL_3(Y1, GPIO18E0, FWSPIDCS, VBCS, SD3DAT4); -FUNC_GROUP_DECL(SD3DAT4, Y1); +SIG_EXPR_LIST_DECL_SEMG(Y1, EMMCDAT4, EMMCG8, EMMC, SIG_DESC_SET(SCU404, 0)); +PIN_DECL_3(Y1, GPIO18E0, FWSPIDCS, VBCS, EMMCDAT4); #define Y2 241 SIG_EXPR_LIST_DECL_SEMG(Y2, FWSPIDCK, FWSPID, FWSPID, SIG_DESC_SET(SCU500, 3)); SIG_EXPR_LIST_DECL_SESG(Y2, VBCK, VB, SIG_DESC_SET(SCU500, 5)); -SIG_EXPR_LIST_DECL_SESG(Y2, SD3DAT5, SD3DAT5, SIG_DESC_SET(SCU404, 1)); -PIN_DECL_3(Y2, GPIO18E1, FWSPIDCK, VBCK, SD3DAT5); -FUNC_GROUP_DECL(SD3DAT5, Y2); +SIG_EXPR_LIST_DECL_SEMG(Y2, EMMCDAT5, EMMCG8, EMMC, SIG_DESC_SET(SCU404, 1)); +PIN_DECL_3(Y2, GPIO18E1, FWSPIDCK, VBCK, EMMCDAT5); #define Y3 242 SIG_EXPR_LIST_DECL_SEMG(Y3, FWSPIDMOSI, FWSPID, FWSPID, SIG_DESC_SET(SCU500, 3)); SIG_EXPR_LIST_DECL_SESG(Y3, VBMOSI, VB, SIG_DESC_SET(SCU500, 5)); -SIG_EXPR_LIST_DECL_SESG(Y3, SD3DAT6, SD3DAT6, SIG_DESC_SET(SCU404, 2)); -PIN_DECL_3(Y3, GPIO18E2, FWSPIDMOSI, VBMOSI, SD3DAT6); -FUNC_GROUP_DECL(SD3DAT6, Y3); +SIG_EXPR_LIST_DECL_SEMG(Y3, EMMCDAT6, EMMCG8, EMMC, SIG_DESC_SET(SCU404, 2)); +PIN_DECL_3(Y3, GPIO18E2, FWSPIDMOSI, VBMOSI, EMMCDAT6); #define Y4 243 SIG_EXPR_LIST_DECL_SEMG(Y4, FWSPIDMISO, FWSPID, FWSPID, SIG_DESC_SET(SCU500, 3)); SIG_EXPR_LIST_DECL_SESG(Y4, VBMISO, VB, SIG_DESC_SET(SCU500, 5)); -SIG_EXPR_LIST_DECL_SESG(Y4, SD3DAT7, SD3DAT7, SIG_DESC_SET(SCU404, 3)); -PIN_DECL_3(Y4, GPIO18E3, FWSPIDMISO, VBMISO, SD3DAT7); -FUNC_GROUP_DECL(SD3DAT7, Y4); +SIG_EXPR_LIST_DECL_SEMG(Y4, EMMCDAT7, EMMCG8, EMMC, SIG_DESC_SET(SCU404, 3)); +PIN_DECL_3(Y4, GPIO18E3, FWSPIDMISO, VBMISO, EMMCDAT7); GROUP_DECL(FWSPID, Y1, Y2, Y3, Y4); GROUP_DECL(FWQSPID, Y1, Y2, Y3, Y4, AE12, AF12); +GROUP_DECL(EMMCG8, AB4, AA4, AC4, AA5, Y5, AB5, AB6, AC5, Y1, Y2, Y3, Y4); FUNC_DECL_2(FWSPID, FWSPID, FWQSPID); FUNC_GROUP_DECL(VB, Y1, Y2, Y3, Y4); - +FUNC_DECL_3(EMMC, EMMCG1, EMMCG4, EMMCG8); /* * FIXME: Confirm bits and priorities are the right way around for the * following 4 pins @@ -1968,11 +1966,9 @@ static const struct aspeed_pin_group aspeed_g6_groups[] = { ASPEED_PINCTRL_GROUP(SALT9G1), ASPEED_PINCTRL_GROUP(SD1), ASPEED_PINCTRL_GROUP(SD2), - ASPEED_PINCTRL_GROUP(SD3), - ASPEED_PINCTRL_GROUP(SD3DAT4), - ASPEED_PINCTRL_GROUP(SD3DAT5), - ASPEED_PINCTRL_GROUP(SD3DAT6), - ASPEED_PINCTRL_GROUP(SD3DAT7), + ASPEED_PINCTRL_GROUP(EMMCG1), + ASPEED_PINCTRL_GROUP(EMMCG4), + ASPEED_PINCTRL_GROUP(EMMCG8), ASPEED_PINCTRL_GROUP(SGPM1), ASPEED_PINCTRL_GROUP(SGPS1), ASPEED_PINCTRL_GROUP(SIOONCTRL), @@ -2051,6 +2047,7 @@ static const struct aspeed_pin_function aspeed_g6_functions[] = { ASPEED_PINCTRL_FUNC(ADC8), ASPEED_PINCTRL_FUNC(ADC9), ASPEED_PINCTRL_FUNC(BMCINT), + ASPEED_PINCTRL_FUNC(EMMC), ASPEED_PINCTRL_FUNC(ESPI), ASPEED_PINCTRL_FUNC(ESPIALT), ASPEED_PINCTRL_FUNC(FSI1), @@ -2183,11 +2180,6 @@ static const struct aspeed_pin_function aspeed_g6_functions[] = { ASPEED_PINCTRL_FUNC(SALT9), ASPEED_PINCTRL_FUNC(SD1), ASPEED_PINCTRL_FUNC(SD2), - ASPEED_PINCTRL_FUNC(SD3), - ASPEED_PINCTRL_FUNC(SD3DAT4), - ASPEED_PINCTRL_FUNC(SD3DAT5), - ASPEED_PINCTRL_FUNC(SD3DAT6), - ASPEED_PINCTRL_FUNC(SD3DAT7), ASPEED_PINCTRL_FUNC(SGPM1), ASPEED_PINCTRL_FUNC(SGPS1), ASPEED_PINCTRL_FUNC(SIOONCTRL), diff --git a/drivers/pinctrl/aspeed/pinmux-aspeed.h b/drivers/pinctrl/aspeed/pinmux-aspeed.h index a2c0d52e4f7b..08c70ea5b582 100644 --- a/drivers/pinctrl/aspeed/pinmux-aspeed.h +++ b/drivers/pinctrl/aspeed/pinmux-aspeed.h @@ -738,6 +738,7 @@ struct aspeed_pin_desc { static const char *FUNC_SYM(func)[] = { __VA_ARGS__ } #define FUNC_DECL_2(func, one, two) FUNC_DECL_(func, #one, #two) +#define FUNC_DECL_3(func, one, two, three) FUNC_DECL_(func, #one, #two, #three) #define FUNC_GROUP_DECL(func, ...) \ GROUP_DECL(func, __VA_ARGS__); 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Thu, 26 Sep 2019 09:35:26 -0400 (EDT) From: Andrew Jeffery To: joel@jms.id.au Subject: [PATCH linux dev-5.3 06/15] pinctrl: aspeed-g6: Add AST2600 I3C1 and I3C2 pinmux config Date: Thu, 26 Sep 2019 23:05:59 +0930 Message-Id: <20190926133608.30566-7-andrew@aj.id.au> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190926133608.30566-1-andrew@aj.id.au> References: <20190926133608.30566-1-andrew@aj.id.au> MIME-Version: 1.0 X-BeenThere: openbmc@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development list for OpenBMC List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrew Jeffery , johnny_huang@aspeedtech.com, openbmc@lists.ozlabs.org Errors-To: openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "openbmc" From: Johnny Huang These pins only expose a single function but are not fixed-function as their I3C capability can be disabled. Signed-off-by: Johnny Huang [AJ: Tweak commit message, sort pins list] Signed-off-by: Andrew Jeffery --- drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c | 30 +++++++++++++++++++++- 1 file changed, 29 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c index c6800d220920..49fc4824ccee 100644 --- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c @@ -37,7 +37,7 @@ #define SCU510 0x510 /* Hardware Strap 2 */ #define SCU694 0x694 /* Multi-function Pin Control #25 */ -#define ASPEED_G6_NR_PINS 248 +#define ASPEED_G6_NR_PINS 252 #define M24 0 SIG_EXPR_LIST_DECL_SESG(M24, MDC3, MDIO3, SIG_DESC_SET(SCU410, 0)); @@ -1542,6 +1542,26 @@ GROUP_DECL(I3C4, AE25, AF24); FUNC_DECL_2(I3C4, HVI3C4, I3C4); FUNC_GROUP_DECL(FSI2, AE25, AF24); +#define AF23 248 +SIG_EXPR_LIST_DECL_SESG(AF23, I3C1SCL, I3C1, SIG_DESC_SET(SCU438, 16)); +PIN_DECL_(AF23, SIG_EXPR_LIST_PTR(AF23, I3C1SCL)); + +#define AE24 249 +SIG_EXPR_LIST_DECL_SESG(AE24, I3C1SDA, I3C1, SIG_DESC_SET(SCU438, 17)); +PIN_DECL_(AE24, SIG_EXPR_LIST_PTR(AE24, I3C1SDA)); + +FUNC_GROUP_DECL(I3C1, AF23, AE24); + +#define AF22 250 +SIG_EXPR_LIST_DECL_SESG(AF22, I3C2SCL, I3C2, SIG_DESC_SET(SCU438, 18)); +PIN_DECL_(AF22, SIG_EXPR_LIST_PTR(AF22, I3C2SCL)); + +#define AE22 251 +SIG_EXPR_LIST_DECL_SESG(AE22, I3C2SDA, I3C2, SIG_DESC_SET(SCU438, 19)); +PIN_DECL_(AE22, SIG_EXPR_LIST_PTR(AE22, I3C2SDA)); + +FUNC_GROUP_DECL(I3C2, AF22, AE22); + /* Pins, groups and functions are sort(1):ed alphabetically for sanity */ static struct pinctrl_pin_desc aspeed_g6_pins[ASPEED_G6_NR_PINS] = { @@ -1633,6 +1653,8 @@ static struct pinctrl_pin_desc aspeed_g6_pins[ASPEED_G6_NR_PINS] = { ASPEED_PINCTRL_PIN(AE16), ASPEED_PINCTRL_PIN(AE18), ASPEED_PINCTRL_PIN(AE19), + ASPEED_PINCTRL_PIN(AE22), + ASPEED_PINCTRL_PIN(AE24), ASPEED_PINCTRL_PIN(AE25), ASPEED_PINCTRL_PIN(AE26), ASPEED_PINCTRL_PIN(AE7), @@ -1642,6 +1664,8 @@ static struct pinctrl_pin_desc aspeed_g6_pins[ASPEED_G6_NR_PINS] = { ASPEED_PINCTRL_PIN(AF12), ASPEED_PINCTRL_PIN(AF14), ASPEED_PINCTRL_PIN(AF15), + ASPEED_PINCTRL_PIN(AF22), + ASPEED_PINCTRL_PIN(AF23), ASPEED_PINCTRL_PIN(AF24), ASPEED_PINCTRL_PIN(AF25), ASPEED_PINCTRL_PIN(AF7), @@ -1855,6 +1879,8 @@ static const struct aspeed_pin_group aspeed_g6_groups[] = { ASPEED_PINCTRL_GROUP(I2C7), ASPEED_PINCTRL_GROUP(I2C8), ASPEED_PINCTRL_GROUP(I2C9), + ASPEED_PINCTRL_GROUP(I3C1), + ASPEED_PINCTRL_GROUP(I3C2), ASPEED_PINCTRL_GROUP(I3C3), ASPEED_PINCTRL_GROUP(I3C4), ASPEED_PINCTRL_GROUP(I3C5), @@ -2087,6 +2113,8 @@ static const struct aspeed_pin_function aspeed_g6_functions[] = { ASPEED_PINCTRL_FUNC(I2C7), ASPEED_PINCTRL_FUNC(I2C8), ASPEED_PINCTRL_FUNC(I2C9), + ASPEED_PINCTRL_FUNC(I3C1), + ASPEED_PINCTRL_FUNC(I3C2), ASPEED_PINCTRL_FUNC(I3C3), ASPEED_PINCTRL_FUNC(I3C4), ASPEED_PINCTRL_FUNC(I3C5), From patchwork Thu Sep 26 13:36:00 2019 Content-Type: text/plain; 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PCIe EHCI to Hub 2. Hub to PHY 3. BMC EHCI to PHY 4. PCIe EHCI to PHY Port B support 3 modes: 1. USB1.1 HID controller 2. USB2.0 Device controller 3. BMC EHCI port2 Implement pinmux support by mapping each ports' functions onto a single pin group for each port. Signed-off-by: Johnny Huang Signed-off-by: Andrew Jeffery --- drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c | 69 +++++++++++++++++++++- drivers/pinctrl/aspeed/pinmux-aspeed.h | 1 + 2 files changed, 69 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c index 49fc4824ccee..22e6c07149c3 100644 --- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c @@ -26,6 +26,7 @@ #define SCU430 0x430 /* Multi-function Pin Control #8 */ #define SCU434 0x434 /* Multi-function Pin Control #9 */ #define SCU438 0x438 /* Multi-function Pin Control #10 */ +#define SCU440 0x440 /* USB Multi-function Pin Control #12 */ #define SCU450 0x450 /* Multi-function Pin Control #14 */ #define SCU4B0 0x4B0 /* Multi-function Pin Control #17 */ #define SCU4B4 0x4B4 /* Multi-function Pin Control #18 */ @@ -36,8 +37,9 @@ #define SCU500 0x500 /* Hardware Strap 1 */ #define SCU510 0x510 /* Hardware Strap 2 */ #define SCU694 0x694 /* Multi-function Pin Control #25 */ +#define SCUC20 0xC20 /* PCIE configuration Setting Control */ -#define ASPEED_G6_NR_PINS 252 +#define ASPEED_G6_NR_PINS 256 #define M24 0 SIG_EXPR_LIST_DECL_SESG(M24, MDC3, MDIO3, SIG_DESC_SET(SCU410, 0)); @@ -1562,6 +1564,58 @@ PIN_DECL_(AE22, SIG_EXPR_LIST_PTR(AE22, I3C2SDA)); FUNC_GROUP_DECL(I3C2, AF22, AE22); +#define USB2ADP_DESC { ASPEED_IP_SCU, SCU440, GENMASK(25, 24), 0, 0 } +#define USB2AD_DESC { ASPEED_IP_SCU, SCU440, GENMASK(25, 24), 1, 0 } +#define USB2AH_DESC { ASPEED_IP_SCU, SCU440, GENMASK(25, 24), 2, 0 } +#define USB2AHP_DESC { ASPEED_IP_SCU, SCU440, GENMASK(25, 24), 3, 0 } +#define USB11BHID_DESC { ASPEED_IP_SCU, SCU440, GENMASK(29, 28), 0, 0 } +#define USB2BD_DESC { ASPEED_IP_SCU, SCU440, GENMASK(29, 28), 1, 0 } +#define USB2BH_DESC { ASPEED_IP_SCU, SCU440, GENMASK(29, 28), 2, 0 } + +#define A4 252 +SIG_EXPR_LIST_DECL_SEMG(A4, USB2ADPDP, USBA, USB2ADP, USB2ADP_DESC, + SIG_DESC_SET(SCUC20, 16)); +SIG_EXPR_LIST_DECL_SEMG(A4, USB2ADDP, USBA, USB2AD, USB2AD_DESC); +SIG_EXPR_LIST_DECL_SEMG(A4, USB2AHDP, USBA, USB2AH, USB2AH_DESC); +SIG_EXPR_LIST_DECL_SEMG(A4, USB2AHPDP, USBA, USB2AHP, USB2AHP_DESC); +PIN_DECL_(A4, SIG_EXPR_LIST_PTR(A4, USB2ADPDP), SIG_EXPR_LIST_PTR(A4, USB2ADDP), + SIG_EXPR_LIST_PTR(A4, USB2AHDP)); + +#define B4 253 +SIG_EXPR_LIST_DECL_SEMG(B4, USB2ADPDN, USBA, USB2ADP, USB2ADP_DESC); +SIG_EXPR_LIST_DECL_SEMG(B4, USB2ADDN, USBA, USB2AD, USB2AD_DESC); +SIG_EXPR_LIST_DECL_SEMG(B4, USB2AHDN, USBA, USB2AH, USB2AH_DESC); +SIG_EXPR_LIST_DECL_SEMG(B4, USB2AHPDN, USBA, USB2AHP, USB2AHP_DESC); +PIN_DECL_(B4, SIG_EXPR_LIST_PTR(B4, USB2ADPDN), SIG_EXPR_LIST_PTR(B4, USB2ADDN), + SIG_EXPR_LIST_PTR(B4, USB2AHDN)); + +GROUP_DECL(USBA, A4, B4); + +FUNC_DECL_1(USB2ADP, USBA); +FUNC_DECL_1(USB2AD, USBA); +FUNC_DECL_1(USB2AH, USBA); +FUNC_DECL_1(USB2AHP, USBA); + +#define A6 254 +SIG_EXPR_LIST_DECL_SEMG(A6, USB11BDP, USBB, USB11BHID, USB11BHID_DESC); +SIG_EXPR_LIST_DECL_SEMG(A6, USB2BDDP, USBB, USB2BD, USB2BD_DESC); +SIG_EXPR_LIST_DECL_SEMG(A6, USB2BHDP, USBB, USB2BH, USB2BH_DESC); +PIN_DECL_(A6, SIG_EXPR_LIST_PTR(A6, USB11BDP), SIG_EXPR_LIST_PTR(A6, USB2BDDP), + SIG_EXPR_LIST_PTR(A6, USB2BHDP)); + +#define B6 255 +SIG_EXPR_LIST_DECL_SEMG(B6, USB11BDN, USBB, USB11BHID, USB11BHID_DESC); +SIG_EXPR_LIST_DECL_SEMG(B6, USB2BDDN, USBB, USB2BD, USB2BD_DESC); +SIG_EXPR_LIST_DECL_SEMG(B6, USB2BHDN, USBB, USB2BH, USB2BH_DESC); +PIN_DECL_(B6, SIG_EXPR_LIST_PTR(B6, USB11BDN), SIG_EXPR_LIST_PTR(B6, USB2BDDN), + SIG_EXPR_LIST_PTR(B6, USB2BHDN)); + +GROUP_DECL(USBB, A6, B6); + +FUNC_DECL_1(USB11BHID, USBB); +FUNC_DECL_1(USB2BD, USBB); +FUNC_DECL_1(USB2BH, USBB); + /* Pins, groups and functions are sort(1):ed alphabetically for sanity */ static struct pinctrl_pin_desc aspeed_g6_pins[ASPEED_G6_NR_PINS] = { @@ -1582,6 +1636,8 @@ static struct pinctrl_pin_desc aspeed_g6_pins[ASPEED_G6_NR_PINS] = { ASPEED_PINCTRL_PIN(A24), ASPEED_PINCTRL_PIN(A25), ASPEED_PINCTRL_PIN(A3), + ASPEED_PINCTRL_PIN(A4), + ASPEED_PINCTRL_PIN(A6), ASPEED_PINCTRL_PIN(AA11), ASPEED_PINCTRL_PIN(AA12), ASPEED_PINCTRL_PIN(AA16), @@ -1686,6 +1742,8 @@ static struct pinctrl_pin_desc aspeed_g6_pins[ASPEED_G6_NR_PINS] = { ASPEED_PINCTRL_PIN(B25), ASPEED_PINCTRL_PIN(B26), ASPEED_PINCTRL_PIN(B3), + ASPEED_PINCTRL_PIN(B4), + ASPEED_PINCTRL_PIN(B6), ASPEED_PINCTRL_PIN(C1), ASPEED_PINCTRL_PIN(C11), ASPEED_PINCTRL_PIN(C12), @@ -2046,6 +2104,8 @@ static const struct aspeed_pin_group aspeed_g6_groups[] = { ASPEED_PINCTRL_GROUP(UART7), ASPEED_PINCTRL_GROUP(UART8), ASPEED_PINCTRL_GROUP(UART9), + ASPEED_PINCTRL_GROUP(USBA), + ASPEED_PINCTRL_GROUP(USBB), ASPEED_PINCTRL_GROUP(VB), ASPEED_PINCTRL_GROUP(VGAHS), ASPEED_PINCTRL_GROUP(VGAVS), @@ -2257,6 +2317,13 @@ static const struct aspeed_pin_function aspeed_g6_functions[] = { ASPEED_PINCTRL_FUNC(UART7), ASPEED_PINCTRL_FUNC(UART8), ASPEED_PINCTRL_FUNC(UART9), + ASPEED_PINCTRL_FUNC(USB11BHID), + ASPEED_PINCTRL_FUNC(USB2AD), + ASPEED_PINCTRL_FUNC(USB2ADP), + ASPEED_PINCTRL_FUNC(USB2AH), + ASPEED_PINCTRL_FUNC(USB2AHP), + ASPEED_PINCTRL_FUNC(USB2BD), + ASPEED_PINCTRL_FUNC(USB2BH), ASPEED_PINCTRL_FUNC(VB), ASPEED_PINCTRL_FUNC(VGAHS), ASPEED_PINCTRL_FUNC(VGAVS), diff --git a/drivers/pinctrl/aspeed/pinmux-aspeed.h b/drivers/pinctrl/aspeed/pinmux-aspeed.h index 08c70ea5b582..31d903953c68 100644 --- a/drivers/pinctrl/aspeed/pinmux-aspeed.h +++ b/drivers/pinctrl/aspeed/pinmux-aspeed.h @@ -737,6 +737,7 @@ struct aspeed_pin_desc { #define FUNC_DECL_(func, ...) \ static const char *FUNC_SYM(func)[] = { __VA_ARGS__ } +#define FUNC_DECL_1(func, group) FUNC_DECL_(func, #group) #define FUNC_DECL_2(func, one, two) FUNC_DECL_(func, #one, #two) #define FUNC_DECL_3(func, one, two, three) FUNC_DECL_(func, #one, #two, #three) From patchwork Thu Sep 26 13:36:01 2019 Content-Type: text/plain; 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b=zZhx5jk+ HtUZWn2ou57Jf/kGmYmaS5oJcxE6Zb89QuSpTCfhg4cM9prw8LHZM+V7NQtjIU7a BC8b0HpXl9QXh6tJXXEB38ttIO4G7U5LtcNyCnaFSfxSnLNNYCeVvmmQQe8kkpGx u4cD/CBEmmz0W2WmBnmQjzwfen08Nr11cST4ak9aAqdF/5oCMAgPopejR9qRstWa 5R5M6wkvP9STxB4rmY0hfpFJ2x8mZwsUNba7OAgZEk61A1tn6240ZBLcuBwEAEGF wOeB0GybNOWN+FQnReW4qQdP6YyEsaT/M3pMDm+Jz3WLTwgZlXNgw7O+YewlQcWV SBg1uRoTNhTGEQ== X-ME-Sender: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgedufedrfeeggdeiiecutefuodetggdotefrodftvf curfhrohhfihhlvgemucfhrghsthforghilhdpqfgfvfdpuffrtefokffrpgfnqfghnecu uegrihhlohhuthemuceftddtnecunecujfgurhephffvufffkffojghfggfgsedtkeertd ertddtnecuhfhrohhmpeetnhgurhgvficulfgvfhhfvghrhicuoegrnhgurhgvfiesrghj rdhiugdrrghuqeenucfkphepvddtfedrheejrddvudehrddujeeknecurfgrrhgrmhepmh grihhlfhhrohhmpegrnhgurhgvfiesrghjrdhiugdrrghunecuvehluhhsthgvrhfuihii vgephe X-ME-Proxy: Received: from mistburn.lan (203-57-215-178.dyn.iinet.net.au [203.57.215.178]) by mail.messagingengine.com (Postfix) with ESMTPA id 1ECD2D6005B; Thu, 26 Sep 2019 09:35:31 -0400 (EDT) From: Andrew Jeffery To: joel@jms.id.au Subject: [PATCH linux dev-5.3 08/15] pinctrl: aspeed: Add ASPEED_SB_PINCONF() helper Date: Thu, 26 Sep 2019 23:06:01 +0930 Message-Id: <20190926133608.30566-9-andrew@aj.id.au> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190926133608.30566-1-andrew@aj.id.au> References: <20190926133608.30566-1-andrew@aj.id.au> MIME-Version: 1.0 X-BeenThere: openbmc@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development list for OpenBMC List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrew Jeffery , johnny_huang@aspeedtech.com, openbmc@lists.ozlabs.org Errors-To: openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "openbmc" From: Johnny Huang This helper macro is for declaring single bit (SB) mask pinconf, and is used to prepare for modifying aspeed_pin_config structure, the aspeed_pin_config structure @bit variable will be modified to @mask. This case is common in the AST2400/AST2500 which the mask is a single bit. Signed-off-by: Johnny Huang Signed-off-by: Andrew Jeffery --- drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c | 160 ++++++++-------- drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c | 202 ++++++++++----------- drivers/pinctrl/aspeed/pinctrl-aspeed.h | 7 + 3 files changed, 188 insertions(+), 181 deletions(-) diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c index 95ea593fa29d..c56ded0ac57e 100644 --- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c @@ -2439,88 +2439,88 @@ static const struct aspeed_pin_function aspeed_g4_functions[] = { static const struct aspeed_pin_config aspeed_g4_configs[] = { /* GPIO banks ranges [A, B], [D, J], [M, R] */ - { PIN_CONFIG_BIAS_PULL_DOWN, { D6, D5 }, SCU8C, 16 }, - { PIN_CONFIG_BIAS_DISABLE, { D6, D5 }, SCU8C, 16 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { J21, E18 }, SCU8C, 17 }, - { PIN_CONFIG_BIAS_DISABLE, { J21, E18 }, SCU8C, 17 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { A18, E15 }, SCU8C, 19 }, - { PIN_CONFIG_BIAS_DISABLE, { A18, E15 }, SCU8C, 19 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { D15, B14 }, SCU8C, 20 }, - { PIN_CONFIG_BIAS_DISABLE, { D15, B14 }, SCU8C, 20 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { D18, C17 }, SCU8C, 21 }, - { PIN_CONFIG_BIAS_DISABLE, { D18, C17 }, SCU8C, 21 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { A14, U18 }, SCU8C, 22 }, - { PIN_CONFIG_BIAS_DISABLE, { A14, U18 }, SCU8C, 22 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { A8, E7 }, SCU8C, 23 }, - { PIN_CONFIG_BIAS_DISABLE, { A8, E7 }, SCU8C, 23 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { C22, E20 }, SCU8C, 24 }, - { PIN_CONFIG_BIAS_DISABLE, { C22, E20 }, SCU8C, 24 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { J5, T1 }, SCU8C, 25 }, - { PIN_CONFIG_BIAS_DISABLE, { J5, T1 }, SCU8C, 25 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { U1, U5 }, SCU8C, 26 }, - { PIN_CONFIG_BIAS_DISABLE, { U1, U5 }, SCU8C, 26 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { V3, V5 }, SCU8C, 27 }, - { PIN_CONFIG_BIAS_DISABLE, { V3, V5 }, SCU8C, 27 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { W4, AB2 }, SCU8C, 28 }, - { PIN_CONFIG_BIAS_DISABLE, { W4, AB2 }, SCU8C, 28 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { V6, V7 }, SCU8C, 29 }, - { PIN_CONFIG_BIAS_DISABLE, { V6, V7 }, SCU8C, 29 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { Y6, AB7 }, SCU8C, 30 }, - { PIN_CONFIG_BIAS_DISABLE, { Y6, AB7 }, SCU8C, 30 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { V20, A5 }, SCU8C, 31 }, - { PIN_CONFIG_BIAS_DISABLE, { V20, A5 }, SCU8C, 31 }, + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, D6, D5, SCU8C, 16), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, D6, D5, SCU8C, 16), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, J21, E18, SCU8C, 17), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, J21, E18, SCU8C, 17), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, A18, E15, SCU8C, 19), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, A18, E15, SCU8C, 19), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, D15, B14, SCU8C, 20), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, D15, B14, SCU8C, 20), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, D18, C17, SCU8C, 21), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, D18, C17, SCU8C, 21), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, A14, U18, SCU8C, 22), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, A14, U18, SCU8C, 22), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, A8, E7, SCU8C, 23), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, A8, E7, SCU8C, 23), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, C22, E20, SCU8C, 24), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, C22, E20, SCU8C, 24), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, J5, T1, SCU8C, 25), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, J5, T1, SCU8C, 25), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, U1, U5, SCU8C, 26), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, U1, U5, SCU8C, 26), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, V3, V5, SCU8C, 27), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, V3, V5, SCU8C, 27), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, W4, AB2, SCU8C, 28), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, W4, AB2, SCU8C, 28), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, V6, V7, SCU8C, 29), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, V6, V7, SCU8C, 29), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, Y6, AB7, SCU8C, 30), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, Y6, AB7, SCU8C, 30), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, V20, A5, SCU8C, 31), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, V20, A5, SCU8C, 31), /* GPIOs T[0-5] (RGMII1 Tx pins) */ - { PIN_CONFIG_DRIVE_STRENGTH, { A12, A13 }, SCU90, 9 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { A12, A13 }, SCU90, 12 }, - { PIN_CONFIG_BIAS_DISABLE, { A12, A13 }, SCU90, 12 }, + ASPEED_SB_PINCONF(PIN_CONFIG_DRIVE_STRENGTH, A12, A13, SCU90, 9), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, A12, A13, SCU90, 12), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, A12, A13, SCU90, 12), /* GPIOs T[6-7], U[0-3] (RGMII2 TX pins) */ - { PIN_CONFIG_DRIVE_STRENGTH, { D9, D10 }, SCU90, 11 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { D9, D10 }, SCU90, 14 }, - { PIN_CONFIG_BIAS_DISABLE, { D9, D10 }, SCU90, 14 }, + ASPEED_SB_PINCONF(PIN_CONFIG_DRIVE_STRENGTH, D9, D10, SCU90, 11), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, D9, D10, SCU90, 14), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, D9, D10, SCU90, 14), /* GPIOs U[4-7], V[0-1] (RGMII1 Rx pins) */ - { PIN_CONFIG_BIAS_PULL_DOWN, { E11, E10 }, SCU90, 13 }, - { PIN_CONFIG_BIAS_DISABLE, { E11, E10 }, SCU90, 13 }, + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, E11, E10, SCU90, 13), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, E11, E10, SCU90, 13), /* GPIOs V[2-7] (RGMII2 Rx pins) */ - { PIN_CONFIG_BIAS_PULL_DOWN, { C9, C8 }, SCU90, 15 }, - { PIN_CONFIG_BIAS_DISABLE, { C9, C8 }, SCU90, 15 }, + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, C9, C8, SCU90, 15), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, C9, C8, SCU90, 15), /* ADC pull-downs (SCUA8[19:4]) */ - { PIN_CONFIG_BIAS_PULL_DOWN, { L5, L5 }, SCUA8, 4 }, - { PIN_CONFIG_BIAS_DISABLE, { L5, L5 }, SCUA8, 4 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { L4, L4 }, SCUA8, 5 }, - { PIN_CONFIG_BIAS_DISABLE, { L4, L4 }, SCUA8, 5 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { L3, L3 }, SCUA8, 6 }, - { PIN_CONFIG_BIAS_DISABLE, { L3, L3 }, SCUA8, 6 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { L2, L2 }, SCUA8, 7 }, - { PIN_CONFIG_BIAS_DISABLE, { L2, L2 }, SCUA8, 7 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { L1, L1 }, SCUA8, 8 }, - { PIN_CONFIG_BIAS_DISABLE, { L1, L1 }, SCUA8, 8 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { M5, M5 }, SCUA8, 9 }, - { PIN_CONFIG_BIAS_DISABLE, { M5, M5 }, SCUA8, 9 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { M4, M4 }, SCUA8, 10 }, - { PIN_CONFIG_BIAS_DISABLE, { M4, M4 }, SCUA8, 10 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { M3, M3 }, SCUA8, 11 }, - { PIN_CONFIG_BIAS_DISABLE, { M3, M3 }, SCUA8, 11 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { M2, M2 }, SCUA8, 12 }, - { PIN_CONFIG_BIAS_DISABLE, { M2, M2 }, SCUA8, 12 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { M1, M1 }, SCUA8, 13 }, - { PIN_CONFIG_BIAS_DISABLE, { M1, M1 }, SCUA8, 13 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { N5, N5 }, SCUA8, 14 }, - { PIN_CONFIG_BIAS_DISABLE, { N5, N5 }, SCUA8, 14 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { N4, N4 }, SCUA8, 15 }, - { PIN_CONFIG_BIAS_DISABLE, { N4, N4 }, SCUA8, 15 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { N3, N3 }, SCUA8, 16 }, - { PIN_CONFIG_BIAS_DISABLE, { N3, N3 }, SCUA8, 16 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { N2, N2 }, SCUA8, 17 }, - { PIN_CONFIG_BIAS_DISABLE, { N2, N2 }, SCUA8, 17 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { N1, N1 }, SCUA8, 18 }, - { PIN_CONFIG_BIAS_DISABLE, { N1, N1 }, SCUA8, 18 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { P5, P5 }, SCUA8, 19 }, - { PIN_CONFIG_BIAS_DISABLE, { P5, P5 }, SCUA8, 19 }, + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, L5, L5, SCUA8, 4), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, L5, L5, SCUA8, 4), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, L4, L4, SCUA8, 5), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, L4, L4, SCUA8, 5), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, L3, L3, SCUA8, 6), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, L3, L3, SCUA8, 6), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, L2, L2, SCUA8, 7), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, L2, L2, SCUA8, 7), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, L1, L1, SCUA8, 8), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, L1, L1, SCUA8, 8), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, M5, M5, SCUA8, 9), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, M5, M5, SCUA8, 9), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, M4, M4, SCUA8, 10), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, M4, M4, SCUA8, 10), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, M3, M3, SCUA8, 11), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, M3, M3, SCUA8, 11), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, M2, M2, SCUA8, 12), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, M2, M2, SCUA8, 12), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, M1, M1, SCUA8, 13), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, M1, M1, SCUA8, 13), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, N5, N5, SCUA8, 14), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, N5, N5, SCUA8, 14), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, N4, N4, SCUA8, 15), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, N4, N4, SCUA8, 15), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, N3, N3, SCUA8, 16), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, N3, N3, SCUA8, 16), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, N2, N2, SCUA8, 17), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, N2, N2, SCUA8, 17), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, N1, N1, SCUA8, 18), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, N1, N1, SCUA8, 18), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, P5, P5, SCUA8, 19), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, P5, P5, SCUA8, 19), /* * Debounce settings for GPIOs D and E passthrough mode are in @@ -2531,14 +2531,14 @@ static const struct aspeed_pin_config aspeed_g4_configs[] = { * controller. Due to this tangle between GPIO and pinctrl we don't yet * fully support pass-through debounce. */ - { PIN_CONFIG_INPUT_DEBOUNCE, { A18, D16 }, SCUA8, 20 }, - { PIN_CONFIG_INPUT_DEBOUNCE, { B17, A17 }, SCUA8, 21 }, - { PIN_CONFIG_INPUT_DEBOUNCE, { C16, B16 }, SCUA8, 22 }, - { PIN_CONFIG_INPUT_DEBOUNCE, { A16, E15 }, SCUA8, 23 }, - { PIN_CONFIG_INPUT_DEBOUNCE, { D15, C15 }, SCUA8, 24 }, - { PIN_CONFIG_INPUT_DEBOUNCE, { B15, A15 }, SCUA8, 25 }, - { PIN_CONFIG_INPUT_DEBOUNCE, { E14, D14 }, SCUA8, 26 }, - { PIN_CONFIG_INPUT_DEBOUNCE, { C14, B14 }, SCUA8, 27 }, + ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, A18, D16, SCUA8, 20), + ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, B17, A17, SCUA8, 21), + ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, C16, B16, SCUA8, 22), + ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, A16, E15, SCUA8, 23), + ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, D15, C15, SCUA8, 24), + ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, B15, A15, SCUA8, 25), + ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, E14, D14, SCUA8, 26), + ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, C14, B14, SCUA8, 27), }; static int aspeed_g4_sig_expr_set(struct aspeed_pinmux_data *ctx, diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c index d8a804b9f958..b2fe47b98fa0 100644 --- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c @@ -2476,124 +2476,124 @@ static const struct aspeed_pin_function aspeed_g5_functions[] = { static struct aspeed_pin_config aspeed_g5_configs[] = { /* GPIOA, GPIOQ */ - { PIN_CONFIG_BIAS_PULL_DOWN, { B14, B13 }, SCU8C, 16 }, - { PIN_CONFIG_BIAS_DISABLE, { B14, B13 }, SCU8C, 16 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { A11, N20 }, SCU8C, 16 }, - { PIN_CONFIG_BIAS_DISABLE, { A11, N20 }, SCU8C, 16 }, + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, B14, B13, SCU8C, 16), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, B14, B13, SCU8C, 16), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, A11, N20, SCU8C, 16), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, A11, N20, SCU8C, 16), /* GPIOB, GPIOR */ - { PIN_CONFIG_BIAS_PULL_DOWN, { K19, H20 }, SCU8C, 17 }, - { PIN_CONFIG_BIAS_DISABLE, { K19, H20 }, SCU8C, 17 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { AA19, E10 }, SCU8C, 17 }, - { PIN_CONFIG_BIAS_DISABLE, { AA19, E10 }, SCU8C, 17 }, + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, K19, H20, SCU8C, 17), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, K19, H20, SCU8C, 17), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, AA19, E10, SCU8C, 17), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, AA19, E10, SCU8C, 17), /* GPIOC, GPIOS*/ - { PIN_CONFIG_BIAS_PULL_DOWN, { C12, B11 }, SCU8C, 18 }, - { PIN_CONFIG_BIAS_DISABLE, { C12, B11 }, SCU8C, 18 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { V20, AA20 }, SCU8C, 18 }, - { PIN_CONFIG_BIAS_DISABLE, { V20, AA20 }, SCU8C, 18 }, + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, C12, B11, SCU8C, 18), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, C12, B11, SCU8C, 18), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, V20, AA20, SCU8C, 18), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, V20, AA20, SCU8C, 18), /* GPIOD, GPIOY */ - { PIN_CONFIG_BIAS_PULL_DOWN, { F19, C21 }, SCU8C, 19 }, - { PIN_CONFIG_BIAS_DISABLE, { F19, C21 }, SCU8C, 19 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { R22, P20 }, SCU8C, 19 }, - { PIN_CONFIG_BIAS_DISABLE, { R22, P20 }, SCU8C, 19 }, + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, F19, C21, SCU8C, 19), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, F19, C21, SCU8C, 19), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, R22, P20, SCU8C, 19), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, R22, P20, SCU8C, 19), /* GPIOE, GPIOZ */ - { PIN_CONFIG_BIAS_PULL_DOWN, { B20, B19 }, SCU8C, 20 }, - { PIN_CONFIG_BIAS_DISABLE, { B20, B19 }, SCU8C, 20 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { Y20, W21 }, SCU8C, 20 }, - { PIN_CONFIG_BIAS_DISABLE, { Y20, W21 }, SCU8C, 20 }, + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, B20, B19, SCU8C, 20), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, B20, B19, SCU8C, 20), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, Y20, W21, SCU8C, 20), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, Y20, W21, SCU8C, 20), /* GPIOF, GPIOAA */ - { PIN_CONFIG_BIAS_PULL_DOWN, { J19, H18 }, SCU8C, 21 }, - { PIN_CONFIG_BIAS_DISABLE, { J19, H18 }, SCU8C, 21 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { Y21, P19 }, SCU8C, 21 }, - { PIN_CONFIG_BIAS_DISABLE, { Y21, P19 }, SCU8C, 21 }, + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, J19, H18, SCU8C, 21), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, J19, H18, SCU8C, 21), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, Y21, P19, SCU8C, 21), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, Y21, P19, SCU8C, 21), - /* GPIOG, GPIOAB */ - { PIN_CONFIG_BIAS_PULL_DOWN, { A19, E14 }, SCU8C, 22 }, - { PIN_CONFIG_BIAS_DISABLE, { A19, E14 }, SCU8C, 22 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { N19, R20 }, SCU8C, 22 }, - { PIN_CONFIG_BIAS_DISABLE, { N19, R20 }, SCU8C, 22 }, + /* GPIOG, GPIOAB */ + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, A19, E14, SCU8C, 22), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, A19, E14, SCU8C, 22), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, N19, R20, SCU8C, 22), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, N19, R20, SCU8C, 22), /* GPIOH, GPIOAC */ - { PIN_CONFIG_BIAS_PULL_DOWN, { A18, D18 }, SCU8C, 23 }, - { PIN_CONFIG_BIAS_DISABLE, { A18, D18 }, SCU8C, 23 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { G21, G22 }, SCU8C, 23 }, - { PIN_CONFIG_BIAS_DISABLE, { G21, G22 }, SCU8C, 23 }, + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, A18, D18, SCU8C, 23), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, A18, D18, SCU8C, 23), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, G21, G22, SCU8C, 23), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, G21, G22, SCU8C, 23), /* GPIOs [I, P] */ - { PIN_CONFIG_BIAS_PULL_DOWN, { C18, A15 }, SCU8C, 24 }, - { PIN_CONFIG_BIAS_DISABLE, { C18, A15 }, SCU8C, 24 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { R2, T3 }, SCU8C, 25 }, - { PIN_CONFIG_BIAS_DISABLE, { R2, T3 }, SCU8C, 25 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { L3, R1 }, SCU8C, 26 }, - { PIN_CONFIG_BIAS_DISABLE, { L3, R1 }, SCU8C, 26 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { T2, W1 }, SCU8C, 27 }, - { PIN_CONFIG_BIAS_DISABLE, { T2, W1 }, SCU8C, 27 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { Y1, T5 }, SCU8C, 28 }, - { PIN_CONFIG_BIAS_DISABLE, { Y1, T5 }, SCU8C, 28 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { V2, T4 }, SCU8C, 29 }, - { PIN_CONFIG_BIAS_DISABLE, { V2, T4 }, SCU8C, 29 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { U5, W4 }, SCU8C, 30 }, - { PIN_CONFIG_BIAS_DISABLE, { U5, W4 }, SCU8C, 30 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { V4, V6 }, SCU8C, 31 }, - { PIN_CONFIG_BIAS_DISABLE, { V4, V6 }, SCU8C, 31 }, + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, C18, A15, SCU8C, 24), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, C18, A15, SCU8C, 24), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, R2, T3, SCU8C, 25), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, R2, T3, SCU8C, 25), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, L3, R1, SCU8C, 26), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, L3, R1, SCU8C, 26), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, T2, W1, SCU8C, 27), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, T2, W1, SCU8C, 27), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, Y1, T5, SCU8C, 28), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, Y1, T5, SCU8C, 28), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, V2, T4, SCU8C, 29), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, V2, T4, SCU8C, 29), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, U5, W4, SCU8C, 30), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, U5, W4, SCU8C, 30), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, V4, V6, SCU8C, 31), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, V4, V6, SCU8C, 31), /* GPIOs T[0-5] (RGMII1 Tx pins) */ - { PIN_CONFIG_DRIVE_STRENGTH, { B5, B5 }, SCU90, 8 }, - { PIN_CONFIG_DRIVE_STRENGTH, { E9, A5 }, SCU90, 9 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { B5, D7 }, SCU90, 12 }, - { PIN_CONFIG_BIAS_DISABLE, { B5, D7 }, SCU90, 12 }, + ASPEED_SB_PINCONF(PIN_CONFIG_DRIVE_STRENGTH, B5, B5, SCU90, 8), + ASPEED_SB_PINCONF(PIN_CONFIG_DRIVE_STRENGTH, E9, A5, SCU90, 9), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, B5, D7, SCU90, 12), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, B5, D7, SCU90, 12), /* GPIOs T[6-7], U[0-3] (RGMII2 TX pins) */ - { PIN_CONFIG_DRIVE_STRENGTH, { B2, B2 }, SCU90, 10 }, - { PIN_CONFIG_DRIVE_STRENGTH, { B1, B3 }, SCU90, 11 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { B2, D4 }, SCU90, 14 }, - { PIN_CONFIG_BIAS_DISABLE, { B2, D4 }, SCU90, 14 }, + ASPEED_SB_PINCONF(PIN_CONFIG_DRIVE_STRENGTH, B2, B2, SCU90, 10), + ASPEED_SB_PINCONF(PIN_CONFIG_DRIVE_STRENGTH, B1, B3, SCU90, 11), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, B2, D4, SCU90, 14), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, B2, D4, SCU90, 14), /* GPIOs U[4-7], V[0-1] (RGMII1 Rx pins) */ - { PIN_CONFIG_BIAS_PULL_DOWN, { B4, C4 }, SCU90, 13 }, - { PIN_CONFIG_BIAS_DISABLE, { B4, C4 }, SCU90, 13 }, + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, B4, C4, SCU90, 13), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, B4, C4, SCU90, 13), /* GPIOs V[2-7] (RGMII2 Rx pins) */ - { PIN_CONFIG_BIAS_PULL_DOWN, { C2, E6 }, SCU90, 15 }, - { PIN_CONFIG_BIAS_DISABLE, { C2, E6 }, SCU90, 15 }, + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, C2, E6, SCU90, 15), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, C2, E6, SCU90, 15), /* ADC pull-downs (SCUA8[19:4]) */ - { PIN_CONFIG_BIAS_PULL_DOWN, { F4, F4 }, SCUA8, 4 }, - { PIN_CONFIG_BIAS_DISABLE, { F4, F4 }, SCUA8, 4 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { F5, F5 }, SCUA8, 5 }, - { PIN_CONFIG_BIAS_DISABLE, { F5, F5 }, SCUA8, 5 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { E2, E2 }, SCUA8, 6 }, - { PIN_CONFIG_BIAS_DISABLE, { E2, E2 }, SCUA8, 6 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { E1, E1 }, SCUA8, 7 }, - { PIN_CONFIG_BIAS_DISABLE, { E1, E1 }, SCUA8, 7 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { F3, F3 }, SCUA8, 8 }, - { PIN_CONFIG_BIAS_DISABLE, { F3, F3 }, SCUA8, 8 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { E3, E3 }, SCUA8, 9 }, - { PIN_CONFIG_BIAS_DISABLE, { E3, E3 }, SCUA8, 9 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { G5, G5 }, SCUA8, 10 }, - { PIN_CONFIG_BIAS_DISABLE, { G5, G5 }, SCUA8, 10 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { G4, G4 }, SCUA8, 11 }, - { PIN_CONFIG_BIAS_DISABLE, { G4, G4 }, SCUA8, 11 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { F2, F2 }, SCUA8, 12 }, - { PIN_CONFIG_BIAS_DISABLE, { F2, F2 }, SCUA8, 12 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { G3, G3 }, SCUA8, 13 }, - { PIN_CONFIG_BIAS_DISABLE, { G3, G3 }, SCUA8, 13 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { G2, G2 }, SCUA8, 14 }, - { PIN_CONFIG_BIAS_DISABLE, { G2, G2 }, SCUA8, 14 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { F1, F1 }, SCUA8, 15 }, - { PIN_CONFIG_BIAS_DISABLE, { F1, F1 }, SCUA8, 15 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { H5, H5 }, SCUA8, 16 }, - { PIN_CONFIG_BIAS_DISABLE, { H5, H5 }, SCUA8, 16 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { G1, G1 }, SCUA8, 17 }, - { PIN_CONFIG_BIAS_DISABLE, { G1, G1 }, SCUA8, 17 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { H3, H3 }, SCUA8, 18 }, - { PIN_CONFIG_BIAS_DISABLE, { H3, H3 }, SCUA8, 18 }, - { PIN_CONFIG_BIAS_PULL_DOWN, { H4, H4 }, SCUA8, 19 }, - { PIN_CONFIG_BIAS_DISABLE, { H4, H4 }, SCUA8, 19 }, + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, F4, F4, SCUA8, 4), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, F4, F4, SCUA8, 4), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, F5, F5, SCUA8, 5), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, F5, F5, SCUA8, 5), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, E2, E2, SCUA8, 6), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, E2, E2, SCUA8, 6), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, E1, E1, SCUA8, 7), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, E1, E1, SCUA8, 7), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, F3, F3, SCUA8, 8), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, F3, F3, SCUA8, 8), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, E3, E3, SCUA8, 9), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, E3, E3, SCUA8, 9), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, G5, G5, SCUA8, 10), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, G5, G5, SCUA8, 10), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, G4, G4, SCUA8, 11), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, G4, G4, SCUA8, 11), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, F2, F2, SCUA8, 12), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, F2, F2, SCUA8, 12), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, G3, G3, SCUA8, 13), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, G3, G3, SCUA8, 13), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, G2, G2, SCUA8, 14), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, G2, G2, SCUA8, 14), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, F1, F1, SCUA8, 15), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, F1, F1, SCUA8, 15), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, H5, H5, SCUA8, 16), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, H5, H5, SCUA8, 16), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, G1, G1, SCUA8, 17), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, G1, G1, SCUA8, 17), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, H3, H3, SCUA8, 18), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, H3, H3, SCUA8, 18), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, H4, H4, SCUA8, 19), + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, H4, H4, SCUA8, 19), /* * Debounce settings for GPIOs D and E passthrough mode are in @@ -2604,14 +2604,14 @@ static struct aspeed_pin_config aspeed_g5_configs[] = { * controller. Due to this tangle between GPIO and pinctrl we don't yet * fully support pass-through debounce. */ - { PIN_CONFIG_INPUT_DEBOUNCE, { F19, E21 }, SCUA8, 20 }, - { PIN_CONFIG_INPUT_DEBOUNCE, { F20, D20 }, SCUA8, 21 }, - { PIN_CONFIG_INPUT_DEBOUNCE, { D21, E20 }, SCUA8, 22 }, - { PIN_CONFIG_INPUT_DEBOUNCE, { G18, C21 }, SCUA8, 23 }, - { PIN_CONFIG_INPUT_DEBOUNCE, { B20, C20 }, SCUA8, 24 }, - { PIN_CONFIG_INPUT_DEBOUNCE, { F18, F17 }, SCUA8, 25 }, - { PIN_CONFIG_INPUT_DEBOUNCE, { E18, D19 }, SCUA8, 26 }, - { PIN_CONFIG_INPUT_DEBOUNCE, { A20, B19 }, SCUA8, 27 }, + ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, F19, E21, SCUA8, 20), + ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, F20, D20, SCUA8, 21), + ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, D21, E20, SCUA8, 22), + ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, G18, C21, SCUA8, 23), + ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, B20, C20, SCUA8, 24), + ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, F18, F17, SCUA8, 25), + ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, E18, D19, SCUA8, 26), + ASPEED_SB_PINCONF(PIN_CONFIG_INPUT_DEBOUNCE, A20, B19, SCUA8, 27), }; static struct regmap *aspeed_g5_acquire_regmap(struct aspeed_pinmux_data *ctx, diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed.h b/drivers/pinctrl/aspeed/pinctrl-aspeed.h index a5d83986f32e..a7db31202033 100644 --- a/drivers/pinctrl/aspeed/pinctrl-aspeed.h +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed.h @@ -35,6 +35,13 @@ struct aspeed_pin_config { .drv_data = (void *) &(PIN_SYM(name_)) \ } +#define ASPEED_SB_PINCONF(param_, pin0_, pin1_, reg_, bit_) { \ + .param = param_, \ + .pins = {pin0_, pin1_}, \ + .reg = reg_, \ + .bit = bit_ \ +} + struct aspeed_pinctrl_data { struct regmap *scu; From patchwork Thu Sep 26 13:36:02 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Jeffery X-Patchwork-Id: 1167930 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 46fGbz05wQz9sN1 for ; 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Thu, 26 Sep 2019 09:35:34 -0400 (EDT) From: Andrew Jeffery To: joel@jms.id.au Subject: [PATCH linux dev-5.3 09/15] pinctrl: aspeed: Move aspeed_pin_config_map to separate source file Date: Thu, 26 Sep 2019 23:06:02 +0930 Message-Id: <20190926133608.30566-10-andrew@aj.id.au> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190926133608.30566-1-andrew@aj.id.au> References: <20190926133608.30566-1-andrew@aj.id.au> MIME-Version: 1.0 X-BeenThere: openbmc@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development list for OpenBMC List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrew Jeffery , johnny_huang@aspeedtech.com, openbmc@lists.ozlabs.org Errors-To: openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "openbmc" From: Johnny Huang The AST2600 pinconf differs from the 2400 and 2500, aspeed_pin_config_map should define separately, and add @confmaps and @nconfmaps to aspeed_pinctrl_data structure for that change. Signed-off-by: Johnny Huang Signed-off-by: Andrew Jeffery --- drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c | 10 ++++++ drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c | 10 ++++++ drivers/pinctrl/aspeed/pinctrl-aspeed.c | 38 +++------------------- drivers/pinctrl/aspeed/pinctrl-aspeed.h | 19 +++++++++++ 4 files changed, 44 insertions(+), 33 deletions(-) diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c index c56ded0ac57e..62b8aa53b627 100644 --- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c @@ -2594,6 +2594,14 @@ static int aspeed_g4_sig_expr_set(struct aspeed_pinmux_data *ctx, return 0; } +static const struct aspeed_pin_config_map aspeed_g4_pin_config_map[] = { + { PIN_CONFIG_BIAS_PULL_DOWN, 0, 1}, + { PIN_CONFIG_BIAS_PULL_DOWN, -1, 0}, + { PIN_CONFIG_BIAS_DISABLE, -1, 1}, + { PIN_CONFIG_DRIVE_STRENGTH, 8, 0}, + { PIN_CONFIG_DRIVE_STRENGTH, 16, 1}, +}; + static const struct aspeed_pinmux_ops aspeed_g4_ops = { .set = aspeed_g4_sig_expr_set, }; @@ -2610,6 +2618,8 @@ static struct aspeed_pinctrl_data aspeed_g4_pinctrl_data = { }, .configs = aspeed_g4_configs, .nconfigs = ARRAY_SIZE(aspeed_g4_configs), + .confmaps = aspeed_g4_pin_config_map, + .nconfmaps = ARRAY_SIZE(aspeed_g4_pin_config_map), }; static const struct pinmux_ops aspeed_g4_pinmux_ops = { diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c index b2fe47b98fa0..2acbcf3d508a 100644 --- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c @@ -2780,6 +2780,14 @@ static int aspeed_g5_sig_expr_set(struct aspeed_pinmux_data *ctx, return 0; } +static const struct aspeed_pin_config_map aspeed_g5_pin_config_map[] = { + { PIN_CONFIG_BIAS_PULL_DOWN, 0, 1}, + { PIN_CONFIG_BIAS_PULL_DOWN, -1, 0}, + { PIN_CONFIG_BIAS_DISABLE, -1, 1}, + { PIN_CONFIG_DRIVE_STRENGTH, 8, 0}, + { PIN_CONFIG_DRIVE_STRENGTH, 16, 1}, +}; + static const struct aspeed_pinmux_ops aspeed_g5_ops = { .eval = aspeed_g5_sig_expr_eval, .set = aspeed_g5_sig_expr_set, @@ -2797,6 +2805,8 @@ static struct aspeed_pinctrl_data aspeed_g5_pinctrl_data = { }, .configs = aspeed_g5_configs, .nconfigs = ARRAY_SIZE(aspeed_g5_configs), + .confmaps = aspeed_g5_pin_config_map, + .nconfmaps = ARRAY_SIZE(aspeed_g5_pin_config_map), }; static const struct pinmux_ops aspeed_g5_pinmux_ops = { diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed.c b/drivers/pinctrl/aspeed/pinctrl-aspeed.c index 54933665b5f8..fc68aca7b36c 100644 --- a/drivers/pinctrl/aspeed/pinctrl-aspeed.c +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed.c @@ -411,49 +411,21 @@ static inline const struct aspeed_pin_config *find_pinconf_config( return NULL; } -/* - * Aspeed pin configuration description. - * - * @param: pinconf configuration parameter - * @arg: The supported argument for @param, or -1 if any value is supported - * @val: The register value to write to configure @arg for @param - * - * The map is to be used in conjunction with the configuration array supplied - * by the driver implementation. - */ -struct aspeed_pin_config_map { - enum pin_config_param param; - s32 arg; - u32 val; -}; - enum aspeed_pin_config_map_type { MAP_TYPE_ARG, MAP_TYPE_VAL }; -/* Aspeed consistently both: - * - * 1. Defines "disable bits" for internal pull-downs - * 2. Uses 8mA or 16mA drive strengths - */ -static const struct aspeed_pin_config_map pin_config_map[] = { - { PIN_CONFIG_BIAS_PULL_DOWN, 0, 1 }, - { PIN_CONFIG_BIAS_PULL_DOWN, -1, 0 }, - { PIN_CONFIG_BIAS_DISABLE, -1, 1 }, - { PIN_CONFIG_DRIVE_STRENGTH, 8, 0 }, - { PIN_CONFIG_DRIVE_STRENGTH, 16, 1 }, -}; - static const struct aspeed_pin_config_map *find_pinconf_map( + const struct aspeed_pinctrl_data *pdata, enum pin_config_param param, enum aspeed_pin_config_map_type type, s64 value) { int i; - for (i = 0; i < ARRAY_SIZE(pin_config_map); i++) { + for (i = 0; i < pdata->nconfmaps; i++) { const struct aspeed_pin_config_map *elem; bool match; - elem = &pin_config_map[i]; + elem = &pdata->confmaps[i]; switch (type) { case MAP_TYPE_ARG: @@ -491,7 +463,7 @@ int aspeed_pin_config_get(struct pinctrl_dev *pctldev, unsigned int offset, if (rc < 0) return rc; - pmap = find_pinconf_map(param, MAP_TYPE_VAL, + pmap = find_pinconf_map(pdata, param, MAP_TYPE_VAL, (val & BIT(pconf->bit)) >> pconf->bit); if (!pmap) @@ -535,7 +507,7 @@ int aspeed_pin_config_set(struct pinctrl_dev *pctldev, unsigned int offset, if (!pconf) return -ENOTSUPP; - pmap = find_pinconf_map(param, MAP_TYPE_ARG, arg); + pmap = find_pinconf_map(pdata, param, MAP_TYPE_ARG, arg); if (WARN_ON(!pmap)) return -EINVAL; diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed.h b/drivers/pinctrl/aspeed/pinctrl-aspeed.h index a7db31202033..27d3929b6aca 100644 --- a/drivers/pinctrl/aspeed/pinctrl-aspeed.h +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed.h @@ -42,6 +42,22 @@ struct aspeed_pin_config { .bit = bit_ \ } +/* + * Aspeed pin configuration description. + * + * @param: pinconf configuration parameter + * @arg: The supported argument for @param, or -1 if any value is supported + * @val: The register value to write to configure @arg for @param + * + * The map is to be used in conjunction with the configuration array supplied + * by the driver implementation. + */ +struct aspeed_pin_config_map { + enum pin_config_param param; + s32 arg; + u32 val; +}; + struct aspeed_pinctrl_data { struct regmap *scu; @@ -52,6 +68,9 @@ struct aspeed_pinctrl_data { const unsigned int nconfigs; struct aspeed_pinmux_data pinmux; + + const struct aspeed_pin_config_map *confmaps; + const unsigned int nconfmaps; }; /* Aspeed pinctrl helpers */ From patchwork Thu Sep 26 13:36:03 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Jeffery X-Patchwork-Id: 1167931 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 46fGdL0cS0z9sN1 for ; Thu, 26 Sep 2019 23:54:46 +1000 (AEST) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=aj.id.au Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=aj.id.au header.i=@aj.id.au header.b="FGKqwAgk"; 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Thu, 26 Sep 2019 09:35:36 -0400 (EDT) From: Andrew Jeffery To: joel@jms.id.au Subject: [PATCH linux dev-5.3 10/15] pinctrl: aspeed: Use masks to describe pinconf bitfields Date: Thu, 26 Sep 2019 23:06:03 +0930 Message-Id: <20190926133608.30566-11-andrew@aj.id.au> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190926133608.30566-1-andrew@aj.id.au> References: <20190926133608.30566-1-andrew@aj.id.au> MIME-Version: 1.0 X-BeenThere: openbmc@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development list for OpenBMC List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrew Jeffery , johnny_huang@aspeedtech.com, openbmc@lists.ozlabs.org Errors-To: openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "openbmc" From: Johnny Huang Since some of the AST2600 pinconf setting are not just single bit, modified aspeed_pin_config @bit to @mask and add @mask to aspeed_pin_config_map to support configuring multiple bits. Signed-off-by: Johnny Huang [AJ: Tweak commit message] Signed-off-by: Andrew Jeffery --- drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c | 10 +++++----- drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c | 10 +++++----- drivers/pinctrl/aspeed/pinctrl-aspeed.c | 12 ++++++------ drivers/pinctrl/aspeed/pinctrl-aspeed.h | 7 ++++--- 4 files changed, 20 insertions(+), 19 deletions(-) diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c index 62b8aa53b627..bfed0e274643 100644 --- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g4.c @@ -2595,11 +2595,11 @@ static int aspeed_g4_sig_expr_set(struct aspeed_pinmux_data *ctx, } static const struct aspeed_pin_config_map aspeed_g4_pin_config_map[] = { - { PIN_CONFIG_BIAS_PULL_DOWN, 0, 1}, - { PIN_CONFIG_BIAS_PULL_DOWN, -1, 0}, - { PIN_CONFIG_BIAS_DISABLE, -1, 1}, - { PIN_CONFIG_DRIVE_STRENGTH, 8, 0}, - { PIN_CONFIG_DRIVE_STRENGTH, 16, 1}, + { PIN_CONFIG_BIAS_PULL_DOWN, 0, 1, BIT_MASK(0)}, + { PIN_CONFIG_BIAS_PULL_DOWN, -1, 0, BIT_MASK(0)}, + { PIN_CONFIG_BIAS_DISABLE, -1, 1, BIT_MASK(0)}, + { PIN_CONFIG_DRIVE_STRENGTH, 8, 0, BIT_MASK(0)}, + { PIN_CONFIG_DRIVE_STRENGTH, 16, 1, BIT_MASK(0)}, }; static const struct aspeed_pinmux_ops aspeed_g4_ops = { diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c index 2acbcf3d508a..0cab4c2576e2 100644 --- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g5.c @@ -2781,11 +2781,11 @@ static int aspeed_g5_sig_expr_set(struct aspeed_pinmux_data *ctx, } static const struct aspeed_pin_config_map aspeed_g5_pin_config_map[] = { - { PIN_CONFIG_BIAS_PULL_DOWN, 0, 1}, - { PIN_CONFIG_BIAS_PULL_DOWN, -1, 0}, - { PIN_CONFIG_BIAS_DISABLE, -1, 1}, - { PIN_CONFIG_DRIVE_STRENGTH, 8, 0}, - { PIN_CONFIG_DRIVE_STRENGTH, 16, 1}, + { PIN_CONFIG_BIAS_PULL_DOWN, 0, 1, BIT_MASK(0)}, + { PIN_CONFIG_BIAS_PULL_DOWN, -1, 0, BIT_MASK(0)}, + { PIN_CONFIG_BIAS_DISABLE, -1, 1, BIT_MASK(0)}, + { PIN_CONFIG_DRIVE_STRENGTH, 8, 0, BIT_MASK(0)}, + { PIN_CONFIG_DRIVE_STRENGTH, 16, 1, BIT_MASK(0)}, }; static const struct aspeed_pinmux_ops aspeed_g5_ops = { diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed.c b/drivers/pinctrl/aspeed/pinctrl-aspeed.c index fc68aca7b36c..b625a657171e 100644 --- a/drivers/pinctrl/aspeed/pinctrl-aspeed.c +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed.c @@ -464,7 +464,7 @@ int aspeed_pin_config_get(struct pinctrl_dev *pctldev, unsigned int offset, return rc; pmap = find_pinconf_map(pdata, param, MAP_TYPE_VAL, - (val & BIT(pconf->bit)) >> pconf->bit); + (val & pconf->mask) >> __ffs(pconf->mask)); if (!pmap) return -EINVAL; @@ -512,17 +512,17 @@ int aspeed_pin_config_set(struct pinctrl_dev *pctldev, unsigned int offset, if (WARN_ON(!pmap)) return -EINVAL; - val = pmap->val << pconf->bit; + val = pmap->val << __ffs(pconf->mask); rc = regmap_update_bits(pdata->scu, pconf->reg, - BIT(pconf->bit), val); + pmap->mask, val); if (rc < 0) return rc; - pr_debug("%s: Set SCU%02X[%d]=%d for param %d(=%d) on pin %d\n", - __func__, pconf->reg, pconf->bit, pmap->val, - param, arg, offset); + pr_debug("%s: Set SCU%02X[%lu]=%d for param %d(=%d) on pin %d\n", + __func__, pconf->reg, __ffs(pconf->mask), + pmap->val, param, arg, offset); } return 0; diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed.h b/drivers/pinctrl/aspeed/pinctrl-aspeed.h index 27d3929b6aca..6f0f03395617 100644 --- a/drivers/pinctrl/aspeed/pinctrl-aspeed.h +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed.h @@ -24,8 +24,7 @@ struct aspeed_pin_config { enum pin_config_param param; unsigned int pins[2]; unsigned int reg; - u8 bit; - u8 value; + u32 mask; }; #define ASPEED_PINCTRL_PIN(name_) \ @@ -39,7 +38,7 @@ struct aspeed_pin_config { .param = param_, \ .pins = {pin0_, pin1_}, \ .reg = reg_, \ - .bit = bit_ \ + .mask = BIT_MASK(bit_) \ } /* @@ -48,6 +47,7 @@ struct aspeed_pin_config { * @param: pinconf configuration parameter * @arg: The supported argument for @param, or -1 if any value is supported * @val: The register value to write to configure @arg for @param + * @mask: The bitfield mask for @val * * The map is to be used in conjunction with the configuration array supplied * by the driver implementation. @@ -56,6 +56,7 @@ struct aspeed_pin_config_map { enum pin_config_param param; s32 arg; u32 val; + u32 mask; }; struct aspeed_pinctrl_data { From patchwork Thu Sep 26 13:36:04 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Jeffery X-Patchwork-Id: 1167932 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 46fGgL5tQCz9sNf for ; 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Thu, 26 Sep 2019 09:35:39 -0400 (EDT) From: Andrew Jeffery To: joel@jms.id.au Subject: [PATCH linux dev-5.3 11/15] pinctrl: aspeed-g6: Add AST2600 pinconf support Date: Thu, 26 Sep 2019 23:06:04 +0930 Message-Id: <20190926133608.30566-12-andrew@aj.id.au> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190926133608.30566-1-andrew@aj.id.au> References: <20190926133608.30566-1-andrew@aj.id.au> MIME-Version: 1.0 X-BeenThere: openbmc@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development list for OpenBMC List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrew Jeffery , johnny_huang@aspeedtech.com, openbmc@lists.ozlabs.org Errors-To: openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "openbmc" From: Johnny Huang The AST2600 pinconf is a little different from previous generations of ASPEED BMC SoCs in terms of architecture. The pull-down setting is per-pin setting now, and drive-strength support 4 kind of value (e.g. 4ma, 8ma, 12ma, 16ma). Signed-off-by: Johnny Huang [AJ: Trim unused pinctrl register macros] Signed-off-by: Andrew Jeffery --- drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c | 290 +++++++++++++++++++++ drivers/pinctrl/aspeed/pinctrl-aspeed.h | 7 + 2 files changed, 297 insertions(+) diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c b/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c index 22e6c07149c3..eb0c11a9fbf2 100644 --- a/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed-g6.c @@ -28,6 +28,8 @@ #define SCU438 0x438 /* Multi-function Pin Control #10 */ #define SCU440 0x440 /* USB Multi-function Pin Control #12 */ #define SCU450 0x450 /* Multi-function Pin Control #14 */ +#define SCU454 0x454 /* Multi-function Pin Control #15 */ +#define SCU458 0x458 /* Multi-function Pin Control #16 */ #define SCU4B0 0x4B0 /* Multi-function Pin Control #17 */ #define SCU4B4 0x4B4 /* Multi-function Pin Control #18 */ #define SCU4B8 0x4B8 /* Multi-function Pin Control #19 */ @@ -36,6 +38,13 @@ #define SCU4D8 0x4D8 /* Multi-function Pin Control #23 */ #define SCU500 0x500 /* Hardware Strap 1 */ #define SCU510 0x510 /* Hardware Strap 2 */ +#define SCU610 0x610 /* Disable GPIO Internal Pull-Down #0 */ +#define SCU614 0x614 /* Disable GPIO Internal Pull-Down #1 */ +#define SCU618 0x618 /* Disable GPIO Internal Pull-Down #2 */ +#define SCU61C 0x61c /* Disable GPIO Internal Pull-Down #3 */ +#define SCU620 0x620 /* Disable GPIO Internal Pull-Down #4 */ +#define SCU634 0x634 /* Disable GPIO Internal Pull-Down #5 */ +#define SCU638 0x638 /* Disable GPIO Internal Pull-Down #6 */ #define SCU694 0x694 /* Multi-function Pin Control #25 */ #define SCUC20 0xC20 /* PCIE configuration Setting Control */ @@ -2333,6 +2342,260 @@ static const struct aspeed_pin_function aspeed_g6_functions[] = { ASPEED_PINCTRL_FUNC(WDTRST4), }; +static struct aspeed_pin_config aspeed_g6_configs[] = { + /* GPIOB7 */ + ASPEED_PULL_DOWN_PINCONF(J24, SCU610, 15), + /* GPIOB6 */ + ASPEED_PULL_DOWN_PINCONF(H25, SCU610, 14), + /* GPIOB5 */ + ASPEED_PULL_DOWN_PINCONF(G26, SCU610, 13), + /* GPIOB4 */ + ASPEED_PULL_DOWN_PINCONF(J23, SCU610, 12), + /* GPIOB3 */ + ASPEED_PULL_DOWN_PINCONF(J25, SCU610, 11), + /* GPIOB2 */ + ASPEED_PULL_DOWN_PINCONF(H26, SCU610, 10), + /* GPIOB1 */ + ASPEED_PULL_DOWN_PINCONF(K23, SCU610, 9), + /* GPIOB0 */ + ASPEED_PULL_DOWN_PINCONF(J26, SCU610, 8), + + /* GPIOH3 */ + ASPEED_PULL_DOWN_PINCONF(A17, SCU614, 27), + /* GPIOH2 */ + ASPEED_PULL_DOWN_PINCONF(C18, SCU614, 26), + /* GPIOH1 */ + ASPEED_PULL_DOWN_PINCONF(B18, SCU614, 25), + /* GPIOH0 */ + ASPEED_PULL_DOWN_PINCONF(A18, SCU614, 24), + + /* GPIOL7 */ + ASPEED_PULL_DOWN_PINCONF(C14, SCU618, 31), + /* GPIOL6 */ + ASPEED_PULL_DOWN_PINCONF(B14, SCU618, 30), + /* GPIOL5 */ + ASPEED_PULL_DOWN_PINCONF(F15, SCU618, 29), + /* GPIOL4 */ + ASPEED_PULL_DOWN_PINCONF(C15, SCU618, 28), + + /* GPIOJ7 */ + ASPEED_PULL_UP_PINCONF(D19, SCU618, 15), + /* GPIOJ6 */ + ASPEED_PULL_UP_PINCONF(C20, SCU618, 14), + /* GPIOJ5 */ + ASPEED_PULL_UP_PINCONF(A19, SCU618, 13), + /* GPIOJ4 */ + ASPEED_PULL_UP_PINCONF(C19, SCU618, 12), + /* GPIOJ3 */ + ASPEED_PULL_UP_PINCONF(D20, SCU618, 11), + /* GPIOJ2 */ + ASPEED_PULL_UP_PINCONF(E19, SCU618, 10), + /* GPIOJ1 */ + ASPEED_PULL_UP_PINCONF(A20, SCU618, 9), + /* GPIOJ0 */ + ASPEED_PULL_UP_PINCONF(B20, SCU618, 8), + + /* GPIOI7 */ + ASPEED_PULL_DOWN_PINCONF(A15, SCU618, 7), + /* GPIOI6 */ + ASPEED_PULL_DOWN_PINCONF(B16, SCU618, 6), + /* GPIOI5 */ + ASPEED_PULL_DOWN_PINCONF(E16, SCU618, 5), + /* GPIOI4 */ + ASPEED_PULL_DOWN_PINCONF(C16, SCU618, 4), + /* GPIOI3 */ + ASPEED_PULL_DOWN_PINCONF(D16, SCU618, 3), + /* GPIOI2 */ + ASPEED_PULL_DOWN_PINCONF(E17, SCU618, 2), + /* GPIOI1 */ + ASPEED_PULL_DOWN_PINCONF(A16, SCU618, 1), + /* GPIOI0 */ + ASPEED_PULL_DOWN_PINCONF(D17, SCU618, 0), + + /* GPIOP7 */ + ASPEED_PULL_DOWN_PINCONF(Y23, SCU61C, 31), + /* GPIOP6 */ + ASPEED_PULL_DOWN_PINCONF(AB24, SCU61C, 30), + /* GPIOP5 */ + ASPEED_PULL_DOWN_PINCONF(AB23, SCU61C, 29), + /* GPIOP4 */ + ASPEED_PULL_DOWN_PINCONF(W23, SCU61C, 28), + /* GPIOP3 */ + ASPEED_PULL_DOWN_PINCONF(AA24, SCU61C, 27), + /* GPIOP2 */ + ASPEED_PULL_DOWN_PINCONF(AA23, SCU61C, 26), + /* GPIOP1 */ + ASPEED_PULL_DOWN_PINCONF(W24, SCU61C, 25), + /* GPIOP0 */ + ASPEED_PULL_DOWN_PINCONF(AB22, SCU61C, 24), + + /* GPIOO7 */ + ASPEED_PULL_DOWN_PINCONF(AC23, SCU61C, 23), + /* GPIOO6 */ + ASPEED_PULL_DOWN_PINCONF(AC24, SCU61C, 22), + /* GPIOO5 */ + ASPEED_PULL_DOWN_PINCONF(AC22, SCU61C, 21), + /* GPIOO4 */ + ASPEED_PULL_DOWN_PINCONF(AD25, SCU61C, 20), + /* GPIOO3 */ + ASPEED_PULL_DOWN_PINCONF(AD24, SCU61C, 19), + /* GPIOO2 */ + ASPEED_PULL_DOWN_PINCONF(AD23, SCU61C, 18), + /* GPIOO1 */ + ASPEED_PULL_DOWN_PINCONF(AD22, SCU61C, 17), + /* GPIOO0 */ + ASPEED_PULL_DOWN_PINCONF(AD26, SCU61C, 16), + + /* GPION7 */ + ASPEED_PULL_DOWN_PINCONF(M26, SCU61C, 15), + /* GPION6 */ + ASPEED_PULL_DOWN_PINCONF(N26, SCU61C, 14), + /* GPION5 */ + ASPEED_PULL_DOWN_PINCONF(M23, SCU61C, 13), + /* GPION4 */ + ASPEED_PULL_DOWN_PINCONF(P26, SCU61C, 12), + /* GPION3 */ + ASPEED_PULL_DOWN_PINCONF(N24, SCU61C, 11), + /* GPION2 */ + ASPEED_PULL_DOWN_PINCONF(N25, SCU61C, 10), + /* GPION1 */ + ASPEED_PULL_DOWN_PINCONF(N23, SCU61C, 9), + /* GPION0 */ + ASPEED_PULL_DOWN_PINCONF(P25, SCU61C, 8), + + /* GPIOM7 */ + ASPEED_PULL_DOWN_PINCONF(D13, SCU61C, 7), + /* GPIOM6 */ + ASPEED_PULL_DOWN_PINCONF(C13, SCU61C, 6), + /* GPIOM5 */ + ASPEED_PULL_DOWN_PINCONF(C12, SCU61C, 5), + /* GPIOM4 */ + ASPEED_PULL_DOWN_PINCONF(B12, SCU61C, 4), + /* GPIOM3 */ + ASPEED_PULL_DOWN_PINCONF(E14, SCU61C, 3), + /* GPIOM2 */ + ASPEED_PULL_DOWN_PINCONF(A12, SCU61C, 2), + /* GPIOM1 */ + ASPEED_PULL_DOWN_PINCONF(B13, SCU61C, 1), + /* GPIOM0 */ + ASPEED_PULL_DOWN_PINCONF(D14, SCU61C, 0), + + /* GPIOS7 */ + ASPEED_PULL_DOWN_PINCONF(T24, SCU620, 23), + /* GPIOS6 */ + ASPEED_PULL_DOWN_PINCONF(P23, SCU620, 22), + /* GPIOS5 */ + ASPEED_PULL_DOWN_PINCONF(P24, SCU620, 21), + /* GPIOS4 */ + ASPEED_PULL_DOWN_PINCONF(R26, SCU620, 20), + /* GPIOS3*/ + ASPEED_PULL_DOWN_PINCONF(R24, SCU620, 19), + /* GPIOS2 */ + ASPEED_PULL_DOWN_PINCONF(T26, SCU620, 18), + /* GPIOS1 */ + ASPEED_PULL_DOWN_PINCONF(T25, SCU620, 17), + /* GPIOS0 */ + ASPEED_PULL_DOWN_PINCONF(R23, SCU620, 16), + + /* GPIOR7 */ + ASPEED_PULL_DOWN_PINCONF(U26, SCU620, 15), + /* GPIOR6 */ + ASPEED_PULL_DOWN_PINCONF(W26, SCU620, 14), + /* GPIOR5 */ + ASPEED_PULL_DOWN_PINCONF(T23, SCU620, 13), + /* GPIOR4 */ + ASPEED_PULL_DOWN_PINCONF(U25, SCU620, 12), + /* GPIOR3*/ + ASPEED_PULL_DOWN_PINCONF(V26, SCU620, 11), + /* GPIOR2 */ + ASPEED_PULL_DOWN_PINCONF(V24, SCU620, 10), + /* GPIOR1 */ + ASPEED_PULL_DOWN_PINCONF(U24, SCU620, 9), + /* GPIOR0 */ + ASPEED_PULL_DOWN_PINCONF(V25, SCU620, 8), + + /* GPIOX7 */ + ASPEED_PULL_DOWN_PINCONF(AB10, SCU634, 31), + /* GPIOX6 */ + ASPEED_PULL_DOWN_PINCONF(AF9, SCU634, 30), + /* GPIOX5 */ + ASPEED_PULL_DOWN_PINCONF(AD9, SCU634, 29), + /* GPIOX4 */ + ASPEED_PULL_DOWN_PINCONF(AB9, SCU634, 28), + /* GPIOX3*/ + ASPEED_PULL_DOWN_PINCONF(AF8, SCU634, 27), + /* GPIOX2 */ + ASPEED_PULL_DOWN_PINCONF(AC9, SCU634, 26), + /* GPIOX1 */ + ASPEED_PULL_DOWN_PINCONF(AA9, SCU634, 25), + /* GPIOX0 */ + ASPEED_PULL_DOWN_PINCONF(AE8, SCU634, 24), + + /* GPIOV7 */ + ASPEED_PULL_DOWN_PINCONF(AF15, SCU634, 15), + /* GPIOV6 */ + ASPEED_PULL_DOWN_PINCONF(AD15, SCU634, 14), + /* GPIOV5 */ + ASPEED_PULL_DOWN_PINCONF(AE14, SCU634, 13), + /* GPIOV4 */ + ASPEED_PULL_DOWN_PINCONF(AE15, SCU634, 12), + /* GPIOV3*/ + ASPEED_PULL_DOWN_PINCONF(AC15, SCU634, 11), + /* GPIOV2 */ + ASPEED_PULL_DOWN_PINCONF(AD14, SCU634, 10), + /* GPIOV1 */ + ASPEED_PULL_DOWN_PINCONF(AF14, SCU634, 9), + /* GPIOV0 */ + ASPEED_PULL_DOWN_PINCONF(AB15, SCU634, 8), + + /* GPIOZ7 */ + ASPEED_PULL_DOWN_PINCONF(AF10, SCU638, 15), + /* GPIOZ6 */ + ASPEED_PULL_DOWN_PINCONF(AD11, SCU638, 14), + /* GPIOZ5 */ + ASPEED_PULL_DOWN_PINCONF(AA11, SCU638, 13), + /* GPIOZ4 */ + ASPEED_PULL_DOWN_PINCONF(AC11, SCU638, 12), + /* GPIOZ3*/ + ASPEED_PULL_DOWN_PINCONF(AB11, SCU638, 11), + + /* GPIOZ1 */ + ASPEED_PULL_DOWN_PINCONF(AD10, SCU638, 9), + /* GPIOZ0 */ + ASPEED_PULL_DOWN_PINCONF(AC10, SCU638, 8), + + /* GPIOY6 */ + ASPEED_PULL_DOWN_PINCONF(AC12, SCU638, 6), + /* GPIOY5 */ + ASPEED_PULL_DOWN_PINCONF(AF12, SCU638, 5), + /* GPIOY4 */ + ASPEED_PULL_DOWN_PINCONF(AE12, SCU638, 4), + /* GPIOY3 */ + ASPEED_PULL_DOWN_PINCONF(AA12, SCU638, 3), + /* GPIOY2 */ + ASPEED_PULL_DOWN_PINCONF(AE11, SCU638, 2), + /* GPIOY1 */ + ASPEED_PULL_DOWN_PINCONF(AD12, SCU638, 1), + /* GPIOY0 */ + ASPEED_PULL_DOWN_PINCONF(AF11, SCU638, 0), + + /* LAD3 */ + { PIN_CONFIG_DRIVE_STRENGTH, { AC7, AC7 }, SCU454, GENMASK(31, 30)}, + /* LAD2 */ + { PIN_CONFIG_DRIVE_STRENGTH, { AC8, AC8 }, SCU454, GENMASK(29, 28)}, + /* LAD1 */ + { PIN_CONFIG_DRIVE_STRENGTH, { AB8, AB8 }, SCU454, GENMASK(27, 26)}, + /* LAD0 */ + { PIN_CONFIG_DRIVE_STRENGTH, { AB7, AB7 }, SCU454, GENMASK(25, 24)}, + + /* MAC3 */ + { PIN_CONFIG_POWER_SOURCE, { H24, E26 }, SCU458, BIT_MASK(4)}, + { PIN_CONFIG_DRIVE_STRENGTH, { H24, E26 }, SCU458, GENMASK(1, 0)}, + /* MAC4 */ + { PIN_CONFIG_POWER_SOURCE, { F24, B24 }, SCU458, BIT_MASK(5)}, + { PIN_CONFIG_DRIVE_STRENGTH, { F24, B24 }, SCU458, GENMASK(3, 2)}, +}; + /** * Configure a pin's signal by applying an expression's descriptor state for * all descriptors in the expression. @@ -2400,6 +2663,20 @@ static int aspeed_g6_sig_expr_set(struct aspeed_pinmux_data *ctx, return 0; } +static const struct aspeed_pin_config_map aspeed_g6_pin_config_map[] = { + { PIN_CONFIG_BIAS_PULL_DOWN, 0, 1, BIT_MASK(0)}, + { PIN_CONFIG_BIAS_PULL_DOWN, -1, 0, BIT_MASK(0)}, + { PIN_CONFIG_BIAS_PULL_UP, 0, 1, BIT_MASK(0)}, + { PIN_CONFIG_BIAS_PULL_UP, -1, 0, BIT_MASK(0)}, + { PIN_CONFIG_BIAS_DISABLE, -1, 1, BIT_MASK(0)}, + { PIN_CONFIG_DRIVE_STRENGTH, 4, 0, GENMASK(1, 0)}, + { PIN_CONFIG_DRIVE_STRENGTH, 8, 1, GENMASK(1, 0)}, + { PIN_CONFIG_DRIVE_STRENGTH, 12, 2, GENMASK(1, 0)}, + { PIN_CONFIG_DRIVE_STRENGTH, 16, 3, GENMASK(1, 0)}, + { PIN_CONFIG_POWER_SOURCE, 3300, 0, BIT_MASK(0)}, + { PIN_CONFIG_POWER_SOURCE, 1800, 1, BIT_MASK(0)}, +}; + static const struct aspeed_pinmux_ops aspeed_g5_ops = { .set = aspeed_g6_sig_expr_set, }; @@ -2414,6 +2691,10 @@ static struct aspeed_pinctrl_data aspeed_g6_pinctrl_data = { .functions = aspeed_g6_functions, .nfunctions = ARRAY_SIZE(aspeed_g6_functions), }, + .configs = aspeed_g6_configs, + .nconfigs = ARRAY_SIZE(aspeed_g6_configs), + .confmaps = aspeed_g6_pin_config_map, + .nconfmaps = ARRAY_SIZE(aspeed_g6_pin_config_map), }; static const struct pinmux_ops aspeed_g6_pinmux_ops = { @@ -2434,12 +2715,21 @@ static const struct pinctrl_ops aspeed_g6_pinctrl_ops = { .dt_free_map = pinctrl_utils_free_map, }; +static const struct pinconf_ops aspeed_g6_conf_ops = { + .is_generic = true, + .pin_config_get = aspeed_pin_config_get, + .pin_config_set = aspeed_pin_config_set, + .pin_config_group_get = aspeed_pin_config_group_get, + .pin_config_group_set = aspeed_pin_config_group_set, +}; + static struct pinctrl_desc aspeed_g6_pinctrl_desc = { .name = "aspeed-g6-pinctrl", .pins = aspeed_g6_pins, .npins = ARRAY_SIZE(aspeed_g6_pins), .pctlops = &aspeed_g6_pinctrl_ops, .pmxops = &aspeed_g6_pinmux_ops, + .confops = &aspeed_g6_conf_ops, }; static int aspeed_g6_pinctrl_probe(struct platform_device *pdev) diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed.h b/drivers/pinctrl/aspeed/pinctrl-aspeed.h index 6f0f03395617..4dcde3bc29c8 100644 --- a/drivers/pinctrl/aspeed/pinctrl-aspeed.h +++ b/drivers/pinctrl/aspeed/pinctrl-aspeed.h @@ -41,6 +41,13 @@ struct aspeed_pin_config { .mask = BIT_MASK(bit_) \ } +#define ASPEED_PULL_DOWN_PINCONF(pin_, reg_, bit_) \ + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_DOWN, pin_, pin_, reg_, bit_), \ + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, pin_, pin_, reg_, bit_) + +#define ASPEED_PULL_UP_PINCONF(pin_, reg_, bit_) \ + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_PULL_UP, pin_, pin_, reg_, bit_), \ + ASPEED_SB_PINCONF(PIN_CONFIG_BIAS_DISABLE, pin_, pin_, reg_, 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uegrihhlohhuthemuceftddtnecunecujfgurhephffvufffkffojghfggfgsedtkeertd ertddtnecuhfhrohhmpeetnhgurhgvficulfgvfhhfvghrhicuoegrnhgurhgvfiesrghj rdhiugdrrghuqeenucfkphepvddtfedrheejrddvudehrddujeeknecurfgrrhgrmhepmh grihhlfhhrohhmpegrnhgurhgvfiesrghjrdhiugdrrghunecuvehluhhsthgvrhfuihii vgepuddt X-ME-Proxy: Received: from mistburn.lan (203-57-215-178.dyn.iinet.net.au [203.57.215.178]) by mail.messagingengine.com (Postfix) with ESMTPA id 276CDD6005A; Thu, 26 Sep 2019 09:35:41 -0400 (EDT) From: Andrew Jeffery To: joel@jms.id.au Subject: [PATCH linux dev-5.3 12/15] ARM: dts: aspeed-g6: Fix EMMC function in pinctrl dtsi Date: Thu, 26 Sep 2019 23:06:05 +0930 Message-Id: <20190926133608.30566-13-andrew@aj.id.au> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190926133608.30566-1-andrew@aj.id.au> References: <20190926133608.30566-1-andrew@aj.id.au> MIME-Version: 1.0 X-BeenThere: openbmc@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development list for OpenBMC List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrew Jeffery , johnny_huang@aspeedtech.com, openbmc@lists.ozlabs.org Errors-To: openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "openbmc" The binding was updated to better reflect the intended use of the hardware and the existing function/groups for SD3 were dropped. Signed-off-by: Andrew Jeffery --- arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi b/arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi index 5b8bf58e89cb..045ce66ca876 100644 --- a/arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi +++ b/arch/arm/boot/dts/aspeed-g6-pinctrl.dtsi @@ -852,14 +852,9 @@ groups = "SD2"; }; - pinctrl_sd3_default: sd3_default { - function = "SD3"; - groups = "SD3"; - }; - pinctrl_emmc_default: emmc_default { - function = "SD3"; - groups = "EMMC"; + function = "EMMC"; + groups = "EMMCG4"; }; pinctrl_sgpm1_default: sgpm1_default { From patchwork Thu Sep 26 13:36:06 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Jeffery X-Patchwork-Id: 1167934 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [203.11.71.2]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 46fGkj6ggRz9sN1 for ; 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Thu, 26 Sep 2019 09:35:44 -0400 (EDT) From: Andrew Jeffery To: joel@jms.id.au Subject: [PATCH linux dev-5.3 13/15] ARM: dts: aspeed-g6: Add pinctrl properties to MDIO nodes Date: Thu, 26 Sep 2019 23:06:06 +0930 Message-Id: <20190926133608.30566-14-andrew@aj.id.au> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190926133608.30566-1-andrew@aj.id.au> References: <20190926133608.30566-1-andrew@aj.id.au> MIME-Version: 1.0 X-BeenThere: openbmc@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development list for OpenBMC List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrew Jeffery , johnny_huang@aspeedtech.com, openbmc@lists.ozlabs.org Errors-To: openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "openbmc" This way enabling the MDIO controllers automatically requests the right pinmux configuration. Signed-off-by: Andrew Jeffery --- arch/arm/boot/dts/aspeed-g6.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi index ec791b54b81a..6ad1bc094f1c 100644 --- a/arch/arm/boot/dts/aspeed-g6.dtsi +++ b/arch/arm/boot/dts/aspeed-g6.dtsi @@ -165,6 +165,8 @@ #address-cells = <1>; #size-cells = <0>; status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mdio1_default>; }; mdio1: mdio@1e650008 { @@ -173,6 +175,8 @@ #address-cells = <1>; #size-cells = <0>; status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mdio2_default>; }; mdio2: mdio@1e650010 { @@ -181,6 +185,8 @@ #address-cells = <1>; #size-cells = <0>; status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mdio3_default>; }; mdio3: mdio@1e650018 { @@ -189,6 +195,8 @@ #address-cells = <1>; #size-cells = <0>; status = "disabled"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_mdio4_default>; }; mac0: ftgmac@1e660000 { From patchwork Thu Sep 26 13:36:07 2019 Content-Type: text/plain; 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Signed-off-by: Andrew Jeffery --- arch/arm/boot/dts/aspeed-ast2600-evb.dts | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/arch/arm/boot/dts/aspeed-ast2600-evb.dts b/arch/arm/boot/dts/aspeed-ast2600-evb.dts index 0b3d3978c4d3..0392e9162f11 100644 --- a/arch/arm/boot/dts/aspeed-ast2600-evb.dts +++ b/arch/arm/boot/dts/aspeed-ast2600-evb.dts @@ -55,6 +55,9 @@ phy-mode = "rgmii"; phy-handle = <ðphy1>; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii2_default>; }; &mac2 { @@ -62,6 +65,9 @@ phy-mode = "rgmii"; phy-handle = <ðphy2>; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii3_default>; }; &mac3 { @@ -69,6 +75,9 @@ phy-mode = "rgmii"; phy-handle = <ðphy3>; + + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_rgmii4_default>; }; &emmc_controller { From patchwork Thu Sep 26 13:36:08 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrew Jeffery X-Patchwork-Id: 1167936 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.ozlabs.org (lists.ozlabs.org [IPv6:2401:3900:2:1::3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 46fGqP2SWxz9sNx for ; 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Thu, 26 Sep 2019 09:35:48 -0400 (EDT) From: Andrew Jeffery To: joel@jms.id.au Subject: [PATCH linux dev-5.3 15/15] ARM: dts: aspeed-g6: Add missing pinctrl-names property to I2C nodes Date: Thu, 26 Sep 2019 23:06:08 +0930 Message-Id: <20190926133608.30566-16-andrew@aj.id.au> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20190926133608.30566-1-andrew@aj.id.au> References: <20190926133608.30566-1-andrew@aj.id.au> MIME-Version: 1.0 X-BeenThere: openbmc@lists.ozlabs.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Development list for OpenBMC List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrew Jeffery , johnny_huang@aspeedtech.com, openbmc@lists.ozlabs.org Errors-To: openbmc-bounces+incoming=patchwork.ozlabs.org@lists.ozlabs.org Sender: "openbmc" Setting `pinctrl-names = "default";` will make the pinctrl subsystem configure the pinmux prior to probing the driver. Signed-off-by: Andrew Jeffery --- arch/arm/boot/dts/aspeed-g6.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi index 6ad1bc094f1c..5bea04b67b5c 100644 --- a/arch/arm/boot/dts/aspeed-g6.dtsi +++ b/arch/arm/boot/dts/aspeed-g6.dtsi @@ -533,6 +533,7 @@ resets = <&syscon ASPEED_RESET_I2C>; interrupts = ; bus-frequency = <100000>; + pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c2_default>; status = "disabled"; }; @@ -547,6 +548,7 @@ resets = <&syscon ASPEED_RESET_I2C>; interrupts = ; bus-frequency = <100000>; + pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c3_default>; status = "disabled"; }; @@ -561,6 +563,7 @@ resets = <&syscon ASPEED_RESET_I2C>; interrupts = ; bus-frequency = <100000>; + pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c4_default>; status = "disabled"; }; @@ -575,6 +578,7 @@ resets = <&syscon ASPEED_RESET_I2C>; interrupts = ; bus-frequency = <100000>; + pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c5_default>; status = "disabled"; }; @@ -589,6 +593,7 @@ resets = <&syscon ASPEED_RESET_I2C>; interrupts = ; bus-frequency = <100000>; + pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c6_default>; status = "disabled"; }; @@ -603,6 +608,7 @@ resets = <&syscon ASPEED_RESET_I2C>; interrupts = ; bus-frequency = <100000>; + pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c7_default>; status = "disabled"; }; @@ -617,6 +623,7 @@ resets = <&syscon ASPEED_RESET_I2C>; interrupts = ; bus-frequency = <100000>; + pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c8_default>; status = "disabled"; }; @@ -631,6 +638,7 @@ resets = <&syscon ASPEED_RESET_I2C>; interrupts = ; bus-frequency = <100000>; + pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c9_default>; status = "disabled"; }; @@ -645,6 +653,7 @@ resets = <&syscon ASPEED_RESET_I2C>; interrupts = ; bus-frequency = <100000>; + pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c10_default>; status = "disabled"; }; @@ -659,6 +668,7 @@ resets = <&syscon ASPEED_RESET_I2C>; interrupts = ; bus-frequency = <100000>; + pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c11_default>; status = "disabled"; }; @@ -673,6 +683,7 @@ resets = <&syscon ASPEED_RESET_I2C>; interrupts = ; bus-frequency = <100000>; + pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c12_default>; status = "disabled"; }; @@ -687,6 +698,7 @@ resets = <&syscon ASPEED_RESET_I2C>; interrupts = ; bus-frequency = <100000>; + pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c13_default>; status = "disabled"; }; @@ -701,6 +713,7 @@ resets = <&syscon ASPEED_RESET_I2C>; interrupts = ; bus-frequency = <100000>; + pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c14_default>; status = "disabled"; }; @@ -715,6 +728,7 @@ resets = <&syscon ASPEED_RESET_I2C>; interrupts = ; bus-frequency = <100000>; + pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c15_default>; status = "disabled"; }; @@ -729,6 +743,7 @@ resets = <&syscon ASPEED_RESET_I2C>; interrupts = ; bus-frequency = <100000>; + pinctrl-names = "default"; pinctrl-0 = <&pinctrl_i2c16_default>; status = "disabled"; };