From patchwork Thu Sep 19 22:49:07 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Sam Shih X-Patchwork-Id: 1164949 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 46ZBsj00YYz9sPJ for ; Fri, 20 Sep 2019 08:51:20 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2406202AbfISWvB (ORCPT ); Thu, 19 Sep 2019 18:51:01 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:10136 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S2405645AbfISWvA (ORCPT ); Thu, 19 Sep 2019 18:51:00 -0400 X-UUID: 8ba29d304ad24a47823e1e6bd8fecf5c-20190920 X-UUID: 8ba29d304ad24a47823e1e6bd8fecf5c-20190920 Received: from mtkcas08.mediatek.inc [(172.21.101.126)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 440646369; Fri, 20 Sep 2019 06:50:55 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs08n2.mediatek.inc (172.21.101.56) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Fri, 20 Sep 2019 06:50:49 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Fri, 20 Sep 2019 06:50:49 +0800 From: Sam Shih To: Rob Herring , Mark Rutland , Matthias Brugger , Thierry Reding CC: Ryder Lee , John Crispin , , , , , Sam Shih Subject: [PATCH v9 07/11] dt-bindings: pwm: pwm-mediatek: add a property "num-pwms" Date: Fri, 20 Sep 2019 06:49:07 +0800 Message-ID: <1568933351-8584-8-git-send-email-sam.shih@mediatek.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1568933351-8584-1-git-send-email-sam.shih@mediatek.com> References: <1568933351-8584-1-git-send-email-sam.shih@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: FFEC2990FFC8854E91CF1143C2D186BA71F4D7967EB0BE75220FF2AD442D7BB42000:8 X-MTK: N Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Ryder Lee This adds a property "num-pwms" in example so that we could specify the number of PWM channels via device tree. Signed-off-by: Ryder Lee Signed-off-by: Sam Shih Reviewed-by: Matthias Brugger Acked-by: Uwe Kleine-König --- Changes since v6: Follow reviewers's comments: - The subject should indicate this is for Mediatek Changes since v5: - Add an Acked-by tag - This file is original v4 patch 5/10 (https://patchwork.kernel.org/patch/11102577/) --- Documentation/devicetree/bindings/pwm/pwm-mediatek.txt | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/pwm/pwm-mediatek.txt b/Documentation/devicetree/bindings/pwm/pwm-mediatek.txt index 991728cb46cb..ea95b490a913 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-mediatek.txt +++ b/Documentation/devicetree/bindings/pwm/pwm-mediatek.txt @@ -14,12 +14,12 @@ Required properties: has no clocks - "top": the top clock generator - "main": clock used by the PWM core - - "pwm1-8": the eight per PWM clocks for mt2712 - - "pwm1-6": the six per PWM clocks for mt7622 - - "pwm1-5": the five per PWM clocks for mt7623 + - "pwm1-N": the PWM clocks for each channel + where N starting from 1 to the maximum number of PWM channels - pinctrl-names: Must contain a "default" entry. - pinctrl-0: One property must exist for each entry in pinctrl-names. See pinctrl/pinctrl-bindings.txt for details of the property values. + - num-pwms: the number of PWM channels. Example: pwm0: pwm@11006000 { @@ -37,4 +37,5 @@ Example: "pwm3", "pwm4", "pwm5"; pinctrl-names = "default"; pinctrl-0 = <&pwm0_pins>; + num-pwms = <5>; }; From patchwork Thu Sep 19 22:49:10 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Shih X-Patchwork-Id: 1164946 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 46ZBsW6gLQz9sNk for ; Fri, 20 Sep 2019 08:51:11 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2406399AbfISWvG (ORCPT ); Thu, 19 Sep 2019 18:51:06 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:36261 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S2406262AbfISWvF (ORCPT ); Thu, 19 Sep 2019 18:51:05 -0400 X-UUID: a600f8cbd91f45619bb794e56bce1dc9-20190920 X-UUID: a600f8cbd91f45619bb794e56bce1dc9-20190920 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 1422154027; Fri, 20 Sep 2019 06:50:59 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs08n2.mediatek.inc (172.21.101.56) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Fri, 20 Sep 2019 06:50:54 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Fri, 20 Sep 2019 06:50:54 +0800 From: Sam Shih To: Rob Herring , Mark Rutland , Matthias Brugger , Thierry Reding CC: Ryder Lee , John Crispin , , , , , Sam Shih Subject: [PATCH v9 10/11] dt-bindings: pwm: update bindings for MT7629 SoC Date: Fri, 20 Sep 2019 06:49:10 +0800 Message-ID: <1568933351-8584-11-git-send-email-sam.shih@mediatek.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1568933351-8584-1-git-send-email-sam.shih@mediatek.com> References: <1568933351-8584-1-git-send-email-sam.shih@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: 0E0BD68C5B0239AD628993A1099FE5B3FA385D5F42D3D191052146B1EF60F2402000:8 X-MTK: N Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Ryder Lee This updates bindings for MT7629 pwm controller. Signed-off-by: Ryder Lee Signed-off-by: Sam Shih Reviewed-by: Rob Herring Reviewed-by: Matthias Brugger --- Changes since v7: - add a missed Reviewed-by tag back from v1: https://patchwork.kernel.org/patch/10769381/ Changes since v1: - add a Reviewed-by tag --- Documentation/devicetree/bindings/pwm/pwm-mediatek.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pwm/pwm-mediatek.txt b/Documentation/devicetree/bindings/pwm/pwm-mediatek.txt index ea95b490a913..c7bd5633d1eb 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-mediatek.txt +++ b/Documentation/devicetree/bindings/pwm/pwm-mediatek.txt @@ -6,6 +6,7 @@ Required properties: - "mediatek,mt7622-pwm": found on mt7622 SoC. - "mediatek,mt7623-pwm": found on mt7623 SoC. - "mediatek,mt7628-pwm": found on mt7628 SoC. + - "mediatek,mt7629-pwm", "mediatek,mt7622-pwm": found on mt7629 SoC. - reg: physical base address and length of the controller's registers. - #pwm-cells: must be 2. See pwm.txt in this directory for a description of the cell format.