From patchwork Thu Sep 19 18:46:45 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Paul A. Clarke" X-Patchwork-Id: 1164798 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=sourceware.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=libc-alpha-return-105266-incoming=patchwork.ozlabs.org@sourceware.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=us.ibm.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; secure) header.d=sourceware.org header.i=@sourceware.org header.b="kVyjpcIZ"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 46Z5SB6bFpz9sN1 for ; Fri, 20 Sep 2019 04:47:22 +1000 (AEST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=sourceware.org; h=list-id :list-unsubscribe:list-subscribe:list-archive:list-post :list-help:sender:from:to:cc:subject:date:message-id:in-reply-to :references; q=dns; s=default; b=nvVt2K4RI1T0fgwoEPPWPYE21UKp0Dt y0NRIVXDXQyhlvQtCPK3pTntpOYx8klo/bYFLr7Q6ENUqPm00slzwYgqBhR5t9VL tJ4jVI2vMKoTYU1F0LmKdFM9hFaxau6rP3Vpu2aXrisIiBB9GApBwBB53kfv2mKC zSqSx+BLSR3A= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=sourceware.org; h=list-id :list-unsubscribe:list-subscribe:list-archive:list-post :list-help:sender:from:to:cc:subject:date:message-id:in-reply-to :references; s=default; bh=igZdDc7JhpyB4kRFA52+Y5Fijhc=; b=kVyjp cIZ3uCC0Tn6MlPm5p5Bp/tFo26QbkPjFvDZmxYd0DTDK81wY3xFv3BLWuz/UKZGK WSVt9nTIVqjxIjTTdCo+aWUbzX8ejaPkEvTZpAwVyzKhRqOpLjMxOk0lBtsIb7NI 9EJqtoQEbMo6VRSHJGNURu2/eLMRfhr30H0mvM= Received: (qmail 70332 invoked by alias); 19 Sep 2019 18:46:59 -0000 Mailing-List: contact libc-alpha-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: libc-alpha-owner@sourceware.org Delivered-To: mailing list libc-alpha@sourceware.org Received: (qmail 70267 invoked by uid 89); 19 Sep 2019 18:46:59 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.8 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.1 spammy= X-HELO: mx0a-001b2d01.pphosted.com From: "Paul A. Clarke" To: libc-alpha@sourceware.org Cc: tuliom@ascii.art.br, murphyp@linux.ibm.com Subject: [PATCH v2 1/6] [powerpc] fenv_private.h clean up Date: Thu, 19 Sep 2019 13:46:45 -0500 Message-Id: <1568918810-20393-2-git-send-email-pc@us.ibm.com> In-Reply-To: <1568918810-20393-1-git-send-email-pc@us.ibm.com> References: <1568918810-20393-1-git-send-email-pc@us.ibm.com> From: "Paul A. Clarke" fenv_private.h includes unused functions, magic macro constants, and some replicated common code fragments. Remove unused functions, replace magic constants with constants from fenv_libc.h, and refactor replicated code. Suggested-by: Paul E. Murphy 2019-09-19 Paul A. Clarke * sysdeps/powerpc/fpu/fenv_libc.h: (__TEST_AND_ENTER_NON_STOP): New. (__TEST_AND_EXIT_NON_STOP): New. * sysdeps/powerpc/fpu/fenv_private.h (_FPU_ALL_TRAPS): Delete, replace with FPSCR_ENABLES_MASK. (_FPU_MASK_RN): Delete. (_FPU_MASK_NOT_RN_NI): Delete. (_FPU_MASK_TRAPS_RN): Delete, replace with ~FPSCR_CONTROL_MASK. (_FPU_MASK_FRAC_INEX_RET_CC): Delete, replace with ~FPSCR_STATUS_MASK. (__libc_feholdbits_ppc): Delete, move code into libc_feholdexcept_setround_ppc. (libc_feholdexcept_ppc): Delete. (libc_fesetround_ppc): Delete. (libc_fetestexcept_ppc): Delete. (libc_feholdsetround_ppc): Delete. (__libc_femergeenv_ppc): Use __TEST_AND_ENTER/EXIT_NON_STOP. (libc_feholdsetround_noex_ppc_ctx): Likewise. (libc_feupdateenv_test_ppc): Use FPSCR defines. * sysdeps/powerpc/fpu/feenablxcpt.c (feenableexcept): Use __TEST_AND_ENTER_NON_STOP. * sysdeps/powerpc/fpu/fedisblxcpt.c (fedisableexcept): Likewise. * sysdeps/powerpc/fpu/feholdexcpt.c (__feholdexcept): Likewise. * sysdeps/powerpc/fpu/fesetenv.c (__fesetenv): Likewise. * sysdeps/powerpc/fpu/fesetmode.c (fesetmode): Likewise. * sysdeps/powerpc/fpu/feupdateenv.c (__feupdateenv): Likewise. (_FPU_MASK_ALL): Delete. Reviewed-By: Paul E Murphy --- v2: - Use new __TEST_AND_ENTER/EXIT_NON_STOP macros everywhere. - Remove more local _FPU macros. sysdeps/powerpc/fpu/fedisblxcpt.c | 3 +- sysdeps/powerpc/fpu/feenablxcpt.c | 3 +- sysdeps/powerpc/fpu/feholdexcpt.c | 7 +--- sysdeps/powerpc/fpu/fenv_libc.h | 20 +++++++++ sysdeps/powerpc/fpu/fenv_private.h | 83 +++++--------------------------------- sysdeps/powerpc/fpu/fesetenv.c | 15 +------ sysdeps/powerpc/fpu/fesetmode.c | 7 +--- sysdeps/powerpc/fpu/feupdateenv.c | 17 +------- 8 files changed, 38 insertions(+), 117 deletions(-) diff --git a/sysdeps/powerpc/fpu/fedisblxcpt.c b/sysdeps/powerpc/fpu/fedisblxcpt.c index d0f7fe6..0d9bf00 100644 --- a/sysdeps/powerpc/fpu/fedisblxcpt.c +++ b/sysdeps/powerpc/fpu/fedisblxcpt.c @@ -43,8 +43,7 @@ fedisableexcept (int excepts) if (fe.l != curr.l) fesetenv_mode (fe.fenv); - if (new == 0 && result != 0) - (void)__fe_mask_env (); + __TEST_AND_ENTER_NON_STOP (-1ULL, fe.l); return result; } diff --git a/sysdeps/powerpc/fpu/feenablxcpt.c b/sysdeps/powerpc/fpu/feenablxcpt.c index fc96b24..cf670b8 100644 --- a/sysdeps/powerpc/fpu/feenablxcpt.c +++ b/sysdeps/powerpc/fpu/feenablxcpt.c @@ -43,8 +43,7 @@ feenableexcept (int excepts) if (fe.l != curr.l) fesetenv_mode (fe.fenv); - if (new != 0 && result == 0) - (void) __fe_nomask_env_priv (); + __TEST_AND_EXIT_NON_STOP (0ULL, fe.l); return result; } diff --git a/sysdeps/powerpc/fpu/feholdexcpt.c b/sysdeps/powerpc/fpu/feholdexcpt.c index 2939d64..bcd09f6 100644 --- a/sysdeps/powerpc/fpu/feholdexcpt.c +++ b/sysdeps/powerpc/fpu/feholdexcpt.c @@ -18,7 +18,6 @@ #include #include -#define _FPU_MASK_ALL (_FPU_MASK_ZM | _FPU_MASK_OM | _FPU_MASK_UM | _FPU_MASK_XM | _FPU_MASK_IM) int __feholdexcept (fenv_t *envp) @@ -35,11 +34,7 @@ __feholdexcept (fenv_t *envp) if (new.l == old.l) return 0; - /* If the old env had any enabled exceptions, then mask SIGFPE in the - MSR FE0/FE1 bits. This may allow the FPU to run faster because it - always takes the default action and can not generate SIGFPE. */ - if ((old.l & _FPU_MASK_ALL) != 0) - (void)__fe_mask_env (); + __TEST_AND_ENTER_NON_STOP (old.l, 0ULL); /* Put the new state in effect. */ fesetenv_register (new.fenv); diff --git a/sysdeps/powerpc/fpu/fenv_libc.h b/sysdeps/powerpc/fpu/fenv_libc.h index 59c3d57..bc2684e 100644 --- a/sysdeps/powerpc/fpu/fenv_libc.h +++ b/sysdeps/powerpc/fpu/fenv_libc.h @@ -27,6 +27,26 @@ extern const fenv_t *__fe_nomask_env_priv (void); extern const fenv_t *__fe_mask_env (void) attribute_hidden; +/* If the old env had any enabled exceptions and the new env has no enabled + exceptions, then mask SIGFPE in the MSR FE0/FE1 bits. This may allow the + FPU to run faster because it always takes the default action and can not + generate SIGFPE. */ +#define __TEST_AND_ENTER_NON_STOP(old, new) \ + do { \ + if (((old) & FPSCR_ENABLES_MASK) != 0 && ((new) & FPSCR_ENABLES_MASK) == 0) \ + (void) __fe_mask_env (); \ + } while (0) + +/* If the old env has no enabled exceptions and the new env has any enabled + exceptions, then unmask SIGFPE in the MSR FE0/FE1 bits. This will put the + hardware into "precise mode" and may cause the FPU to run slower on some + hardware. */ +#define __TEST_AND_EXIT_NON_STOP(old, new) \ + do { \ + if (((old) & FPSCR_ENABLES_MASK) == 0 && ((new) & FPSCR_ENABLES_MASK) != 0) \ + (void) __fe_nomask_env_priv (); \ + } while (0) + /* The sticky bits in the FPSCR indicating exceptions have occurred. */ #define FPSCR_STICKY_BITS ((FE_ALL_EXCEPT | FE_ALL_INVALID) & ~FE_INVALID) diff --git a/sysdeps/powerpc/fpu/fenv_private.h b/sysdeps/powerpc/fpu/fenv_private.h index 92a3e92..30cbf30 100644 --- a/sysdeps/powerpc/fpu/fenv_private.h +++ b/sysdeps/powerpc/fpu/fenv_private.h @@ -23,73 +23,20 @@ #include #include -/* Mask for the exception enable bits. */ -#define _FPU_ALL_TRAPS (_FPU_MASK_ZM | _FPU_MASK_OM | _FPU_MASK_UM \ - | _FPU_MASK_XM | _FPU_MASK_IM) - -/* Mask the rounding mode bits. */ -#define _FPU_MASK_RN 0xfffffffffffffffcLL - -/* Mask everything but the rounding modes and non-IEEE arithmetic flags. */ -#define _FPU_MASK_NOT_RN_NI 0xffffffff00000807LL - -/* Mask restore rounding mode and exception enabled. */ -#define _FPU_MASK_TRAPS_RN 0xffffffffffffff00LL - -/* Mask FP result flags, preserve fraction rounded/inexact bits. */ -#define _FPU_MASK_FRAC_INEX_RET_CC 0xfffffffffff80fffLL - static __always_inline void -__libc_feholdbits_ppc (fenv_t *envp, unsigned long long mask, - unsigned long long bits) +libc_feholdexcept_setround_ppc (fenv_t *envp, int r) { fenv_union_t old, new; old.fenv = *envp = fegetenv_register (); - new.l = (old.l & mask) | bits; - - /* If the old env had any enabled exceptions, then mask SIGFPE in the - MSR FE0/FE1 bits. This may allow the FPU to run faster because it - always takes the default action and can not generate SIGFPE. */ - if ((old.l & _FPU_ALL_TRAPS) != 0) - (void) __fe_mask_env (); + __TEST_AND_ENTER_NON_STOP (old.l, 0ULL); + /* Clear everything and set the rounding mode. */ + new.l = r; fesetenv_register (new.fenv); } -static __always_inline void -libc_feholdexcept_ppc (fenv_t *envp) -{ - __libc_feholdbits_ppc (envp, _FPU_MASK_NOT_RN_NI, 0LL); -} - -static __always_inline void -libc_feholdexcept_setround_ppc (fenv_t *envp, int r) -{ - __libc_feholdbits_ppc (envp, _FPU_MASK_NOT_RN_NI & _FPU_MASK_RN, r); -} - -static __always_inline void -libc_fesetround_ppc (int r) -{ - __fesetround_inline (r); -} - -static __always_inline int -libc_fetestexcept_ppc (int e) -{ - fenv_union_t u; - u.fenv = fegetenv_register (); - return u.l & e; -} - -static __always_inline void -libc_feholdsetround_ppc (fenv_t *e, int r) -{ - __libc_feholdbits_ppc (e, _FPU_MASK_TRAPS_RN, r); -} - static __always_inline unsigned long long __libc_femergeenv_ppc (const fenv_t *envp, unsigned long long old_mask, unsigned long long new_mask) @@ -102,19 +49,8 @@ __libc_femergeenv_ppc (const fenv_t *envp, unsigned long long old_mask, /* Merge bits while masking unwanted bits from new and old env. */ new.l = (old.l & old_mask) | (new.l & new_mask); - /* If the old env has no enabled exceptions and the new env has any enabled - exceptions, then unmask SIGFPE in the MSR FE0/FE1 bits. This will put the - hardware into "precise mode" and may cause the FPU to run slower on some - hardware. */ - if ((old.l & _FPU_ALL_TRAPS) == 0 && (new.l & _FPU_ALL_TRAPS) != 0) - (void) __fe_nomask_env_priv (); - - /* If the old env had any enabled exceptions and the new env has no enabled - exceptions, then mask SIGFPE in the MSR FE0/FE1 bits. This may allow the - FPU to run faster because it always takes the default action and can not - generate SIGFPE. */ - if ((old.l & _FPU_ALL_TRAPS) != 0 && (new.l & _FPU_ALL_TRAPS) == 0) - (void) __fe_mask_env (); + __TEST_AND_EXIT_NON_STOP (old.l, new.l); + __TEST_AND_ENTER_NON_STOP (old.l, new.l); /* Atomically enable and raise (if appropriate) exceptions set in `new'. */ fesetenv_register (new.fenv); @@ -139,8 +75,8 @@ libc_feresetround_ppc (fenv_t *envp) static __always_inline int libc_feupdateenv_test_ppc (fenv_t *envp, int ex) { - return __libc_femergeenv_ppc (envp, _FPU_MASK_TRAPS_RN, - _FPU_MASK_FRAC_INEX_RET_CC) & ex; + return __libc_femergeenv_ppc (envp, ~FPSCR_CONTROL_MASK, + ~FPSCR_STATUS_MASK) & ex; } static __always_inline void @@ -193,8 +129,7 @@ libc_feholdsetround_noex_ppc_ctx (struct rm_ctx *ctx, int r) ctx->env = old.fenv; if (__glibc_unlikely (new.l != old.l)) { - if ((old.l & _FPU_ALL_TRAPS) != 0) - (void) __fe_mask_env (); + __TEST_AND_ENTER_NON_STOP (old.l, 0ULL); fesetenv_register (new.fenv); ctx->updated_status = true; } diff --git a/sysdeps/powerpc/fpu/fesetenv.c b/sysdeps/powerpc/fpu/fesetenv.c index 96f8d99..949d916 100644 --- a/sysdeps/powerpc/fpu/fesetenv.c +++ b/sysdeps/powerpc/fpu/fesetenv.c @@ -28,19 +28,8 @@ __fesetenv (const fenv_t *envp) new.fenv = *envp; old.fenv = fegetenv_status (); - /* If the old env has no enabled exceptions and the new env has any enabled - exceptions, then unmask SIGFPE in the MSR FE0/FE1 bits. This will put the - hardware into "precise mode" and may cause the FPU to run slower on some - hardware. */ - if ((old.l & FPSCR_ENABLES_MASK) == 0 && (new.l & FPSCR_ENABLES_MASK) != 0) - (void) __fe_nomask_env_priv (); - - /* If the old env had any enabled exceptions and the new env has no enabled - exceptions, then mask SIGFPE in the MSR FE0/FE1 bits. This may allow the - FPU to run faster because it always takes the default action and can not - generate SIGFPE. */ - if ((old.l & FPSCR_ENABLES_MASK) != 0 && (new.l & FPSCR_ENABLES_MASK) == 0) - (void)__fe_mask_env (); + __TEST_AND_EXIT_NON_STOP (old.l, new.l); + __TEST_AND_ENTER_NON_STOP (old.l, new.l); fesetenv_register (new.fenv); diff --git a/sysdeps/powerpc/fpu/fesetmode.c b/sysdeps/powerpc/fpu/fesetmode.c index 92fc15c..90d86a9 100644 --- a/sysdeps/powerpc/fpu/fesetmode.c +++ b/sysdeps/powerpc/fpu/fesetmode.c @@ -33,11 +33,8 @@ fesetmode (const femode_t *modep) if (old.l == new.l) return 0; - if ((old.l & FPSCR_ENABLES_MASK) == 0 && (new.l & FPSCR_ENABLES_MASK) != 0) - (void) __fe_nomask_env_priv (); - - if ((old.l & FPSCR_ENABLES_MASK) != 0 && (new.l & FPSCR_ENABLES_MASK) == 0) - (void) __fe_mask_env (); + __TEST_AND_EXIT_NON_STOP (old.l, new.l); + __TEST_AND_ENTER_NON_STOP (old.l, new.l); fesetenv_mode (new.fenv); return 0; diff --git a/sysdeps/powerpc/fpu/feupdateenv.c b/sysdeps/powerpc/fpu/feupdateenv.c index 931de60..d5c7394 100644 --- a/sysdeps/powerpc/fpu/feupdateenv.c +++ b/sysdeps/powerpc/fpu/feupdateenv.c @@ -20,8 +20,6 @@ #include #include -#define _FPU_MASK_ALL (_FPU_MASK_ZM | _FPU_MASK_OM | _FPU_MASK_UM | _FPU_MASK_XM | _FPU_MASK_IM) - int __feupdateenv (const fenv_t *envp) { @@ -36,19 +34,8 @@ __feupdateenv (const fenv_t *envp) unchanged. */ new.l = (old.l & 0xffffffff1fffff00LL) | (new.l & 0x1ff80fff); - /* If the old env has no enabled exceptions and the new env has any enabled - exceptions, then unmask SIGFPE in the MSR FE0/FE1 bits. This will put - the hardware into "precise mode" and may cause the FPU to run slower on - some hardware. */ - if ((old.l & _FPU_MASK_ALL) == 0 && (new.l & _FPU_MASK_ALL) != 0) - (void) __fe_nomask_env_priv (); - - /* If the old env had any enabled exceptions and the new env has no enabled - exceptions, then mask SIGFPE in the MSR FE0/FE1 bits. This may allow the - FPU to run faster because it always takes the default action and can not - generate SIGFPE. */ - if ((old.l & _FPU_MASK_ALL) != 0 && (new.l & _FPU_MASK_ALL) == 0) - (void)__fe_mask_env (); + __TEST_AND_EXIT_NON_STOP (old.l, new.l); + __TEST_AND_ENTER_NON_STOP (old.l, new.l); /* Atomically enable and raise (if appropriate) exceptions set in `new'. */ fesetenv_register (new.fenv); From patchwork Thu Sep 19 18:46:46 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Paul A. Clarke" X-Patchwork-Id: 1164797 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=sourceware.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=libc-alpha-return-105265-incoming=patchwork.ozlabs.org@sourceware.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=us.ibm.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; secure) header.d=sourceware.org header.i=@sourceware.org header.b="USlKeiuu"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 46Z5S04HMFz9sN1 for ; Fri, 20 Sep 2019 04:47:12 +1000 (AEST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=sourceware.org; h=list-id :list-unsubscribe:list-subscribe:list-archive:list-post :list-help:sender:from:to:cc:subject:date:message-id:in-reply-to :references; q=dns; s=default; b=YZmS0/QqcmQoGfXLdxRMFEP1I+Z3m+o eWroqRqEEd7I78K2Npp5jWgVpoMRc+2+jKb4UYVNbEebFewVjduL3oKwXsxiQlcY nP2+Uis6LReBZB+IiOKvJuYg8zOHnpFYkVM+qImLEeR7ys+9VlyeA3bQD7CzTbBp VNgThGNcPbMI= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=sourceware.org; h=list-id :list-unsubscribe:list-subscribe:list-archive:list-post :list-help:sender:from:to:cc:subject:date:message-id:in-reply-to :references; s=default; bh=/M6t15mC2ENXXzASOHJm3wVcMMI=; b=USlKe iuumTpP35Dd3GcPh1Obe/km8RgTvz3FN/Fvcm26RK11r+JNoUuOB4+BcPyF/HvHK pPWoSG82z7GlQUw4ooSyLG9v7wRqclJQ4Qk6eTiY8Rzq7abzSkvpijamhfa2xVnt KylI19g5/PecWtBuw6JzRGKjHycoIPTPb8+flc= Received: (qmail 70124 invoked by alias); 19 Sep 2019 18:46:58 -0000 Mailing-List: contact libc-alpha-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: libc-alpha-owner@sourceware.org Delivered-To: mailing list libc-alpha@sourceware.org Received: (qmail 70077 invoked by uid 89); 19 Sep 2019 18:46:58 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.7 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_LOW autolearn=ham version=3.3.1 spammy=HX-Languages-Length:2220 X-HELO: mx0a-001b2d01.pphosted.com From: "Paul A. Clarke" To: libc-alpha@sourceware.org Cc: tuliom@ascii.art.br, murphyp@linux.ibm.com Subject: [PATCH v2 2/6] [powerpc] No need to enter "Ignore Exceptions Mode" Date: Thu, 19 Sep 2019 13:46:46 -0500 Message-Id: <1568918810-20393-3-git-send-email-pc@us.ibm.com> In-Reply-To: <1568918810-20393-1-git-send-email-pc@us.ibm.com> References: <1568918810-20393-1-git-send-email-pc@us.ibm.com> From: "Paul A. Clarke" Since at least POWER8, there is no performance advantage to entering "Ignore Exceptions Mode", and doing so conditionally requires the conditional logic as well as a system call. Make it a no-op. 2019-09-19 Paul A. Clarke * sysdeps/powerpc/fpu/fenv_libc.h: (__ENTER_NON_STOP): New. (__EXIT_NON_STOP): New. (__TEST_AND_ENTER_NON_STOP): Use __ENTER_NON_STOP. (__TEST_AND_EXIT_NON_STOP): Use __EXIT_NON_STOP. Reviewed-By: Paul E Murphy --- v2: This is a new patch in the series. sysdeps/powerpc/fpu/fenv_libc.h | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/sysdeps/powerpc/fpu/fenv_libc.h b/sysdeps/powerpc/fpu/fenv_libc.h index bc2684e..549defa 100644 --- a/sysdeps/powerpc/fpu/fenv_libc.h +++ b/sysdeps/powerpc/fpu/fenv_libc.h @@ -27,6 +27,14 @@ extern const fenv_t *__fe_nomask_env_priv (void); extern const fenv_t *__fe_mask_env (void) attribute_hidden; +#ifdef _ARCH_PWR8 +/* There is no performance advantage to non-stop mode. */ +#define __ENTER_NON_STOP() do {} while (0) +#else +#define __ENTER_NON_STOP() do { (void) __fe_mask_env (); } while (0) +#endif +#define __EXIT_NON_STOP() do { (void) __fe_nomask_env_priv (); } while (0) + /* If the old env had any enabled exceptions and the new env has no enabled exceptions, then mask SIGFPE in the MSR FE0/FE1 bits. This may allow the FPU to run faster because it always takes the default action and can not @@ -34,7 +42,7 @@ extern const fenv_t *__fe_mask_env (void) attribute_hidden; #define __TEST_AND_ENTER_NON_STOP(old, new) \ do { \ if (((old) & FPSCR_ENABLES_MASK) != 0 && ((new) & FPSCR_ENABLES_MASK) == 0) \ - (void) __fe_mask_env (); \ + __ENTER_NON_STOP (); \ } while (0) /* If the old env has no enabled exceptions and the new env has any enabled @@ -44,7 +52,7 @@ extern const fenv_t *__fe_mask_env (void) attribute_hidden; #define __TEST_AND_EXIT_NON_STOP(old, new) \ do { \ if (((old) & FPSCR_ENABLES_MASK) == 0 && ((new) & FPSCR_ENABLES_MASK) != 0) \ - (void) __fe_nomask_env_priv (); \ + __EXIT_NON_STOP (); \ } while (0) /* The sticky bits in the FPSCR indicating exceptions have occurred. */ From patchwork Thu Sep 19 18:46:47 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Paul A. Clarke" X-Patchwork-Id: 1164799 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=sourceware.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=libc-alpha-return-105267-incoming=patchwork.ozlabs.org@sourceware.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=us.ibm.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; secure) header.d=sourceware.org header.i=@sourceware.org header.b="YFZpNsZm"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 46Z5SN5tpbz9sN1 for ; Fri, 20 Sep 2019 04:47:32 +1000 (AEST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=sourceware.org; h=list-id :list-unsubscribe:list-subscribe:list-archive:list-post :list-help:sender:from:to:cc:subject:date:message-id:in-reply-to :references; q=dns; s=default; b=f6yfxSkScUC1oXDC0HgH9YLuzbOyl1T lxwv1+8dkhRMHJm8Wm1aPLeWVKqFkg8BBHffKssvOWkSyy8Fm7QqwSMV/kPzF5CM 2EpqhV7PjvyPP/8J0s3dNc2hK04OHBOA/eWX7Xt+JvyAnFZ1Wb9B6vwhz3hM0ifG V9nwhAtan2UU= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=sourceware.org; h=list-id :list-unsubscribe:list-subscribe:list-archive:list-post :list-help:sender:from:to:cc:subject:date:message-id:in-reply-to :references; s=default; bh=UBFaQUtjXOlnOSI4nL6a78X1AZ0=; b=YFZpN sZmvTyniHlPE04rP3F2/jZdoXhiDhJNYWkFw56aU+pVA0L6KtcBSrQJStIMSTzBF DRFLfXjPsNQqs5YQz8UZjaDw8smBocH22l+h+8t/kqvWD5mkJC4+PGj6Lk8Uv0by Te79C6b0mIRAt0NwHT/MjSljl2jT7n5Ks/WQgA= Received: (qmail 70393 invoked by alias); 19 Sep 2019 18:47:00 -0000 Mailing-List: contact libc-alpha-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: libc-alpha-owner@sourceware.org Delivered-To: mailing list libc-alpha@sourceware.org Received: (qmail 70307 invoked by uid 89); 19 Sep 2019 18:46:59 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.8 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_LOW autolearn=ham version=3.3.1 spammy=Murphy X-HELO: mx0a-001b2d01.pphosted.com From: "Paul A. Clarke" To: libc-alpha@sourceware.org Cc: tuliom@ascii.art.br, murphyp@linux.ibm.com Subject: [PATCH v2 3/6] [powerpc] libc_feupdateenv_test: optimize FPSCR access Date: Thu, 19 Sep 2019 13:46:47 -0500 Message-Id: <1568918810-20393-4-git-send-email-pc@us.ibm.com> In-Reply-To: <1568918810-20393-1-git-send-email-pc@us.ibm.com> References: <1568918810-20393-1-git-send-email-pc@us.ibm.com> From: "Paul A. Clarke" ROUND_TO_ODD and a couple of other places use libc_feupdateenv_test to restore the rounding mode and exception enables, preserve exception flags, and test whether given exception(s) were generated. If the exception flags haven't changed, then it is sufficient and a bit more efficient to just restore the rounding mode and enables, rather than writing the full Floating-Point Status and Control Register (FPSCR). Reviewed-by: Paul E. Murphy 2019-09-19 Paul A. Clarke * sysdeps/powerpc/fpu/fenv_libc.h (FPSCR_EXCEPTIONS_MASK): New. * sysdeps/powerpc/fpu/fenv_private.h (__libc_femergeenv_ppc): Optimize to write FPSCR control only, if exceptions have not changed. Reviewed-By: Paul E Murphy --- v2: - No changes, but respun after removing _FPU macros at the suggestion of Paul Murphy, to make it a bit easier to review. sysdeps/powerpc/fpu/fenv_libc.h | 4 ++++ sysdeps/powerpc/fpu/fenv_private.h | 16 ++++++++++++++-- 2 files changed, 18 insertions(+), 2 deletions(-) diff --git a/sysdeps/powerpc/fpu/fenv_libc.h b/sysdeps/powerpc/fpu/fenv_libc.h index 549defa..53de1c8 100644 --- a/sysdeps/powerpc/fpu/fenv_libc.h +++ b/sysdeps/powerpc/fpu/fenv_libc.h @@ -264,6 +264,10 @@ enum { (FPSCR_VE_MASK|FPSCR_OE_MASK|FPSCR_UE_MASK|FPSCR_ZE_MASK|FPSCR_XE_MASK) #define FPSCR_BASIC_EXCEPTIONS_MASK \ (FPSCR_VX_MASK|FPSCR_OX_MASK|FPSCR_UX_MASK|FPSCR_ZX_MASK|FPSCR_XX_MASK) +#define FPSCR_EXCEPTIONS_MASK (FPSCR_BASIC_EXCEPTIONS_MASK| \ + FPSCR_VXSNAN_MASK|FPSCR_VXISI_MASK|FPSCR_VXIDI_MASK|FPSCR_VXZDZ_MASK| \ + FPSCR_VXIMZ_MASK|FPSCR_VXVC_MASK|FPSCR_VXSOFT_MASK|FPSCR_VXSQRT_MASK| \ + FPSCR_VXCVI_MASK) #define FPSCR_FPRF_MASK \ (FPSCR_FPRF_C_MASK|FPSCR_FPRF_FL_MASK|FPSCR_FPRF_FG_MASK| \ FPSCR_FPRF_FE_MASK|FPSCR_FPRF_FU_MASK) diff --git a/sysdeps/powerpc/fpu/fenv_private.h b/sysdeps/powerpc/fpu/fenv_private.h index 30cbf30..9496026 100644 --- a/sysdeps/powerpc/fpu/fenv_private.h +++ b/sysdeps/powerpc/fpu/fenv_private.h @@ -52,8 +52,20 @@ __libc_femergeenv_ppc (const fenv_t *envp, unsigned long long old_mask, __TEST_AND_EXIT_NON_STOP (old.l, new.l); __TEST_AND_ENTER_NON_STOP (old.l, new.l); - /* Atomically enable and raise (if appropriate) exceptions set in `new'. */ - fesetenv_register (new.fenv); + /* If requesting to keep status, replace control, and merge exceptions, + and exceptions haven't changed, we can just set new control instead + of the whole FPSCR. */ + if ((old_mask & (FPSCR_CONTROL_MASK|FPSCR_STATUS_MASK|FPSCR_EXCEPTIONS_MASK)) + == (FPSCR_STATUS_MASK|FPSCR_EXCEPTIONS_MASK) && + (new_mask & (FPSCR_CONTROL_MASK|FPSCR_STATUS_MASK|FPSCR_EXCEPTIONS_MASK)) + == (FPSCR_CONTROL_MASK|FPSCR_EXCEPTIONS_MASK) && + (old.l & FPSCR_EXCEPTIONS_MASK) == (new.l & FPSCR_EXCEPTIONS_MASK)) + { + fesetenv_mode (new.fenv); + } + else + /* Atomically enable and raise (if appropriate) exceptions set in `new'. */ + fesetenv_register (new.fenv); return old.l; } From patchwork Thu Sep 19 18:46:48 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Paul A. Clarke" X-Patchwork-Id: 1164800 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=sourceware.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=libc-alpha-return-105268-incoming=patchwork.ozlabs.org@sourceware.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=us.ibm.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; secure) header.d=sourceware.org header.i=@sourceware.org header.b="mlfKvrdH"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 46Z5Sd3bTYz9sN1 for ; Fri, 20 Sep 2019 04:47:45 +1000 (AEST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=sourceware.org; h=list-id :list-unsubscribe:list-subscribe:list-archive:list-post :list-help:sender:from:to:cc:subject:date:message-id:in-reply-to :references; q=dns; s=default; b=j8nqXZ08iwrxxRqWVp21dqcD1c43RIq j4wjUIYI0IZae1ptlRaiQrc3FbTUo6bjIscMcaydhEYE9m7qWjy/YqKmWKVdnQfm WRU2OHJLyrLAEQSDyLVBxRZY4tKEB3T0xsC1FutjGk20AgZAGWeCKMrlUAZ2Nffi wmUx7k9miFZ0= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=sourceware.org; h=list-id :list-unsubscribe:list-subscribe:list-archive:list-post :list-help:sender:from:to:cc:subject:date:message-id:in-reply-to :references; s=default; bh=R8EIRJEY119N2Vb6W0biNNJFeaA=; b=mlfKv rdHVEZc5POmgzV6/hLPm7VC30u0oP4HW+CpcKcrmCZ94V1mMUdq7OKosTgauWs83 nrsVZLV7ArD8BUUhTRp/Tu80Bh1TzMpLa1fqKyIpe4u3tpbCWLpbyqRSBK/++A+b egM2b76SzENYTQTkeGOhKPRQsIgOmVu1NAEFu4= Received: (qmail 70745 invoked by alias); 19 Sep 2019 18:47:02 -0000 Mailing-List: contact libc-alpha-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: libc-alpha-owner@sourceware.org Delivered-To: mailing list libc-alpha@sourceware.org Received: (qmail 70690 invoked by uid 89); 19 Sep 2019 18:47:01 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.9 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_LOW autolearn=ham version=3.3.1 spammy=HX-Languages-Length:1226 X-HELO: mx0a-001b2d01.pphosted.com From: "Paul A. Clarke" To: libc-alpha@sourceware.org Cc: tuliom@ascii.art.br, murphyp@linux.ibm.com Subject: [PATCH v2 4/6] [powerpc] libc_feholdsetround_noex_ppc_ctx: optimize FPSCR write Date: Thu, 19 Sep 2019 13:46:48 -0500 Message-Id: <1568918810-20393-5-git-send-email-pc@us.ibm.com> In-Reply-To: <1568918810-20393-1-git-send-email-pc@us.ibm.com> References: <1568918810-20393-1-git-send-email-pc@us.ibm.com> From: "Paul A. Clarke" libc_feholdsetround_noex_ppc_ctx currently does, basically: 1. Read FPSCR, save to context. 2. Create new FPSCR value: clear enables and set new rounding mode. 3. Write new value to FPSCR. Since other bits just pass through, there is no need to write them. Instead, write just the changed values (enables and rounding mode), which can be a bit more efficient. 2019-09-19 Paul A. Clarke * sysdeps/powerpc/fpu/fenv_private.h (libc_feholdsetround_noex_ppc_ctx): Call fesetenv_mode instead of fesetenv_register. Reviewed-By: Paul E Murphy --- v2: No change. sysdeps/powerpc/fpu/fenv_private.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sysdeps/powerpc/fpu/fenv_private.h b/sysdeps/powerpc/fpu/fenv_private.h index 9496026..ade0bfa 100644 --- a/sysdeps/powerpc/fpu/fenv_private.h +++ b/sysdeps/powerpc/fpu/fenv_private.h @@ -142,7 +142,7 @@ libc_feholdsetround_noex_ppc_ctx (struct rm_ctx *ctx, int r) if (__glibc_unlikely (new.l != old.l)) { __TEST_AND_ENTER_NON_STOP (old.l, 0ULL); - fesetenv_register (new.fenv); + fesetenv_mode (new.fenv); ctx->updated_status = true; } else From patchwork Thu Sep 19 18:46:49 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Paul A. Clarke" X-Patchwork-Id: 1164802 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=sourceware.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=libc-alpha-return-105270-incoming=patchwork.ozlabs.org@sourceware.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=us.ibm.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; secure) header.d=sourceware.org header.i=@sourceware.org header.b="eek72OcB"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 46Z5T44kw5z9sNw for ; Fri, 20 Sep 2019 04:48:08 +1000 (AEST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=sourceware.org; h=list-id :list-unsubscribe:list-subscribe:list-archive:list-post :list-help:sender:from:to:cc:subject:date:message-id:in-reply-to :references; q=dns; s=default; b=GCoB+t84up5SMzdyYj0n9QPllfbuZsN V90ZOLOFfn8ND1YRy+uV4SIn520J7FhF6pvEEcQxNwWLVB8csEcjCQrwsgWyQVEN ELfm3gg3USbIYvsSNL94iIJ9JHT/fjPgpEz0NnBZFPHK6m+l0hzLNj7huYorDbOp QRip3x+9NreU= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=sourceware.org; h=list-id :list-unsubscribe:list-subscribe:list-archive:list-post :list-help:sender:from:to:cc:subject:date:message-id:in-reply-to :references; s=default; bh=T1rQxah1OCVYEgqFN/0R/aEJ/Ro=; b=eek72 OcBgX4s8TI6FYXQr6N1YVRSKVWbGqRyXw5YkzoYOtTIa80+1PbIvzNts1il9njgB 48TJAdNw/2htujdz30vAKuBGqZxsHL/9zZvqStX66Vm/sWo1tFUYUB5Rr1GHcTlH xdWuYFtkPV/7XGycB9BkTFQ0gaY7MYYtlWpXb8= Received: (qmail 72251 invoked by alias); 19 Sep 2019 18:47:12 -0000 Mailing-List: contact libc-alpha-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: libc-alpha-owner@sourceware.org Delivered-To: mailing list libc-alpha@sourceware.org Received: (qmail 72202 invoked by uid 89); 19 Sep 2019 18:47:12 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-27.0 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_LOW autolearn=ham version=3.3.1 spammy= X-HELO: mx0a-001b2d01.pphosted.com From: "Paul A. Clarke" To: libc-alpha@sourceware.org Cc: tuliom@ascii.art.br, murphyp@linux.ibm.com Subject: [PATCH v2 5/6] [powerpc] __fesetround_inline optimizations Date: Thu, 19 Sep 2019 13:46:49 -0500 Message-Id: <1568918810-20393-6-git-send-email-pc@us.ibm.com> In-Reply-To: <1568918810-20393-1-git-send-email-pc@us.ibm.com> References: <1568918810-20393-1-git-send-email-pc@us.ibm.com> From: "Paul A. Clarke" On POWER9, use more efficient means to update the 2-bit rounding mode via the 'mffscrn' instruction (instead of two 'mtfsb0/1' instructions or one 'mtfsfi' instruction that modifies 4 bits). Suggested-by: Paul E. Murphy 2019-09-19 Paul A. Clarke * sysdeps/powerpc/fpu/fenv_libc.h (__fesetround_inline): Use 'mffscrn' instruction on POWER9. (__fesetround_inline_nocheck): Likewise. Reviewed-By: Paul E Murphy --- v2: No change. sysdeps/powerpc/fpu/fenv_libc.h | 18 +++++++++++++++--- 1 file changed, 15 insertions(+), 3 deletions(-) diff --git a/sysdeps/powerpc/fpu/fenv_libc.h b/sysdeps/powerpc/fpu/fenv_libc.h index 53de1c8..3b91340 100644 --- a/sysdeps/powerpc/fpu/fenv_libc.h +++ b/sysdeps/powerpc/fpu/fenv_libc.h @@ -156,7 +156,12 @@ typedef union static inline int __fesetround_inline (int round) { - if ((unsigned int) round < 2) +#ifdef _ARCH_PWR9 + __fe_mffscrn (round); +#else + if (__glibc_likely (GLRO(dl_hwcap2) & PPC_FEATURE2_ARCH_3_00)) + __fe_mffscrn (round); + else if ((unsigned int) round < 2) { asm volatile ("mtfsb0 30"); if ((unsigned int) round == 0) @@ -172,7 +177,7 @@ __fesetround_inline (int round) else asm volatile ("mtfsb1 31"); } - +#endif return 0; } @@ -181,7 +186,14 @@ __fesetround_inline (int round) static inline void __fesetround_inline_nocheck (const int round) { - asm volatile ("mtfsfi 7,%0" : : "i" (round)); +#ifdef _ARCH_PWR9 + __fe_mffscrn (round); +#else + if (__glibc_likely (GLRO(dl_hwcap2) & PPC_FEATURE2_ARCH_3_00)) + __fe_mffscrn (round); + else + asm volatile ("mtfsfi 7,%0" : : "i" (round)); +#endif } #define FPSCR_MASK(bit) (1 << (31 - (bit))) From patchwork Thu Sep 19 18:46:50 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Paul A. Clarke" X-Patchwork-Id: 1164801 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=sourceware.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=libc-alpha-return-105269-incoming=patchwork.ozlabs.org@sourceware.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=us.ibm.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; secure) header.d=sourceware.org header.i=@sourceware.org header.b="ETnPtVyY"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 46Z5Sr13vdz9sN1 for ; Fri, 20 Sep 2019 04:47:55 +1000 (AEST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=sourceware.org; h=list-id :list-unsubscribe:list-subscribe:list-archive:list-post :list-help:sender:from:to:cc:subject:date:message-id:in-reply-to :references; q=dns; s=default; b=js8aWaHM0CsVbpmVBHam3KNz8vlDTS+ 2ZPNjwQ4usuVNz6Oltu+I2P5+RCSt7Dvnzra+WMq3ps2ZsPENQM8urjUFnJtcwpu z1bYEaIKh5Dm5Tl2YA252PP+Zop2LcgGgFQFlcjY0MBV8HFTpaml9kpqgW1++1ec U1ZXjoW2C/GU= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=sourceware.org; h=list-id :list-unsubscribe:list-subscribe:list-archive:list-post :list-help:sender:from:to:cc:subject:date:message-id:in-reply-to :references; s=default; bh=QgLd9xBySefE4mwzhEYviCiDryo=; b=ETnPt VyYVM4zQfK15bfGA+cpNSIBf//eebljPlMQnJDf/Znfknl7KG7sA4smtAWrTF74i DuDvppG/72VB8HJaNVwJWuGn+ZkNeiy5T1BCiCwBp9j58YUFcUFwzVsv1PScfQzo wHFA8DatsENjXWPdRrYDu6lS67iKRd0INnGNGE= Received: (qmail 71418 invoked by alias); 19 Sep 2019 18:47:07 -0000 Mailing-List: contact libc-alpha-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: libc-alpha-owner@sourceware.org Delivered-To: mailing list libc-alpha@sourceware.org Received: (qmail 71326 invoked by uid 89); 19 Sep 2019 18:47:06 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-26.9 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.1 spammy= X-HELO: mx0a-001b2d01.pphosted.com From: "Paul A. Clarke" To: libc-alpha@sourceware.org Cc: tuliom@ascii.art.br, murphyp@linux.ibm.com Subject: [PATCH v2 6/6] [powerpc] Rename fegetenv_status to fegetenv_control Date: Thu, 19 Sep 2019 13:46:50 -0500 Message-Id: <1568918810-20393-7-git-send-email-pc@us.ibm.com> In-Reply-To: <1568918810-20393-1-git-send-email-pc@us.ibm.com> References: <1568918810-20393-1-git-send-email-pc@us.ibm.com> From: "Paul A. Clarke" fegetenv_status is used variously to retrieve the FPSCR exception enable bits, rounding mode bits, or both. These are referred to as the control bits in the POWER ISA. FPSCR status bits are also returned by the 'mffs' and 'mffsl' instructions, but they are uniformly ignored by all uses of fegetenv_status. Change the name to be reflective of its current and expected use. 2019-09-19 Paul A. Clarke * sysdeps/powerpc/fpu/fenv_libc.h (fegetenv_status): Rename to fegetenv_control. * sysdeps/powerpc/fpu/fedisblxcpt.c (fedisableexcept): Accommodate rename of fegetenv_status to fegetenv_control. * sysdeps/powerpc/fpu/feenablxcpt.c (feenableexcept): Likewise. * sysdeps/powerpc/fpu/fegetexcept.c (__fegetexcept): Likewise. * sysdeps/powerpc/fpu/fegetmode.c (fegetmode): Likewise. * sysdeps/powerpc/fpu/fesetenv.c (__fesetenv): Likewise. * sysdeps/powerpc/fpu/fesetmode.c (fesetmode): Likewise. Reviewed-By: Paul E Murphy --- v2: This is a new patch in the series. sysdeps/powerpc/fpu/fedisblxcpt.c | 2 +- sysdeps/powerpc/fpu/feenablxcpt.c | 2 +- sysdeps/powerpc/fpu/fegetexcept.c | 2 +- sysdeps/powerpc/fpu/fegetmode.c | 2 +- sysdeps/powerpc/fpu/fenv_libc.h | 6 +++--- sysdeps/powerpc/fpu/fesetenv.c | 2 +- sysdeps/powerpc/fpu/fesetmode.c | 2 +- 7 files changed, 9 insertions(+), 9 deletions(-) diff --git a/sysdeps/powerpc/fpu/fedisblxcpt.c b/sysdeps/powerpc/fpu/fedisblxcpt.c index 0d9bf00..870cfc8 100644 --- a/sysdeps/powerpc/fpu/fedisblxcpt.c +++ b/sysdeps/powerpc/fpu/fedisblxcpt.c @@ -26,7 +26,7 @@ fedisableexcept (int excepts) int result, new; /* Get current exception mask to return. */ - fe.fenv = curr.fenv = fegetenv_status (); + fe.fenv = curr.fenv = fegetenv_control (); result = fenv_reg_to_exceptions (fe.l); if ((excepts & FE_ALL_INVALID) == FE_ALL_INVALID) diff --git a/sysdeps/powerpc/fpu/feenablxcpt.c b/sysdeps/powerpc/fpu/feenablxcpt.c index cf670b8..43f6482 100644 --- a/sysdeps/powerpc/fpu/feenablxcpt.c +++ b/sysdeps/powerpc/fpu/feenablxcpt.c @@ -26,7 +26,7 @@ feenableexcept (int excepts) int result, new; /* Get current exception mask to return. */ - fe.fenv = curr.fenv = fegetenv_status (); + fe.fenv = curr.fenv = fegetenv_control (); result = fenv_reg_to_exceptions (fe.l); if ((excepts & FE_ALL_INVALID) == FE_ALL_INVALID) diff --git a/sysdeps/powerpc/fpu/fegetexcept.c b/sysdeps/powerpc/fpu/fegetexcept.c index bd27a80..179e3c4 100644 --- a/sysdeps/powerpc/fpu/fegetexcept.c +++ b/sysdeps/powerpc/fpu/fegetexcept.c @@ -24,7 +24,7 @@ __fegetexcept (void) { fenv_union_t fe; - fe.fenv = fegetenv_status (); + fe.fenv = fegetenv_control (); return fenv_reg_to_exceptions (fe.l); } diff --git a/sysdeps/powerpc/fpu/fegetmode.c b/sysdeps/powerpc/fpu/fegetmode.c index 0e0a01c..65c5ebe 100644 --- a/sysdeps/powerpc/fpu/fegetmode.c +++ b/sysdeps/powerpc/fpu/fegetmode.c @@ -21,6 +21,6 @@ int fegetmode (femode_t *modep) { - *modep = fegetenv_status (); + *modep = fegetenv_control (); return 0; } diff --git a/sysdeps/powerpc/fpu/fenv_libc.h b/sysdeps/powerpc/fpu/fenv_libc.h index 3b91340..231d264 100644 --- a/sysdeps/powerpc/fpu/fenv_libc.h +++ b/sysdeps/powerpc/fpu/fenv_libc.h @@ -68,7 +68,7 @@ extern const fenv_t *__fe_mask_env (void) attribute_hidden; 'mffs' on architectures older than "power9" because the additional bits set for 'mffsl' are "don't care" for 'mffs'. 'mffs' is a superset of 'mffsl'. */ -#define fegetenv_status() \ +#define fegetenv_control() \ ({register double __fr; \ __asm__ __volatile__ ( \ ".machine push; .machine \"power9\"; mffsl %0; .machine pop" \ @@ -92,7 +92,7 @@ extern const fenv_t *__fe_mask_env (void) attribute_hidden; __fr.fenv; \ }) -/* Like fegetenv_status, but also sets the rounding mode. */ +/* Like fegetenv_control, but also sets the rounding mode. */ #ifdef _ARCH_PWR9 #define fegetenv_and_set_rn(rn) __fe_mffscrn (rn) #else @@ -123,7 +123,7 @@ extern const fenv_t *__fe_mask_env (void) attribute_hidden; /* Set the last 2 nibbles of the FPSCR, which contain the exception enables and the rounding mode. - 'fegetenv_status' retrieves these bits by reading the FPSCR. */ + 'fegetenv_control' retrieves these bits by reading the FPSCR. */ #define fesetenv_mode(env) __builtin_mtfsf (0b00000011, (env)); /* This very handy macro: diff --git a/sysdeps/powerpc/fpu/fesetenv.c b/sysdeps/powerpc/fpu/fesetenv.c index 949d916..fc7b819 100644 --- a/sysdeps/powerpc/fpu/fesetenv.c +++ b/sysdeps/powerpc/fpu/fesetenv.c @@ -26,7 +26,7 @@ __fesetenv (const fenv_t *envp) /* get the currently set exceptions. */ new.fenv = *envp; - old.fenv = fegetenv_status (); + old.fenv = fegetenv_control (); __TEST_AND_EXIT_NON_STOP (old.l, new.l); __TEST_AND_ENTER_NON_STOP (old.l, new.l); diff --git a/sysdeps/powerpc/fpu/fesetmode.c b/sysdeps/powerpc/fpu/fesetmode.c index 90d86a9..1e9a874 100644 --- a/sysdeps/powerpc/fpu/fesetmode.c +++ b/sysdeps/powerpc/fpu/fesetmode.c @@ -27,7 +27,7 @@ fesetmode (const femode_t *modep) /* Logic regarding enabled exceptions as in fesetenv. */ new.fenv = *modep; - old.fenv = fegetenv_status (); + old.fenv = fegetenv_control (); new.l = (new.l & ~FPSCR_STATUS_MASK) | (old.l & FPSCR_STATUS_MASK); if (old.l == new.l) From patchwork Thu Sep 19 19:14:56 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Paul A. Clarke" X-Patchwork-Id: 1164804 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=sourceware.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=libc-alpha-return-105271-incoming=patchwork.ozlabs.org@sourceware.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=us.ibm.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; secure) header.d=sourceware.org header.i=@sourceware.org header.b="PA2GEZ5V"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 46Z64z6ghTz9sNf for ; Fri, 20 Sep 2019 05:15:47 +1000 (AEST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=sourceware.org; h=list-id :list-unsubscribe:list-subscribe:list-archive:list-post :list-help:sender:from:to:cc:subject:date:message-id:in-reply-to :references; q=dns; s=default; b=ZUBQ0tVKnUVIT2m6YchOc0Jt4ZfogZr YrhIxaU8UyqHq8+R1hbBqQpOb1RCFErmW82Syhch9csNCsA6cIlcHnBNhNLEyz9W F7TO+FndP/wnwQCseFAuqAeYAqaAdxkNuWRZ8SLsrXmjTJMpM6A87wyUfSYOM/sm sLSvpzO2uc9A= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=sourceware.org; h=list-id :list-unsubscribe:list-subscribe:list-archive:list-post :list-help:sender:from:to:cc:subject:date:message-id:in-reply-to :references; s=default; bh=g/2Xp3CCZzbAao+zZLMS23zQcjI=; b=PA2GE Z5VIfrwx9zlv6UpsHx8ZQrVcjOYMhM13dvMjYZVjYFWv4o2oMjsqABEHzwf3evp4 RdXGABH27HhtFZnm0W7EaAeGyM3PQmBCA3a+1vz3Y5SedBidirMl9pOFe4e1Ue3H wiGlIXGH6CeDnFCAt8IXZCiQXy5js4uv6uHRWc= Received: (qmail 66031 invoked by alias); 19 Sep 2019 19:15:40 -0000 Mailing-List: contact libc-alpha-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: libc-alpha-owner@sourceware.org Delivered-To: mailing list libc-alpha@sourceware.org Received: (qmail 65782 invoked by uid 89); 19 Sep 2019 19:15:22 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-27.0 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.1 spammy= X-HELO: mx0a-001b2d01.pphosted.com From: "Paul A. Clarke" To: libc-alpha@sourceware.org Cc: tuliom@ascii.art.br, murphyp@linux.ibm.com Subject: [PATCH v2 7/6] [powerpc] Rename fesetenv_mode to fesetenv_control Date: Thu, 19 Sep 2019 14:14:56 -0500 Message-Id: <1568920496-26685-1-git-send-email-pc@us.ibm.com> In-Reply-To: <1568918810-20393-1-git-send-email-pc@us.ibm.com> References: <1568918810-20393-1-git-send-email-pc@us.ibm.com> From: "Paul A. Clarke" fesetenv_mode is used variously to write the FPSCR exception enable bits and rounding mode bits. These are referred to as the control bits in the POWER ISA. Change the name to be reflective of its current and expected use, and match up well with fegetenv_control. 2019-09-19 Paul A. Clarke * sysdeps/powerpc/fpu/fenv_libc.h (fesetenv_mode): Rename to fesetenv_control. * sysdeps/powerpc/fpu/fedisblxcpt.c (fedisableexcept): Accommodate rename of fesetenv_mode to fegetenv_control. * sysdeps/powerpc/fpu/feenablxcpt.c (feenableexcept): Likewise. * sysdeps/powerpc/fpu/fesetmode.c (fesetmode): Likewise. * sysdeps/powerpc/fpu/fenv_private.h (__libc_femergeenv_ppc): Likewise. (libc_feholdsetround_noex_ppc_ctx): Likewise. Reviewed-By: Paul E Murphy --- This patch should've been tacked onto the series that I just posted "[PATCH v2 0/6] Various FPSCR-related changes", thus the "7/6". :-? This is a new patch. sysdeps/powerpc/fpu/fedisblxcpt.c | 2 +- sysdeps/powerpc/fpu/feenablxcpt.c | 2 +- sysdeps/powerpc/fpu/fenv_libc.h | 2 +- sysdeps/powerpc/fpu/fenv_private.h | 4 ++-- sysdeps/powerpc/fpu/fesetmode.c | 2 +- 5 files changed, 6 insertions(+), 6 deletions(-) diff --git a/sysdeps/powerpc/fpu/fedisblxcpt.c b/sysdeps/powerpc/fpu/fedisblxcpt.c index 870cfc8..9f86c5f 100644 --- a/sysdeps/powerpc/fpu/fedisblxcpt.c +++ b/sysdeps/powerpc/fpu/fedisblxcpt.c @@ -41,7 +41,7 @@ fedisableexcept (int excepts) fe.l &= ~new; if (fe.l != curr.l) - fesetenv_mode (fe.fenv); + fesetenv_control (fe.fenv); __TEST_AND_ENTER_NON_STOP (-1ULL, fe.l); diff --git a/sysdeps/powerpc/fpu/feenablxcpt.c b/sysdeps/powerpc/fpu/feenablxcpt.c index 43f6482..141cfb4 100644 --- a/sysdeps/powerpc/fpu/feenablxcpt.c +++ b/sysdeps/powerpc/fpu/feenablxcpt.c @@ -41,7 +41,7 @@ feenableexcept (int excepts) fe.l |= new; if (fe.l != curr.l) - fesetenv_mode (fe.fenv); + fesetenv_control (fe.fenv); __TEST_AND_EXIT_NON_STOP (0ULL, fe.l); diff --git a/sysdeps/powerpc/fpu/fenv_libc.h b/sysdeps/powerpc/fpu/fenv_libc.h index 231d264..ed6cfeb 100644 --- a/sysdeps/powerpc/fpu/fenv_libc.h +++ b/sysdeps/powerpc/fpu/fenv_libc.h @@ -124,7 +124,7 @@ extern const fenv_t *__fe_mask_env (void) attribute_hidden; /* Set the last 2 nibbles of the FPSCR, which contain the exception enables and the rounding mode. 'fegetenv_control' retrieves these bits by reading the FPSCR. */ -#define fesetenv_mode(env) __builtin_mtfsf (0b00000011, (env)); +#define fesetenv_control(env) __builtin_mtfsf (0b00000011, (env)); /* This very handy macro: - Sets the rounding mode to 'round to nearest'; diff --git a/sysdeps/powerpc/fpu/fenv_private.h b/sysdeps/powerpc/fpu/fenv_private.h index ade0bfa..5eedc3b 100644 --- a/sysdeps/powerpc/fpu/fenv_private.h +++ b/sysdeps/powerpc/fpu/fenv_private.h @@ -61,7 +61,7 @@ __libc_femergeenv_ppc (const fenv_t *envp, unsigned long long old_mask, == (FPSCR_CONTROL_MASK|FPSCR_EXCEPTIONS_MASK) && (old.l & FPSCR_EXCEPTIONS_MASK) == (new.l & FPSCR_EXCEPTIONS_MASK)) { - fesetenv_mode (new.fenv); + fesetenv_control (new.fenv); } else /* Atomically enable and raise (if appropriate) exceptions set in `new'. */ @@ -142,7 +142,7 @@ libc_feholdsetround_noex_ppc_ctx (struct rm_ctx *ctx, int r) if (__glibc_unlikely (new.l != old.l)) { __TEST_AND_ENTER_NON_STOP (old.l, 0ULL); - fesetenv_mode (new.fenv); + fesetenv_control (new.fenv); ctx->updated_status = true; } else diff --git a/sysdeps/powerpc/fpu/fesetmode.c b/sysdeps/powerpc/fpu/fesetmode.c index 1e9a874..a7ead9f 100644 --- a/sysdeps/powerpc/fpu/fesetmode.c +++ b/sysdeps/powerpc/fpu/fesetmode.c @@ -36,6 +36,6 @@ fesetmode (const femode_t *modep) __TEST_AND_EXIT_NON_STOP (old.l, new.l); __TEST_AND_ENTER_NON_STOP (old.l, new.l); - fesetenv_mode (new.fenv); + fesetenv_control (new.fenv); return 0; }