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[36.228.113.219]) by smtp.gmail.com with ESMTPSA id u31sm25491414pgn.93.2019.09.19.00.28.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 Sep 2019 00:28:05 -0700 (PDT) From: Green Wan Cc: linux-hackers@sifive.com, Green Wan , Vinod Koul , Rob Herring , Mark Rutland , Paul Walmsley , Palmer Dabbelt , Mauro Carvalho Chehab , "David S. Miller" , Greg Kroah-Hartman , Linus Walleij , Nicolas Ferre , "Paul E. McKenney" , dmaengine@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 1/3] dt-bindings: dmaengine: sf-pdma: add bindins for SiFive PDMA Date: Thu, 19 Sep 2019 15:27:26 +0800 Message-Id: <20190919072756.1973-1-green.wan@sifive.com> X-Mailer: git-send-email 2.17.1 To: unlisted-recipients:; (no To-header on input) Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Add DT bindings document for Platform DMA(PDMA) driver of board, HiFive Unleashed Rev A00. Signed-off-by: Green Wan --- .../bindings/dma/sifive,fu540-c000-pdma.yaml | 63 +++++++++++++++++++ MAINTAINERS | 5 ++ 2 files changed, 68 insertions(+) create mode 100644 Documentation/devicetree/bindings/dma/sifive,fu540-c000-pdma.yaml diff --git a/Documentation/devicetree/bindings/dma/sifive,fu540-c000-pdma.yaml b/Documentation/devicetree/bindings/dma/sifive,fu540-c000-pdma.yaml new file mode 100644 index 000000000000..b5423f1cfcaf --- /dev/null +++ b/Documentation/devicetree/bindings/dma/sifive,fu540-c000-pdma.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/dma/sifive,fu540-c000-pdma.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SiFive Unleashed Rev C000 Platform DMA + +maintainers: + - Green Wan + - Palmer Debbelt + - Paul Walmsley + +description: | + Platform DMA is a DMA engine of SiFive Unleashed. It supports 4 + channels. Each channel has 2 interrupts. One is for DMA done and + the other is for DME error. + + In different SoC, DMA could be attached to different IRQ line. + DT file need to be changed to meet the difference. For technical + doc, + + https://static.dev.sifive.com/FU540-C000-v1.0.pdf + +properties: + compatible: + items: + - const: sifive,fu540-c000-pdma + + reg: + maxItems: 1 + + interrupts: + minItems: 8 + maxItems: 8 + + interrupt-parent: + description: + Interrupt parent must correspond to the name PLIC interrupt + controller, i.e. "plic0" + maxItems: 1 + + '#dma-cells': + const: 1 + +required: + - compatible + - reg + - interrupt-parent + - interrupts + - '#dma-cells' + +examples: + - | + dma@3000000 { + compatible = "sifive,fu540-c000-pdma"; + reg = <0x0 0x3000000 0x0 0x8000>; + interrupt-parent = <&plic0>; + interrupts = <23 24 25 26 27 28 29 30>; + #dma-cells = <1>; + }; + +... diff --git a/MAINTAINERS b/MAINTAINERS index 49f75d1b7b51..d0caa09a479e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -14591,6 +14591,11 @@ F: drivers/media/usb/siano/ F: drivers/media/usb/siano/ F: drivers/media/mmc/siano/ +SIFIVE PDMA DRIVER +M: Green Wan +S: Maintained +F: Documentation/devicetree/bindings/dma/sifive,fu540-c000-pdma.yaml + SIFIVE DRIVERS M: Palmer Dabbelt M: Paul Walmsley