From patchwork Thu Sep 19 06:43:51 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Kito Cheng X-Patchwork-Id: 1164382 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-509248-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="mb8apU2B"; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="ILc7cYBT"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 46YnPs6snFz9sN1 for ; Thu, 19 Sep 2019 16:44:15 +1000 (AEST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:from:date:message-id:subject:to:content-type; q= dns; s=default; b=gYshUVo/s3qpKHHw2LFkoPugqn940vSMKlmGaFFEvt6hGe 5bgjlFDfjUfEj5Kw8aO8J8zBxiR7T6FjrgPUVR1bPm+NUDmXfpku/24wpfWEsjzG ytpEWd2wa/oxj2E03XxU66qNfZIgmmPH1bPUxjaPQZCj9RU1rmumg8uPWuMnc= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:from:date:message-id:subject:to:content-type; s= default; bh=V79v62+aABKHaozrlXRgCK3uIRY=; b=mb8apU2BWKjrrcPXihlk 0HBedy2GuK1MFMDKtTtWJMM20WKhnmCgzXvBut5+o2SclYiWSaPTY/isxsxOnT87 kkcCdvE27zNGoLyphCJM3NZaMHPYwc1vtkX8d07z+bbQrP7SuH4Ptl9MvEWElT2+ 26inZazbAdp+aOzAoxS3+5g= Received: (qmail 130730 invoked by alias); 19 Sep 2019 06:44:07 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 130721 invoked by uid 89); 19 Sep 2019 06:44:07 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-18.9 required=5.0 tests=AWL, BAYES_00, FREEMAIL_FROM, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.1 spammy= X-HELO: mail-wm1-f49.google.com Received: from mail-wm1-f49.google.com (HELO mail-wm1-f49.google.com) (209.85.128.49) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 19 Sep 2019 06:44:05 +0000 Received: by mail-wm1-f49.google.com with SMTP id 3so2534871wmi.3 for ; Wed, 18 Sep 2019 23:44:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:from:date:message-id:subject:to; bh=uLW9e1IJ09NMQpK4Gy/B8vCT6dPUC8wgMWZhDGaDR3Y=; b=ILc7cYBTi/B9je6Xlp+s7AsEbBP2R1VjRY5n4Gh7Cj/w2xYbVBfEZomJRkRIH0X3Ok prFbd8h+KXInIRaWyViutY2kD7lYaGHq4ut7uIPFa4PFLqZUQBbVFYolMXip8KoTWly6 wZ42QAJJPEHtVwWe0Tu8oIicsbE+r9JxtNv3rkUvD2Ov50e58EHLieLI2XLuViOVeQ6W kWEBMzqGO2kNHvsRtnQBq0992y9vWKijoV5N+/f+E4BG3Rh+BM0RyHT2nmaZZ0XAtmG1 60TH0hDPAZp7P6fKRt4cteNfOilc6sDkJ2W5Y+6NzF7nl5EW6lyF+vF1K7N0mpi4tjPn kyCw== MIME-Version: 1.0 From: Kito Cheng Date: Thu, 19 Sep 2019 14:43:51 +0800 Message-ID: Subject: [COMMITTED][GCC9] Backport RISC-V: Fix bad insn splits with paradoxical subregs. To: GCC Patches , Jim Wilson X-IsSubscribed: yes This patch fix PR target/91635, fixing wrong code gen for RISC-V. From 52e32e2f82b4fe09c253e230c4fe321a0341aae7 Mon Sep 17 00:00:00 2001 From: kito Date: Thu, 19 Sep 2019 06:38:23 +0000 Subject: [PATCH] RISC-V: Fix bad insn splits with paradoxical subregs. Shifting by more than the size of a SUBREG_REG doesn't work, so we either need to disable splits if an input is paradoxical, or else we need to generate a clean temporary for intermediate results. Jakub wrote the first version of this patch, so gets primary credit for it. gcc/ PR target/91635 * config/riscv/riscv.md (zero_extendsidi2, zero_extendhi2, extend2): Don't split if paradoxical_subreg_p (operands[0]). (*lshrsi3_zero_extend_3+1, *lshrsi3_zero_extend_3+2): Add clobber and use as intermediate value. gcc/testsuite/ PR target/91635 * gcc.c-torture/execute/pr91635.c: New test. * gcc.target/riscv/shift-shift-4.c: New test. * gcc.target/riscv/shift-shift-5.c: New test. git-svn-id: svn+ssh://gcc.gnu.org/svn/gcc/branches/gcc-9-branch@275929 138bc75d-0d04-0410-961f-82ee72b054a4 --- gcc/ChangeLog | 13 +++++ gcc/config/riscv/riscv.md | 30 +++++++--- gcc/testsuite/ChangeLog | 11 ++++ gcc/testsuite/gcc.c-torture/execute/pr91635.c | 57 +++++++++++++++++++ .../gcc.target/riscv/shift-shift-4.c | 13 +++++ .../gcc.target/riscv/shift-shift-5.c | 16 ++++++ 6 files changed, 131 insertions(+), 9 deletions(-) create mode 100644 gcc/testsuite/gcc.c-torture/execute/pr91635.c create mode 100644 gcc/testsuite/gcc.target/riscv/shift-shift-4.c create mode 100644 gcc/testsuite/gcc.target/riscv/shift-shift-5.c diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 95f978d5805..aa90ce5df7b 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,16 @@ +2019-09-19 Kito Cheng + + Backport from mainline + 2019-09-05 Jakub Jelinek + Jim Wilson + + PR target/91635 + * config/riscv/riscv.md (zero_extendsidi2, zero_extendhi2, + extend2): Don't split if + paradoxical_subreg_p (operands[0]). + (*lshrsi3_zero_extend_3+1, *lshrsi3_zero_extend_3+2): Add clobber and + use as intermediate value. + 2019-09-11 Eric Botcazou PR rtl-optimization/89795 diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md index a8bac170e72..7850c41f3c7 100644 --- a/gcc/config/riscv/riscv.md +++ b/gcc/config/riscv/riscv.md @@ -1051,7 +1051,9 @@ "@ # lwu\t%0,%1" - "&& reload_completed && REG_P (operands[1])" + "&& reload_completed + && REG_P (operands[1]) + && !paradoxical_subreg_p (operands[0])" [(set (match_dup 0) (ashift:DI (match_dup 1) (const_int 32))) (set (match_dup 0) @@ -1068,7 +1070,9 @@ "@ # lhu\t%0,%1" - "&& reload_completed && REG_P (operands[1])" + "&& reload_completed + && REG_P (operands[1]) + && !paradoxical_subreg_p (operands[0])" [(set (match_dup 0) (ashift:GPR (match_dup 1) (match_dup 2))) (set (match_dup 0) @@ -1117,7 +1121,9 @@ "@ # l\t%0,%1" - "&& reload_completed && REG_P (operands[1])" + "&& reload_completed + && REG_P (operands[1]) + && !paradoxical_subreg_p (operands[0])" [(set (match_dup 0) (ashift:SI (match_dup 1) (match_dup 2))) (set (match_dup 0) (ashiftrt:SI (match_dup 0) (match_dup 2)))] { @@ -1765,15 +1771,20 @@ ;; Handle AND with 2^N-1 for N from 12 to XLEN. This can be split into ;; two logical shifts. Otherwise it requires 3 instructions: lui, ;; xor/addi/srli, and. + +;; Generating a temporary for the shift output gives better combiner results; +;; and also fixes a problem where op0 could be a paradoxical reg and shifting +;; by amounts larger than the size of the SUBREG_REG doesn't work. (define_split [(set (match_operand:GPR 0 "register_operand") (and:GPR (match_operand:GPR 1 "register_operand") - (match_operand:GPR 2 "p2m1_shift_operand")))] + (match_operand:GPR 2 "p2m1_shift_operand"))) + (clobber (match_operand:GPR 3 "register_operand"))] "" - [(set (match_dup 0) + [(set (match_dup 3) (ashift:GPR (match_dup 1) (match_dup 2))) (set (match_dup 0) - (lshiftrt:GPR (match_dup 0) (match_dup 2)))] + (lshiftrt:GPR (match_dup 3) (match_dup 2)))] { /* Op2 is a VOIDmode constant, so get the mode size from op1. */ operands[2] = GEN_INT (GET_MODE_BITSIZE (GET_MODE (operands[1])) @@ -1785,12 +1796,13 @@ (define_split [(set (match_operand:DI 0 "register_operand") (and:DI (match_operand:DI 1 "register_operand") - (match_operand:DI 2 "high_mask_shift_operand")))] + (match_operand:DI 2 "high_mask_shift_operand"))) + (clobber (match_operand:DI 3 "register_operand"))] "TARGET_64BIT" - [(set (match_dup 0) + [(set (match_dup 3) (lshiftrt:DI (match_dup 1) (match_dup 2))) (set (match_dup 0) - (ashift:DI (match_dup 0) (match_dup 2)))] + (ashift:DI (match_dup 3) (match_dup 2)))] { operands[2] = GEN_INT (ctz_hwi (INTVAL (operands[2]))); }) diff --git a/gcc/testsuite/ChangeLog b/gcc/testsuite/ChangeLog index cd500d0b1c7..2c6127fa526 100644 --- a/gcc/testsuite/ChangeLog +++ b/gcc/testsuite/ChangeLog @@ -1,3 +1,14 @@ +2019-09-19 Kito Cheng + + Backport from mainline + 2019-09-05 Jakub Jelinek + Jim Wilson + + PR target/91635 + * gcc.c-torture/execute/pr91635.c: New test. + * gcc.target/riscv/shift-shift-4.c: New test. + * gcc.target/riscv/shift-shift-5.c: New test. + 2019-09-18 Thomas Koenig Backport from trunk diff --git a/gcc/testsuite/gcc.c-torture/execute/pr91635.c b/gcc/testsuite/gcc.c-torture/execute/pr91635.c new file mode 100644 index 00000000000..878a491fc36 --- /dev/null +++ b/gcc/testsuite/gcc.c-torture/execute/pr91635.c @@ -0,0 +1,57 @@ +/* PR target/91635 */ + +#if __CHAR_BIT__ == 8 && __SIZEOF_SHORT__ == 2 \ + && __SIZEOF_INT__ == 4 && __SIZEOF_LONG_LONG__ == 8 +unsigned short b, c; +int u, v, w, x; + +__attribute__ ((noipa)) int +foo (unsigned short c) +{ + c <<= __builtin_add_overflow (-c, -1, &b); + c >>= 1; + return c; +} + +__attribute__ ((noipa)) int +bar (unsigned short b) +{ + b <<= -14 & 15; + b = b >> -~1; + return b; +} + +__attribute__ ((noipa)) int +baz (unsigned short e) +{ + e <<= 1; + e >>= __builtin_add_overflow (8719476735, u, &v); + return e; +} + +__attribute__ ((noipa)) int +qux (unsigned int e) +{ + c = ~1; + c *= e; + c = c >> (-15 & 5); + return c + w + x; +} +#endif + +int +main () +{ +#if __CHAR_BIT__ == 8 && __SIZEOF_SHORT__ == 2 \ + && __SIZEOF_INT__ == 4 && __SIZEOF_LONG_LONG__ == 8 + if (foo (0xffff) != 0x7fff) + __builtin_abort (); + if (bar (5) != 5) + __builtin_abort (); + if (baz (~0) != 0x7fff) + __builtin_abort (); + if (qux (2) != 0x7ffe) + __builtin_abort (); +#endif + return 0; +} diff --git a/gcc/testsuite/gcc.target/riscv/shift-shift-4.c b/gcc/testsuite/gcc.target/riscv/shift-shift-4.c new file mode 100644 index 00000000000..72a45ee87ae --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/shift-shift-4.c @@ -0,0 +1,13 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv32i -mabi=ilp32 -O2" } */ + +/* One zero-extend shift can be eliminated by modifying the constant in the + greater than test. Started working after modifying the splitter + lshrsi3_zero_extend_3+1 to use a temporary reg for the first split dest. */ +int +sub (int i) +{ + i &= 0x7fffffff; + return i > 0x7f800000; +} +/* { dg-final { scan-assembler-not "srli" } } */ diff --git a/gcc/testsuite/gcc.target/riscv/shift-shift-5.c b/gcc/testsuite/gcc.target/riscv/shift-shift-5.c new file mode 100644 index 00000000000..5b2ae89a471 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/shift-shift-5.c @@ -0,0 +1,16 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc -mabi=lp64d -O2" } */ + +/* Fails if lshrsi3_zero_extend_3+1 uses a temp reg which has no REG_DEST + note. */ +unsigned long +sub (long l) +{ + union u { + struct s { int a : 19; unsigned int b : 13; int x; } s; + long l; + } u; + u.l = l; + return u.s.b; +} +/* { dg-final { scan-assembler "srliw" } } */ -- 2.17.1