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Thu, 19 Sep 2019 00:11:40 +0000 (GMT) Date: Wed, 18 Sep 2019 20:11:39 -0400 From: Michael Meissner To: Michael Meissner , gcc-patches@gcc.gnu.org, segher@kernel.crashing.org, dje.gcc@gmail.com Subject: [PATCH] V4, patch #6: Use PLI (PADDI) to load up 32-bit SImode constants Message-ID: <20190919001139.GF28484@ibm-toto.the-meissners.org> Mail-Followup-To: Michael Meissner , gcc-patches@gcc.gnu.org, segher@kernel.crashing.org, dje.gcc@gmail.com References: <20190918234214.GA27521@ibm-toto.the-meissners.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20190918234214.GA27521@ibm-toto.the-meissners.org> User-Agent: Mutt/1.5.21 (2010-09-15) This patch is similar to the previous patch, except it loads up 32-bit SImode constants instead of DImode constants. I have done a bootstrap build with all of the patches applied, and there were no regressions in the test suite. After posting these patches, I will start a job to build each set of patches in turn just to make sure there are no extra warnings. Can I commit this patch to the trunk? 2019-09-18 Michael Meissner * config/rs6000/rs6000.md (movsi_internal1): Add support to load up 32-bit SImode integer constants with PADDI. (movsi integer constant splitter): Do not split constant if PADDI can load it up directly. Index: gcc/config/rs6000/rs6000.md =================================================================== --- gcc/config/rs6000/rs6000.md (revision 275912) +++ gcc/config/rs6000/rs6000.md (working copy) @@ -6908,22 +6908,22 @@ (define_insn "movsi_low" ;; MR LA LWZ LFIWZX LXSIWZX ;; STW STFIWX STXSIWX LI LIS -;; # XXLOR XXSPLTIB 0 XXSPLTIB -1 VSPLTISW -;; XXLXOR 0 XXLORC -1 P9 const MTVSRWZ MFVSRWZ -;; MF%1 MT%0 NOP +;; PLI # XXLOR XXSPLTIB 0 XXSPLTIB -1 +;; VSPLTISW XXLXOR 0 XXLORC -1 P9 const MTVSRWZ +;; MFVSRWZ MF%1 MT%0 NOP (define_insn "*movsi_internal1" [(set (match_operand:SI 0 "nonimmediate_operand" "=r, r, r, d, v, m, Z, Z, r, r, - r, wa, wa, wa, v, - wa, v, v, wa, r, - r, *h, *h") + r, r, wa, wa, wa, + v, wa, v, v, wa, + r, r, *h, *h") (match_operand:SI 1 "input_operand" "r, U, m, Z, Z, r, d, v, I, L, - n, wa, O, wM, wB, - O, wM, wS, r, wa, - *h, r, 0"))] + eI, n, wa, O, wM, + wB, O, wM, wS, r, + wa, *h, r, 0"))] "gpc_reg_operand (operands[0], SImode) || gpc_reg_operand (operands[1], SImode)" "@ @@ -6937,6 +6937,7 @@ (define_insn "*movsi_internal1" stxsiwx %x1,%y0 li %0,%1 lis %0,%v1 + li %0,%1 # xxlor %x0,%x1,%x1 xxspltib %x0,0 @@ -6953,21 +6954,21 @@ (define_insn "*movsi_internal1" [(set_attr "type" "*, *, load, fpload, fpload, store, fpstore, fpstore, *, *, - *, veclogical, vecsimple, vecsimple, vecsimple, - veclogical, veclogical, vecsimple, mffgpr, mftgpr, - *, *, *") + *, *, veclogical, vecsimple, vecsimple, + vecsimple, veclogical, veclogical, vecsimple, mffgpr, + mftgpr, *, *, *") (set_attr "length" "*, *, *, *, *, *, *, *, *, *, - 8, *, *, *, *, - *, *, 8, *, *, - *, *, *") + *, 8, *, *, *, + *, *, *, 8, *, + *, *, *, *") (set_attr "isa" "*, *, *, p8v, p8v, *, p8v, p8v, *, *, - *, p8v, p9v, p9v, p8v, - p9v, p8v, p9v, p8v, p8v, - *, *, *")]) + fut, *, p8v, p9v, p9v, + p8v, p9v, p8v, p9v, p8v, + p8v, *, *, *")]) ;; Like movsi, but adjust a SF value to be used in a SI context, i.e. ;; (set (reg:SI ...) (subreg:SI (reg:SF ...) 0)) @@ -7112,14 +7113,15 @@ (define_insn "*movsi_from_df" "xscvdpsp %x0,%x1" [(set_attr "type" "fp")]) -;; Split a load of a large constant into the appropriate two-insn -;; sequence. +;; Split a load of a large constant into the appropriate two-insn sequence. On +;; systems that support PADDI (PLI), we can use PLI to load any 32-bit constant +;; in one instruction. (define_split [(set (match_operand:SI 0 "gpc_reg_operand") (match_operand:SI 1 "const_int_operand"))] "(unsigned HOST_WIDE_INT) (INTVAL (operands[1]) + 0x8000) >= 0x10000 - && (INTVAL (operands[1]) & 0xffff) != 0" + && (INTVAL (operands[1]) & 0xffff) != 0 && !TARGET_PREFIXED_ADDR" [(set (match_dup 0) (match_dup 2)) (set (match_dup 0)