From patchwork Tue Sep 10 15:41:47 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Beckett X-Patchwork-Id: 1160418 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=collabora.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 46STnv6dNXz9s4Y for ; Wed, 11 Sep 2019 01:43:15 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2393142AbfIJPnP (ORCPT ); Tue, 10 Sep 2019 11:43:15 -0400 Received: from bhuna.collabora.co.uk ([46.235.227.227]:43742 "EHLO bhuna.collabora.co.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726664AbfIJPnP (ORCPT ); Tue, 10 Sep 2019 11:43:15 -0400 Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: bbeckett) with ESMTPSA id 9FFAA28D91B From: Robert Beckett To: netdev@vger.kernel.org Cc: Robert Beckett , Andrew Lunn , Vivien Didelot , Florian Fainelli , "David S. Miller" Subject: [PATCH 1/7] net/dsa: configure autoneg for CPU port Date: Tue, 10 Sep 2019 16:41:47 +0100 Message-Id: <20190910154238.9155-2-bob.beckett@collabora.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20190910154238.9155-1-bob.beckett@collabora.com> References: <20190910154238.9155-1-bob.beckett@collabora.com> Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Configure autoneg for phy connected CPU ports. This allows us to use autoneg between the CPU port's phy and the link partner's phy. This enables us to negoatiate pause frame transmission to prioritise packet delivery over throughput. Signed-off-by: Robert Beckett --- net/dsa/port.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/net/dsa/port.c b/net/dsa/port.c index f071acf2842b..1b6832eac2c5 100644 --- a/net/dsa/port.c +++ b/net/dsa/port.c @@ -538,10 +538,20 @@ static int dsa_port_setup_phy_of(struct dsa_port *dp, bool enable) return PTR_ERR(phydev); if (enable) { + phydev->supported = PHY_GBIT_FEATURES | SUPPORTED_MII | + SUPPORTED_AUI | SUPPORTED_FIBRE | + SUPPORTED_BNC | SUPPORTED_Pause | + SUPPORTED_Asym_Pause; + phydev->advertising = phydev->supported; + err = genphy_config_init(phydev); if (err < 0) goto err_put_dev; + err = genphy_config_aneg(phydev); + if (err < 0) + goto err_put_dev; + err = genphy_resume(phydev); if (err < 0) goto err_put_dev; From patchwork Tue Sep 10 15:41:48 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Beckett X-Patchwork-Id: 1160419 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=collabora.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 46STp24sgXz9s4Y for ; Wed, 11 Sep 2019 01:43:22 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2393957AbfIJPnV (ORCPT ); Tue, 10 Sep 2019 11:43:21 -0400 Received: from bhuna.collabora.co.uk ([46.235.227.227]:43750 "EHLO bhuna.collabora.co.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726664AbfIJPnV (ORCPT ); Tue, 10 Sep 2019 11:43:21 -0400 Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: bbeckett) with ESMTPSA id 175B828D91B From: Robert Beckett To: netdev@vger.kernel.org Cc: Robert Beckett , Andrew Lunn , Vivien Didelot , Florian Fainelli , "David S. Miller" Subject: [PATCH 2/7] net: dsa: mv88e6xxx: add ability to set default queue priorities per port Date: Tue, 10 Sep 2019 16:41:48 +0100 Message-Id: <20190910154238.9155-3-bob.beckett@collabora.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20190910154238.9155-1-bob.beckett@collabora.com> References: <20190910154238.9155-1-bob.beckett@collabora.com> Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Add code to set DefQPri for any port that specifies "defqpri" in their device tree node. This allows setting the default output queue priority for all packets entering the switch via the port that uses this, which is useful for prioritizing traffic based on port. Signed-off-by: Robert Beckett --- drivers/net/dsa/mv88e6xxx/chip.c | 25 +++++++++++++++++++++++++ drivers/net/dsa/mv88e6xxx/chip.h | 1 + drivers/net/dsa/mv88e6xxx/port.c | 19 +++++++++++++++++++ drivers/net/dsa/mv88e6xxx/port.h | 4 ++++ 4 files changed, 49 insertions(+) diff --git a/drivers/net/dsa/mv88e6xxx/chip.c b/drivers/net/dsa/mv88e6xxx/chip.c index d0a97eb73a37..5005a35493e3 100644 --- a/drivers/net/dsa/mv88e6xxx/chip.c +++ b/drivers/net/dsa/mv88e6xxx/chip.c @@ -2086,6 +2086,23 @@ static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port) return 0; } +static int mv88e6xxx_set_port_defqpri(struct mv88e6xxx_chip *chip, int port) +{ + struct dsa_switch *ds = chip->ds; + struct device_node *dn = ds->ports[port].dn; + int err; + u32 pri; + + if (!dn || !chip->info->ops->port_set_defqpri) + return 0; + + err = of_property_read_u32(dn, "defqpri", &pri); + if (err < 0) + return 0; + + return chip->info->ops->port_set_defqpri(chip, port, (u16)pri); +} + static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port) { struct dsa_switch *ds = chip->ds; @@ -2176,6 +2193,10 @@ static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port) return err; } + err = mv88e6xxx_set_port_defqpri(chip, port); + if (err) + return err; + /* Port Association Vector: when learning source addresses * of packets, add the address to the address database using * a port bitmap that has only the bit for this port set and @@ -3107,6 +3128,7 @@ static const struct mv88e6xxx_ops mv88e6172_ops = { .port_set_egress_floods = mv88e6352_port_set_egress_floods, .port_set_ether_type = mv88e6351_port_set_ether_type, .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, + .port_set_defqpri = mv88e6xxx_port_set_defqpri, .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, .port_pause_limit = mv88e6097_port_pause_limit, .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, @@ -3190,6 +3212,7 @@ static const struct mv88e6xxx_ops mv88e6176_ops = { .port_set_egress_floods = mv88e6352_port_set_egress_floods, .port_set_ether_type = mv88e6351_port_set_ether_type, .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, + .port_set_defqpri = mv88e6xxx_port_set_defqpri, .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, .port_pause_limit = mv88e6097_port_pause_limit, .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, @@ -3407,6 +3430,7 @@ static const struct mv88e6xxx_ops mv88e6240_ops = { .port_set_egress_floods = mv88e6352_port_set_egress_floods, .port_set_ether_type = mv88e6351_port_set_ether_type, .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, + .port_set_defqpri = mv88e6xxx_port_set_defqpri, .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, .port_pause_limit = mv88e6097_port_pause_limit, .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, @@ -3750,6 +3774,7 @@ static const struct mv88e6xxx_ops mv88e6352_ops = { .port_set_egress_floods = mv88e6352_port_set_egress_floods, .port_set_ether_type = mv88e6351_port_set_ether_type, .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, + .port_set_defqpri = mv88e6xxx_port_set_defqpri, .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, .port_pause_limit = mv88e6097_port_pause_limit, .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, diff --git a/drivers/net/dsa/mv88e6xxx/chip.h b/drivers/net/dsa/mv88e6xxx/chip.h index 4646e46d47f2..2d2c24f5a79d 100644 --- a/drivers/net/dsa/mv88e6xxx/chip.h +++ b/drivers/net/dsa/mv88e6xxx/chip.h @@ -383,6 +383,7 @@ struct mv88e6xxx_ops { u16 etype); int (*port_set_jumbo_size)(struct mv88e6xxx_chip *chip, int port, size_t size); + int (*port_set_defqpri)(struct mv88e6xxx_chip *chip, int port, u16 pri); int (*port_egress_rate_limiting)(struct mv88e6xxx_chip *chip, int port); int (*port_pause_limit)(struct mv88e6xxx_chip *chip, int port, u8 in, diff --git a/drivers/net/dsa/mv88e6xxx/port.c b/drivers/net/dsa/mv88e6xxx/port.c index 04309ef0a1cc..3a45fcd5cd9c 100644 --- a/drivers/net/dsa/mv88e6xxx/port.c +++ b/drivers/net/dsa/mv88e6xxx/port.c @@ -1147,6 +1147,25 @@ int mv88e6165_port_set_jumbo_size(struct mv88e6xxx_chip *chip, int port, return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg); } +int mv88e6xxx_port_set_defqpri(struct mv88e6xxx_chip *chip, int port, u16 pri) +{ + u16 reg; + int err; + + if (pri > 3) + return -EINVAL; + + err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_CTL2, ®); + if (err) + return err; + + reg &= ~MV88E6XXX_PORT_CTL2_DEFQPRI_MASK; + reg |= pri << MV88E6XXX_PORT_CTL2_DEFQPRI_SHIFT; + reg |= MV88E6XXX_PORT_CTL2_USE_DEFQPRI; + + return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg); +} + /* Offset 0x09: Port Rate Control */ int mv88e6095_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port) diff --git a/drivers/net/dsa/mv88e6xxx/port.h b/drivers/net/dsa/mv88e6xxx/port.h index 8d5a6cd6fb19..03884bbaa762 100644 --- a/drivers/net/dsa/mv88e6xxx/port.h +++ b/drivers/net/dsa/mv88e6xxx/port.h @@ -197,6 +197,9 @@ #define MV88E6XXX_PORT_CTL2_DEFAULT_FORWARD 0x0040 #define MV88E6XXX_PORT_CTL2_EGRESS_MONITOR 0x0020 #define MV88E6XXX_PORT_CTL2_INGRESS_MONITOR 0x0010 +#define MV88E6XXX_PORT_CTL2_USE_DEFQPRI 0x0008 +#define MV88E6XXX_PORT_CTL2_DEFQPRI_MASK 0x0006 +#define MV88E6XXX_PORT_CTL2_DEFQPRI_SHIFT 1 #define MV88E6095_PORT_CTL2_CPU_PORT_MASK 0x000f /* Offset 0x09: Egress Rate Control */ @@ -326,6 +329,7 @@ int mv88e6xxx_port_set_message_port(struct mv88e6xxx_chip *chip, int port, bool message_port); int mv88e6165_port_set_jumbo_size(struct mv88e6xxx_chip *chip, int port, size_t size); +int mv88e6xxx_port_set_defqpri(struct mv88e6xxx_chip *chip, int port, u16 pri); int mv88e6095_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port); int mv88e6097_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port); int mv88e6097_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in, From patchwork Tue Sep 10 15:41:49 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Beckett X-Patchwork-Id: 1160422 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=collabora.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 46STqC2y42z9s4Y for ; Wed, 11 Sep 2019 01:44:23 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2393986AbfIJPoW (ORCPT ); Tue, 10 Sep 2019 11:44:22 -0400 Received: from bhuna.collabora.co.uk ([46.235.227.227]:43794 "EHLO bhuna.collabora.co.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726664AbfIJPoW (ORCPT ); Tue, 10 Sep 2019 11:44:22 -0400 Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: bbeckett) with ESMTPSA id F327228DA1D From: Robert Beckett To: netdev@vger.kernel.org Cc: Robert Beckett , Andrew Lunn , Vivien Didelot , Florian Fainelli , "David S. Miller" , Rob Herring , Mark Rutland , devicetree@vger.kernel.org Subject: [PATCH 3/7] dt-bindings: mv88e6xxx: add ability to set default queue priorities per port Date: Tue, 10 Sep 2019 16:41:49 +0100 Message-Id: <20190910154238.9155-4-bob.beckett@collabora.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20190910154238.9155-1-bob.beckett@collabora.com> References: <20190910154238.9155-1-bob.beckett@collabora.com> Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Document a new setting for Marvell switch chips to set the default queue priorities per port. Signed-off-by: Robert Beckett --- Documentation/devicetree/bindings/net/dsa/marvell.txt | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/net/dsa/marvell.txt b/Documentation/devicetree/bindings/net/dsa/marvell.txt index 6f9538974bb9..e097c3c52eac 100644 --- a/Documentation/devicetree/bindings/net/dsa/marvell.txt +++ b/Documentation/devicetree/bindings/net/dsa/marvell.txt @@ -47,6 +47,10 @@ Optional properties: bus. The node must contains a compatible string of "marvell,mv88e6xxx-mdio-external" +Optional properties for ports: +- defqpri= : Enforced default queue priority for the given port. + Valid range is 0..3 + Example: mdio { From patchwork Tue Sep 10 15:41:50 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Beckett X-Patchwork-Id: 1160424 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=collabora.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 46STqP4lmGz9s4Y for ; Wed, 11 Sep 2019 01:44:33 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2394003AbfIJPoc (ORCPT ); Tue, 10 Sep 2019 11:44:32 -0400 Received: from bhuna.collabora.co.uk ([46.235.227.227]:43804 "EHLO bhuna.collabora.co.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726664AbfIJPoc (ORCPT ); Tue, 10 Sep 2019 11:44:32 -0400 Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: bbeckett) with ESMTPSA id BB6D328DA1D From: Robert Beckett To: netdev@vger.kernel.org Cc: Robert Beckett , Andrew Lunn , Vivien Didelot , Florian Fainelli , "David S. Miller" Subject: [PATCH 4/7] net: dsa: mv88e6xxx: add ability to set queue scheduling Date: Tue, 10 Sep 2019 16:41:50 +0100 Message-Id: <20190910154238.9155-5-bob.beckett@collabora.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20190910154238.9155-1-bob.beckett@collabora.com> References: <20190910154238.9155-1-bob.beckett@collabora.com> Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Add code to set Schedule for any port that specifies "schedule" in their device tree node. This allows port prioritization in conjunction with port default queue priorities or packet priorities. Signed-off-by: Robert Beckett --- drivers/net/dsa/mv88e6xxx/chip.c | 25 +++++++++++++++++++++++++ drivers/net/dsa/mv88e6xxx/chip.h | 1 + drivers/net/dsa/mv88e6xxx/port.c | 21 +++++++++++++++++++++ drivers/net/dsa/mv88e6xxx/port.h | 6 ++++++ 4 files changed, 53 insertions(+) diff --git a/drivers/net/dsa/mv88e6xxx/chip.c b/drivers/net/dsa/mv88e6xxx/chip.c index 5005a35493e3..2bc22c59200c 100644 --- a/drivers/net/dsa/mv88e6xxx/chip.c +++ b/drivers/net/dsa/mv88e6xxx/chip.c @@ -2103,6 +2103,23 @@ static int mv88e6xxx_set_port_defqpri(struct mv88e6xxx_chip *chip, int port) return chip->info->ops->port_set_defqpri(chip, port, (u16)pri); } +static int mv88e6xxx_set_port_sched(struct mv88e6xxx_chip *chip, int port) +{ + struct dsa_switch *ds = chip->ds; + struct device_node *dn = ds->ports[port].dn; + int err; + u32 sched; + + if (!dn || !chip->info->ops->port_set_sched) + return 0; + + err = of_property_read_u32(dn, "schedule", &sched); + if (err < 0) + return 0; + + return chip->info->ops->port_set_sched(chip, port, (u16)sched); +} + static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port) { struct dsa_switch *ds = chip->ds; @@ -2218,6 +2235,10 @@ static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port) if (err) return err; + err = mv88e6xxx_set_port_sched(chip, port); + if (err) + return err; + if (chip->info->ops->port_pause_limit) { err = chip->info->ops->port_pause_limit(chip, port, 0, 0); if (err) @@ -3130,6 +3151,7 @@ static const struct mv88e6xxx_ops mv88e6172_ops = { .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, .port_set_defqpri = mv88e6xxx_port_set_defqpri, .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, + .port_set_sched = mv88e6xxx_port_set_sched, .port_pause_limit = mv88e6097_port_pause_limit, .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, @@ -3214,6 +3236,7 @@ static const struct mv88e6xxx_ops mv88e6176_ops = { .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, .port_set_defqpri = mv88e6xxx_port_set_defqpri, .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, + .port_set_sched = mv88e6xxx_port_set_sched, .port_pause_limit = mv88e6097_port_pause_limit, .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, @@ -3432,6 +3455,7 @@ static const struct mv88e6xxx_ops mv88e6240_ops = { .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, .port_set_defqpri = mv88e6xxx_port_set_defqpri, .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, + .port_set_sched = mv88e6xxx_port_set_sched, .port_pause_limit = mv88e6097_port_pause_limit, .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, @@ -3776,6 +3800,7 @@ static const struct mv88e6xxx_ops mv88e6352_ops = { .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, .port_set_defqpri = mv88e6xxx_port_set_defqpri, .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, + .port_set_sched = mv88e6xxx_port_set_sched, .port_pause_limit = mv88e6097_port_pause_limit, .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, diff --git a/drivers/net/dsa/mv88e6xxx/chip.h b/drivers/net/dsa/mv88e6xxx/chip.h index 2d2c24f5a79d..ff3e35eceee0 100644 --- a/drivers/net/dsa/mv88e6xxx/chip.h +++ b/drivers/net/dsa/mv88e6xxx/chip.h @@ -386,6 +386,7 @@ struct mv88e6xxx_ops { int (*port_set_defqpri)(struct mv88e6xxx_chip *chip, int port, u16 pri); int (*port_egress_rate_limiting)(struct mv88e6xxx_chip *chip, int port); + int (*port_set_sched)(struct mv88e6xxx_chip *chip, int port, u16 sched); int (*port_pause_limit)(struct mv88e6xxx_chip *chip, int port, u8 in, u8 out); int (*port_disable_learn_limit)(struct mv88e6xxx_chip *chip, int port); diff --git a/drivers/net/dsa/mv88e6xxx/port.c b/drivers/net/dsa/mv88e6xxx/port.c index 3a45fcd5cd9c..236732fc598d 100644 --- a/drivers/net/dsa/mv88e6xxx/port.c +++ b/drivers/net/dsa/mv88e6xxx/port.c @@ -1180,6 +1180,27 @@ int mv88e6097_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port) 0x0001); } +/* Offset 0x0A: Egress Rate Control 2 */ +int mv88e6xxx_port_set_sched(struct mv88e6xxx_chip *chip, int port, u16 sched) +{ + u16 reg; + int err; + + if (sched > MV88E6XXX_PORT_SCHED_STRICT_ALL) + return -EINVAL; + + err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2, + ®); + if (err) + return err; + + reg &= ~MV88E6XXX_PORT_SCHED_MASK; + reg |= sched << MV88E6XXX_PORT_SCHED_SHIFT; + + return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2, + reg); +} + /* Offset 0x0C: Port ATU Control */ int mv88e6xxx_port_disable_learn_limit(struct mv88e6xxx_chip *chip, int port) diff --git a/drivers/net/dsa/mv88e6xxx/port.h b/drivers/net/dsa/mv88e6xxx/port.h index 03884bbaa762..710d6eccafae 100644 --- a/drivers/net/dsa/mv88e6xxx/port.h +++ b/drivers/net/dsa/mv88e6xxx/port.h @@ -11,6 +11,7 @@ #ifndef _MV88E6XXX_PORT_H #define _MV88E6XXX_PORT_H +#include #include "chip.h" /* Offset 0x00: Port Status Register */ @@ -207,6 +208,10 @@ /* Offset 0x0A: Egress Rate Control 2 */ #define MV88E6XXX_PORT_EGRESS_RATE_CTL2 0x0a +#define MV88E6XXX_PORT_SCHED_SHIFT 12 +#define MV88E6XXX_PORT_SCHED_MASK \ + (0x3 << MV88E6XXX_PORT_SCHED_SHIFT) +/* see MV88E6XXX_PORT_SCHED_* in include/dt-bindings/net/dsa-mv88e6xxx.h */ /* Offset 0x0B: Port Association Vector */ #define MV88E6XXX_PORT_ASSOC_VECTOR 0x0b @@ -332,6 +337,7 @@ int mv88e6165_port_set_jumbo_size(struct mv88e6xxx_chip *chip, int port, int mv88e6xxx_port_set_defqpri(struct mv88e6xxx_chip *chip, int port, u16 pri); int mv88e6095_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port); int mv88e6097_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port); +int mv88e6xxx_port_set_sched(struct mv88e6xxx_chip *chip, int port, u16 sched); int mv88e6097_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in, u8 out); int mv88e6390_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in, From patchwork Tue Sep 10 15:41:51 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Beckett X-Patchwork-Id: 1160427 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=collabora.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 46STqg3092z9sNw for ; Wed, 11 Sep 2019 01:44:47 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2436473AbfIJPoq (ORCPT ); Tue, 10 Sep 2019 11:44:46 -0400 Received: from bhuna.collabora.co.uk ([46.235.227.227]:43820 "EHLO bhuna.collabora.co.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726664AbfIJPoq (ORCPT ); Tue, 10 Sep 2019 11:44:46 -0400 Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: bbeckett) with ESMTPSA id AA5C528DA1D From: Robert Beckett To: netdev@vger.kernel.org Cc: Robert Beckett , Andrew Lunn , Vivien Didelot , Florian Fainelli , "David S. Miller" , Rob Herring , Mark Rutland , devicetree@vger.kernel.org Subject: [PATCH 5/7] dt-bindings: mv88e6xxx: add ability to set queue scheduling Date: Tue, 10 Sep 2019 16:41:51 +0100 Message-Id: <20190910154238.9155-6-bob.beckett@collabora.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20190910154238.9155-1-bob.beckett@collabora.com> References: <20190910154238.9155-1-bob.beckett@collabora.com> Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Document port queue scheduling settings. Add definitions for specific valid values. Signed-off-by: Robert Beckett --- .../devicetree/bindings/net/dsa/marvell.txt | 12 ++++++++++++ include/dt-bindings/net/dsa-mv88e6xxx.h | 17 +++++++++++++++++ 2 files changed, 29 insertions(+) create mode 100644 include/dt-bindings/net/dsa-mv88e6xxx.h diff --git a/Documentation/devicetree/bindings/net/dsa/marvell.txt b/Documentation/devicetree/bindings/net/dsa/marvell.txt index e097c3c52eac..7de90929c3c9 100644 --- a/Documentation/devicetree/bindings/net/dsa/marvell.txt +++ b/Documentation/devicetree/bindings/net/dsa/marvell.txt @@ -50,6 +50,18 @@ Optional properties: Optional properties for ports: - defqpri= : Enforced default queue priority for the given port. Valid range is 0..3 +- schedule= : Set ports scheduling mode. Valid values are: + MV88E6XXX_PORT_SCHED_ROUND_ROBIN - All output queues + use a weighter round robin scheme. + MV88E6XXX_PORT_SCHED_STRICT_3 - Output queue 3 uses + a strict scheme, where any packets in queue 3 will be + egressed first, followed by weighted round robin for + the other ports. + MV88E6XXX_PORT_SCHED_STRICT_3_2 - Output queue's 2 + and 3 use strict, other use weighted round robin. + MV88E6XXX_PORT_SCHED_STRICT_ALL - All queues use + strict priority, where queues drain in descending + queue number order. Example: diff --git a/include/dt-bindings/net/dsa-mv88e6xxx.h b/include/dt-bindings/net/dsa-mv88e6xxx.h new file mode 100644 index 000000000000..3f62003841ce --- /dev/null +++ b/include/dt-bindings/net/dsa-mv88e6xxx.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Device Tree constants for Marvell 88E6xxx Switch Port Registers + * + * Copyright (c) 2019, Collabora Ltd. + * Copyright (c) 2019, General Electric Company + */ + +#ifndef _DT_BINDINGS_MV88E6XXX_H +#define _DT_BINDINGS_MV88E6XXX_H + +#define MV88E6XXX_PORT_SCHED_ROUND_ROBIN 0 +#define MV88E6XXX_PORT_SCHED_STRICT_3 1 +#define MV88E6XXX_PORT_SCHED_STRICT_3_2 2 +#define MV88E6XXX_PORT_SCHED_STRICT_ALL 3 + +#endif /* _DT_BINDINGS_MV88E6XXX_H */ From patchwork Tue Sep 10 15:41:52 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Beckett X-Patchwork-Id: 1160428 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=collabora.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 46STqy05xqz9sNw for ; Wed, 11 Sep 2019 01:45:02 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2436542AbfIJPpB (ORCPT ); Tue, 10 Sep 2019 11:45:01 -0400 Received: from bhuna.collabora.co.uk ([46.235.227.227]:43830 "EHLO bhuna.collabora.co.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726664AbfIJPpA (ORCPT ); Tue, 10 Sep 2019 11:45:00 -0400 Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: bbeckett) with ESMTPSA id 99BD328DA1D From: Robert Beckett To: netdev@vger.kernel.org Cc: Robert Beckett , Andrew Lunn , Vivien Didelot , Florian Fainelli , "David S. Miller" Subject: [PATCH 6/7] net: dsa: mv88e6xxx: add egress rate limiting Date: Tue, 10 Sep 2019 16:41:52 +0100 Message-Id: <20190910154238.9155-7-bob.beckett@collabora.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20190910154238.9155-1-bob.beckett@collabora.com> References: <20190910154238.9155-1-bob.beckett@collabora.com> Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Add code for specifying egress rate limiting per port. The rate can be specified as ethernet frames or bits per second. Signed-off-by: Robert Beckett --- drivers/net/dsa/mv88e6xxx/chip.c | 72 ++++++++++++++------- drivers/net/dsa/mv88e6xxx/chip.h | 3 +- drivers/net/dsa/mv88e6xxx/port.c | 106 ++++++++++++++++++++++++++++--- drivers/net/dsa/mv88e6xxx/port.h | 14 +++- 4 files changed, 158 insertions(+), 37 deletions(-) diff --git a/drivers/net/dsa/mv88e6xxx/chip.c b/drivers/net/dsa/mv88e6xxx/chip.c index 2bc22c59200c..8c116496ab2f 100644 --- a/drivers/net/dsa/mv88e6xxx/chip.c +++ b/drivers/net/dsa/mv88e6xxx/chip.c @@ -2120,6 +2120,32 @@ static int mv88e6xxx_set_port_sched(struct mv88e6xxx_chip *chip, int port) return chip->info->ops->port_set_sched(chip, port, (u16)sched); } +static int mv88e6xxx_set_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, + int port) +{ + struct dsa_switch *ds = chip->ds; + struct device_node *dn = ds->ports[port].dn; + int err; + u32 mode, count; + + if (!dn || !chip->info->ops->port_egress_rate_limiting) + return 0; + + err = of_property_read_u32(dn, "egress-limit-mode", &mode); + if (err < 0) + goto disable; + + err = of_property_read_u32(dn, "egress-limit-count", &count); + if (err < 0) + goto disable; + + return chip->info->ops->port_egress_rate_limiting(chip, port, count, + mode); + +disable: + return chip->info->ops->port_egress_rate_limiting(chip, port, 0, 0); +} + static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port) { struct dsa_switch *ds = chip->ds; @@ -2263,11 +2289,9 @@ static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port) return err; } - if (chip->info->ops->port_egress_rate_limiting) { - err = chip->info->ops->port_egress_rate_limiting(chip, port); - if (err) - return err; - } + err = mv88e6xxx_set_port_egress_rate_limiting(chip, port); + if (err) + return err; err = mv88e6xxx_setup_message_port(chip, port); if (err) @@ -2809,7 +2833,7 @@ static const struct mv88e6xxx_ops mv88e6085_ops = { .port_set_frame_mode = mv88e6351_port_set_frame_mode, .port_set_egress_floods = mv88e6352_port_set_egress_floods, .port_set_ether_type = mv88e6351_port_set_ether_type, - .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, + .port_egress_rate_limiting = mv88e6xxx_port_egress_rate_limiting, .port_pause_limit = mv88e6097_port_pause_limit, .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, @@ -2879,7 +2903,7 @@ static const struct mv88e6xxx_ops mv88e6097_ops = { .port_set_egress_floods = mv88e6352_port_set_egress_floods, .port_set_ether_type = mv88e6351_port_set_ether_type, .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, - .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, + .port_egress_rate_limiting = mv88e6xxx_port_egress_rate_limiting, .port_pause_limit = mv88e6097_port_pause_limit, .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, @@ -2951,7 +2975,7 @@ static const struct mv88e6xxx_ops mv88e6131_ops = { .port_set_ether_type = mv88e6351_port_set_ether_type, .port_set_upstream_port = mv88e6095_port_set_upstream_port, .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, - .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, + .port_egress_rate_limiting = mv88e6xxx_port_egress_rate_limiting, .port_pause_limit = mv88e6097_port_pause_limit, .port_set_pause = mv88e6185_port_set_pause, .port_link_state = mv88e6352_port_link_state, @@ -2994,7 +3018,7 @@ static const struct mv88e6xxx_ops mv88e6141_ops = { .port_set_egress_floods = mv88e6352_port_set_egress_floods, .port_set_ether_type = mv88e6351_port_set_ether_type, .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, - .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, + .port_egress_rate_limiting = mv88e6xxx_port_egress_rate_limiting, .port_pause_limit = mv88e6097_port_pause_limit, .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, @@ -3034,7 +3058,7 @@ static const struct mv88e6xxx_ops mv88e6161_ops = { .port_set_egress_floods = mv88e6352_port_set_egress_floods, .port_set_ether_type = mv88e6351_port_set_ether_type, .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, - .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, + .port_egress_rate_limiting = mv88e6xxx_port_egress_rate_limiting, .port_pause_limit = mv88e6097_port_pause_limit, .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, @@ -3108,7 +3132,7 @@ static const struct mv88e6xxx_ops mv88e6171_ops = { .port_set_egress_floods = mv88e6352_port_set_egress_floods, .port_set_ether_type = mv88e6351_port_set_ether_type, .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, - .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, + .port_egress_rate_limiting = mv88e6xxx_port_egress_rate_limiting, .port_pause_limit = mv88e6097_port_pause_limit, .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, @@ -3150,7 +3174,7 @@ static const struct mv88e6xxx_ops mv88e6172_ops = { .port_set_ether_type = mv88e6351_port_set_ether_type, .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, .port_set_defqpri = mv88e6xxx_port_set_defqpri, - .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, + .port_egress_rate_limiting = mv88e6xxx_port_egress_rate_limiting, .port_set_sched = mv88e6xxx_port_set_sched, .port_pause_limit = mv88e6097_port_pause_limit, .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, @@ -3193,7 +3217,7 @@ static const struct mv88e6xxx_ops mv88e6175_ops = { .port_set_egress_floods = mv88e6352_port_set_egress_floods, .port_set_ether_type = mv88e6351_port_set_ether_type, .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, - .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, + .port_egress_rate_limiting = mv88e6xxx_port_egress_rate_limiting, .port_pause_limit = mv88e6097_port_pause_limit, .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, @@ -3235,7 +3259,7 @@ static const struct mv88e6xxx_ops mv88e6176_ops = { .port_set_ether_type = mv88e6351_port_set_ether_type, .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, .port_set_defqpri = mv88e6xxx_port_set_defqpri, - .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, + .port_egress_rate_limiting = mv88e6xxx_port_egress_rate_limiting, .port_set_sched = mv88e6xxx_port_set_sched, .port_pause_limit = mv88e6097_port_pause_limit, .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, @@ -3275,7 +3299,7 @@ static const struct mv88e6xxx_ops mv88e6185_ops = { .port_set_speed = mv88e6185_port_set_speed, .port_set_frame_mode = mv88e6085_port_set_frame_mode, .port_set_egress_floods = mv88e6185_port_set_egress_floods, - .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, + .port_egress_rate_limiting = mv88e6xxx_port_egress_rate_limiting, .port_set_upstream_port = mv88e6095_port_set_upstream_port, .port_set_pause = mv88e6185_port_set_pause, .port_link_state = mv88e6185_port_link_state, @@ -3454,7 +3478,7 @@ static const struct mv88e6xxx_ops mv88e6240_ops = { .port_set_ether_type = mv88e6351_port_set_ether_type, .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, .port_set_defqpri = mv88e6xxx_port_set_defqpri, - .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, + .port_egress_rate_limiting = mv88e6xxx_port_egress_rate_limiting, .port_set_sched = mv88e6xxx_port_set_sched, .port_pause_limit = mv88e6097_port_pause_limit, .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, @@ -3587,7 +3611,7 @@ static const struct mv88e6xxx_ops mv88e6320_ops = { .port_set_egress_floods = mv88e6352_port_set_egress_floods, .port_set_ether_type = mv88e6351_port_set_ether_type, .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, - .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, + .port_egress_rate_limiting = mv88e6xxx_port_egress_rate_limiting, .port_pause_limit = mv88e6097_port_pause_limit, .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, @@ -3630,7 +3654,7 @@ static const struct mv88e6xxx_ops mv88e6321_ops = { .port_set_egress_floods = mv88e6352_port_set_egress_floods, .port_set_ether_type = mv88e6351_port_set_ether_type, .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, - .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, + .port_egress_rate_limiting = mv88e6xxx_port_egress_rate_limiting, .port_pause_limit = mv88e6097_port_pause_limit, .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, @@ -3673,7 +3697,7 @@ static const struct mv88e6xxx_ops mv88e6341_ops = { .port_set_egress_floods = mv88e6352_port_set_egress_floods, .port_set_ether_type = mv88e6351_port_set_ether_type, .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, - .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, + .port_egress_rate_limiting = mv88e6xxx_port_egress_rate_limiting, .port_pause_limit = mv88e6097_port_pause_limit, .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, @@ -3716,7 +3740,7 @@ static const struct mv88e6xxx_ops mv88e6350_ops = { .port_set_egress_floods = mv88e6352_port_set_egress_floods, .port_set_ether_type = mv88e6351_port_set_ether_type, .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, - .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, + .port_egress_rate_limiting = mv88e6xxx_port_egress_rate_limiting, .port_pause_limit = mv88e6097_port_pause_limit, .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, @@ -3755,7 +3779,7 @@ static const struct mv88e6xxx_ops mv88e6351_ops = { .port_set_egress_floods = mv88e6352_port_set_egress_floods, .port_set_ether_type = mv88e6351_port_set_ether_type, .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, - .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, + .port_egress_rate_limiting = mv88e6xxx_port_egress_rate_limiting, .port_pause_limit = mv88e6097_port_pause_limit, .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, @@ -3799,7 +3823,7 @@ static const struct mv88e6xxx_ops mv88e6352_ops = { .port_set_ether_type = mv88e6351_port_set_ether_type, .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, .port_set_defqpri = mv88e6xxx_port_set_defqpri, - .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, + .port_egress_rate_limiting = mv88e6xxx_port_egress_rate_limiting, .port_set_sched = mv88e6xxx_port_set_sched, .port_pause_limit = mv88e6097_port_pause_limit, .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, @@ -3851,7 +3875,7 @@ static const struct mv88e6xxx_ops mv88e6390_ops = { .port_set_egress_floods = mv88e6352_port_set_egress_floods, .port_set_ether_type = mv88e6351_port_set_ether_type, .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, - .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, + .port_egress_rate_limiting = mv88e6xxx_port_egress_rate_limiting, .port_pause_limit = mv88e6390_port_pause_limit, .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, @@ -3900,7 +3924,7 @@ static const struct mv88e6xxx_ops mv88e6390x_ops = { .port_set_egress_floods = mv88e6352_port_set_egress_floods, .port_set_ether_type = mv88e6351_port_set_ether_type, .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, - .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, + .port_egress_rate_limiting = mv88e6xxx_port_egress_rate_limiting, .port_pause_limit = mv88e6390_port_pause_limit, .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, diff --git a/drivers/net/dsa/mv88e6xxx/chip.h b/drivers/net/dsa/mv88e6xxx/chip.h index ff3e35eceee0..75fbd5df4aae 100644 --- a/drivers/net/dsa/mv88e6xxx/chip.h +++ b/drivers/net/dsa/mv88e6xxx/chip.h @@ -385,7 +385,8 @@ struct mv88e6xxx_ops { size_t size); int (*port_set_defqpri)(struct mv88e6xxx_chip *chip, int port, u16 pri); - int (*port_egress_rate_limiting)(struct mv88e6xxx_chip *chip, int port); + int (*port_egress_rate_limiting)(struct mv88e6xxx_chip *chip, int port, + u32 count, u32 mode); int (*port_set_sched)(struct mv88e6xxx_chip *chip, int port, u16 sched); int (*port_pause_limit)(struct mv88e6xxx_chip *chip, int port, u8 in, u8 out); diff --git a/drivers/net/dsa/mv88e6xxx/port.c b/drivers/net/dsa/mv88e6xxx/port.c index 236732fc598d..41418cfaca56 100644 --- a/drivers/net/dsa/mv88e6xxx/port.c +++ b/drivers/net/dsa/mv88e6xxx/port.c @@ -1166,21 +1166,107 @@ int mv88e6xxx_port_set_defqpri(struct mv88e6xxx_chip *chip, int port, u16 pri) return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL2, reg); } -/* Offset 0x09: Port Rate Control */ +/* Offset 0x09: Port Rate Control + * Offset 0x0A: Egress Rate Control 2 + */ -int mv88e6095_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port) +#define Kb 1000 +#define Mb (1000 * Kb) +#define Gb (1000ull * Mb) +#define EGRESS_FRAME_RATE_MIN 7632 +#define EGRESS_FRAME_RATE_MAX 31250000 +#define EGRESS_BPS_RATE_MIN (64 * Kb) +#define EGRESS_BPS_RATE_MAX (1 * Gb) +#define EGRESS_RATE_PERIOD 32 +int mv88e6xxx_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port, + u32 count, u32 mode) { - return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL1, - 0x0000); -} + u16 reg1, reg2; + int err; -int mv88e6097_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port) -{ - return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL1, - 0x0001); + /* quick exit for disabling */ + if (count == 0) { + err = mv88e6xxx_port_read(chip, port, + MV88E6XXX_PORT_EGRESS_RATE_CTL2, + ®2); + if (err) + return err; + reg2 &= ~MV88E6XXX_PORT_EGRESS_RATE_MASK; + err = mv88e6xxx_port_write(chip, port, + MV88E6XXX_PORT_EGRESS_RATE_CTL2, + reg2); + return err; + } + + if (mode > MV88E6XXX_PORT_EGRESS_COUNT_MODE_L3) + return -EINVAL; + + if (mode == MV88E6XXX_PORT_EGRESS_COUNT_MODE_FRAMES && + (count < EGRESS_FRAME_RATE_MIN || count > EGRESS_FRAME_RATE_MAX)) + return -EINVAL; + + if (mode != MV88E6XXX_PORT_EGRESS_COUNT_MODE_FRAMES && + (count < EGRESS_BPS_RATE_MIN || count > EGRESS_BPS_RATE_MAX)) + return -EINVAL; + + err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL1, + ®1); + if (err) + return err; + + err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2, + ®2); + if (err) + return err; + + reg1 &= ~MV88E6XXX_PORT_EGRESS_DEC_MASK; + reg2 &= ~MV88E6XXX_PORT_EGRESS_COUNT_MODE_MASK; + + if (mode == MV88E6XXX_PORT_EGRESS_COUNT_MODE_FRAMES) { + u32 val; + + /* recommended to use dec of 1 for frame based */ + reg1 |= 1 << MV88E6XXX_PORT_EGRESS_DEC_SHIFT; + + reg2 |= mode << MV88E6XXX_PORT_EGRESS_COUNT_MODE_SHIFT; + reg2 &= ~MV88E6XXX_PORT_EGRESS_RATE_MASK; + + val = NSEC_PER_SEC / (EGRESS_RATE_PERIOD * count); + if (NSEC_PER_SEC % (EGRESS_RATE_PERIOD * count)) + val++; + reg2 |= (u16)(val << MV88E6XXX_PORT_EGRESS_RATE_SHIFT); + } else { + u16 egress_dec, egress_rate; + u64 dec_bytes, ns_bits; + + if (count < (1 * Mb)) + egress_dec = (u16)roundup(count, (64 * Kb)); + else if (count < (100 * Mb)) + egress_dec = (u16)roundup(count, (1 * Mb)); + else + egress_dec = (u16)roundup(count, (10 * Mb)); + + reg1 |= egress_dec; + + dec_bytes = 8ull * NSEC_PER_SEC * egress_dec; + ns_bits = 32ull * count; + egress_rate = (u16)div64_u64(dec_bytes, ns_bits); + reg2 |= egress_rate; + } + + err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL1, + reg1); + if (err) + return err; + + err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2, + reg2); + if (err) + return err; + + return 0; } -/* Offset 0x0A: Egress Rate Control 2 */ int mv88e6xxx_port_set_sched(struct mv88e6xxx_chip *chip, int port, u16 sched) { u16 reg; diff --git a/drivers/net/dsa/mv88e6xxx/port.h b/drivers/net/dsa/mv88e6xxx/port.h index 710d6eccafae..724f839c570a 100644 --- a/drivers/net/dsa/mv88e6xxx/port.h +++ b/drivers/net/dsa/mv88e6xxx/port.h @@ -205,13 +205,23 @@ /* Offset 0x09: Egress Rate Control */ #define MV88E6XXX_PORT_EGRESS_RATE_CTL1 0x09 +#define MV88E6XXX_PORT_EGRESS_DEC_SHIFT 0 +#define MV88E6XXX_PORT_EGRESS_DEC_MASK 0x7f /* Offset 0x0A: Egress Rate Control 2 */ #define MV88E6XXX_PORT_EGRESS_RATE_CTL2 0x0a +#define MV88E6XXX_PORT_EGRESS_COUNT_MODE_SHIFT 14 +#define MV88E6XXX_PORT_EGRESS_COUNT_MODE_MASK \ + (0x3 << MV88E6XXX_PORT_EGRESS_COUNT_MODE_SHIFT) +/* see MV88E6XXX_PORT_EGRESS_COUNT_* in + * include/dt-bindings/net/dsa-mv88e6xxx.h + */ #define MV88E6XXX_PORT_SCHED_SHIFT 12 #define MV88E6XXX_PORT_SCHED_MASK \ (0x3 << MV88E6XXX_PORT_SCHED_SHIFT) /* see MV88E6XXX_PORT_SCHED_* in include/dt-bindings/net/dsa-mv88e6xxx.h */ +#define MV88E6XXX_PORT_EGRESS_RATE_SHIFT 0 +#define MV88E6XXX_PORT_EGRESS_RATE_MASK 0xfff /* Offset 0x0B: Port Association Vector */ #define MV88E6XXX_PORT_ASSOC_VECTOR 0x0b @@ -335,8 +345,8 @@ int mv88e6xxx_port_set_message_port(struct mv88e6xxx_chip *chip, int port, int mv88e6165_port_set_jumbo_size(struct mv88e6xxx_chip *chip, int port, size_t size); int mv88e6xxx_port_set_defqpri(struct mv88e6xxx_chip *chip, int port, u16 pri); -int mv88e6095_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port); -int mv88e6097_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port); +int mv88e6xxx_port_egress_rate_limiting(struct mv88e6xxx_chip *chip, int port, + u32 count, u32 mode); int mv88e6xxx_port_set_sched(struct mv88e6xxx_chip *chip, int port, u16 sched); int mv88e6097_port_pause_limit(struct mv88e6xxx_chip *chip, int port, u8 in, u8 out); From patchwork Tue Sep 10 15:41:53 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Robert Beckett X-Patchwork-Id: 1160429 X-Patchwork-Delegate: davem@davemloft.net Return-Path: X-Original-To: patchwork-incoming-netdev@ozlabs.org Delivered-To: patchwork-incoming-netdev@ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=netdev-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=collabora.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 46STr556L9z9s4Y for ; Wed, 11 Sep 2019 01:45:09 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2436552AbfIJPpJ (ORCPT ); Tue, 10 Sep 2019 11:45:09 -0400 Received: from bhuna.collabora.co.uk ([46.235.227.227]:43836 "EHLO bhuna.collabora.co.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726664AbfIJPpI (ORCPT ); Tue, 10 Sep 2019 11:45:08 -0400 Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: bbeckett) with ESMTPSA id 0AF8F28DA1D From: Robert Beckett To: netdev@vger.kernel.org Cc: Robert Beckett , Andrew Lunn , Vivien Didelot , Florian Fainelli , "David S. Miller" , Rob Herring , Mark Rutland , devicetree@vger.kernel.org Subject: [PATCH 7/7] dt-bindings: mv88e6xxx: add egress rate limiting Date: Tue, 10 Sep 2019 16:41:53 +0100 Message-Id: <20190910154238.9155-8-bob.beckett@collabora.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20190910154238.9155-1-bob.beckett@collabora.com> References: <20190910154238.9155-1-bob.beckett@collabora.com> Sender: netdev-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: netdev@vger.kernel.org Document port egress rate limiting settings. Add defines for specifying egress rate limiting mode. Signed-off-by: Robert Beckett --- .../devicetree/bindings/net/dsa/marvell.txt | 22 +++++++++++++++++++ include/dt-bindings/net/dsa-mv88e6xxx.h | 5 +++++ 2 files changed, 27 insertions(+) diff --git a/Documentation/devicetree/bindings/net/dsa/marvell.txt b/Documentation/devicetree/bindings/net/dsa/marvell.txt index 7de90929c3c9..d33c1958f420 100644 --- a/Documentation/devicetree/bindings/net/dsa/marvell.txt +++ b/Documentation/devicetree/bindings/net/dsa/marvell.txt @@ -62,6 +62,28 @@ Optional properties for ports: MV88E6XXX_PORT_SCHED_STRICT_ALL - All queues use strict priority, where queues drain in descending queue number order. +- egress-limit-mode= : Set port egress rate limiting mode. Valid values are: + MV88E6XXX_PORT_EGRESS_COUNT_MODE_FRAMES - Count layer + 2 frames (assumed to be 64kb). + MV88E6XXX_PORT_EGRESS_COUNT_MODE_L1 - Count all layer + 1 bits + MV88E6XXX_PORT_EGRESS_COUNT_MODE_L2 - Count all layer + 2 bits + MV88E6XXX_PORT_EGRESS_COUNT_MODE_L3 - Count all layer + 3 bits + Must also specify egress-limit-count. +- egress-limit-count=: Set port egress rate limiting count. If + egress-limit-mode is FRAMES, this specifies the + maximum number of ethernet frames to allow to egress + from this port per second, otherwise it is number of + bits as counted based on the mode allowed to egress + from this port per second. + The HW has limitations which the driver adheres to: + between 64 Kbps to 1 Mbps in 16 Kbps increments + between 1 Mbps to 100 Mbps in 1Mbps increments + between 100 Mbps to 1 Gbps in 10 Mbps increments. + Other values will be rounded down the previous + increment. Example: diff --git a/include/dt-bindings/net/dsa-mv88e6xxx.h b/include/dt-bindings/net/dsa-mv88e6xxx.h index 3f62003841ce..33ecd94f5e22 100644 --- a/include/dt-bindings/net/dsa-mv88e6xxx.h +++ b/include/dt-bindings/net/dsa-mv88e6xxx.h @@ -9,6 +9,11 @@ #ifndef _DT_BINDINGS_MV88E6XXX_H #define _DT_BINDINGS_MV88E6XXX_H +#define MV88E6XXX_PORT_EGRESS_COUNT_MODE_FRAMES 0 +#define MV88E6XXX_PORT_EGRESS_COUNT_MODE_L1 1 +#define MV88E6XXX_PORT_EGRESS_COUNT_MODE_L2 2 +#define MV88E6XXX_PORT_EGRESS_COUNT_MODE_L3 3 + #define MV88E6XXX_PORT_SCHED_ROUND_ROBIN 0 #define MV88E6XXX_PORT_SCHED_STRICT_3 1 #define MV88E6XXX_PORT_SCHED_STRICT_3_2 2