From patchwork Sun Sep 8 18:53:02 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Paul A. Clarke" X-Patchwork-Id: 1159521 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=sourceware.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=libc-alpha-return-105095-incoming=patchwork.ozlabs.org@sourceware.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=us.ibm.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; secure) header.d=sourceware.org header.i=@sourceware.org header.b="wWQV0B8N"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 46RL662n9fz9s00 for ; Mon, 9 Sep 2019 04:53:18 +1000 (AEST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=sourceware.org; h=list-id :list-unsubscribe:list-subscribe:list-archive:list-post :list-help:sender:from:to:cc:subject:date:message-id; q=dns; s= default; b=M8eqjjK8AH88fzms2RVzh7FRq24ODp1Gz84Cvx9Pogm+WQ1gnJT97 FmOO2dT0mgpH2gb1HRG8WovAY5tq8CsLNRR5UYbLd3jMJX72dN6E/sMcNJ8tJxVS 2cRWb4GhAfJDtZhVxyURkQJv7A4n03lXOzWZtWm3BN1wx+RhSloj9o= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=sourceware.org; h=list-id :list-unsubscribe:list-subscribe:list-archive:list-post :list-help:sender:from:to:cc:subject:date:message-id; s=default; bh=9pVpXxQwMBiKQaS2TrVW8PGb8lg=; b=wWQV0B8NC89urh5AoVihoHdM4WHA t/TkdiEucXVq60hHIRf6yW1HCyGzUUTtHi/5Z4/0rTk+/07TYPjPhfw1t6EbDGFl GRiD2/Qb5O8oxmx0wKFxJvYXxzGJVKy55fi/hSu1Zt0bMDA0zqZp9VqI4EDyNWxo eC3v6EMld/KVzHk= Received: (qmail 66567 invoked by alias); 8 Sep 2019 18:53:11 -0000 Mailing-List: contact libc-alpha-help@sourceware.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Subscribe: List-Archive: List-Post: List-Help: , Sender: libc-alpha-owner@sourceware.org Delivered-To: mailing list libc-alpha@sourceware.org Received: (qmail 66558 invoked by uid 89); 8 Sep 2019 18:53:11 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-27.6 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_LOW autolearn=ham version=3.3.1 spammy= X-HELO: mx0a-001b2d01.pphosted.com From: "Paul A. Clarke" To: libc-alpha@sourceware.org Cc: tuliom@ascii.art.br, murphyp@linux.ibm.com Subject: [PATCH] [powerpc] fenv_private.h clean up Date: Sun, 8 Sep 2019 13:53:02 -0500 Message-Id: <1567968782-29323-1-git-send-email-pc@us.ibm.com> From: "Paul A. Clarke" fenv_private.h includes unused functions, magic macro constants, and some replicated common code fragments. Remove unused functions, replace magic constants with constants from fenv_libc.h, and refactor replicated code. 2019-09-08 Paul A. Clarke * sysdeps/powerpc/fpu/fenv_private.h (_FPU_ALL_TRAPS): Delete, replace with FPSCR_ENABLES_MASK. (_FPU_MASK_RN): Delete. (_FPU_MASK_NOT_RN_NI): Delete. (_FPU_MASK_TRAPS_RN): Delete, replace with ~FPSCR_CONTROL_MASK. (_FPU_MASK_FRAC_INEX_RET_CC): Delete, replace with ~FPSCR_STATUS_MASK. (__TEST_AND_ENTER_NON_STOP): New. (__TEST_AND_EXIT_NON_STOP): New. (__libc_feholdbits_ppc): Delete, move code into libc_feholdexcept_setround_ppc. --- sysdeps/powerpc/fpu/fenv_private.h | 109 ++++++++++--------------------------- 1 file changed, 29 insertions(+), 80 deletions(-) diff --git a/sysdeps/powerpc/fpu/fenv_private.h b/sysdeps/powerpc/fpu/fenv_private.h index af72560..6072ad8 100644 --- a/sysdeps/powerpc/fpu/fenv_private.h +++ b/sysdeps/powerpc/fpu/fenv_private.h @@ -23,73 +23,40 @@ #include #include -/* Mask for the exception enable bits. */ -#define _FPU_ALL_TRAPS (_FPU_MASK_ZM | _FPU_MASK_OM | _FPU_MASK_UM \ - | _FPU_MASK_XM | _FPU_MASK_IM) +/* If the old env has no enabled exceptions and the new env has any enabled + exceptions, then unmask SIGFPE in the MSR FE0/FE1 bits. This will put the + hardware into "precise mode" and may cause the FPU to run slower on some + hardware. */ +#define __TEST_AND_ENTER_NON_STOP(old, new) \ + do { \ + if ((old & FPSCR_ENABLES_MASK) == 0 && (new & FPSCR_ENABLES_MASK) != 0) \ + (void) __fe_nomask_env_priv (); \ + } while (0) -/* Mask the rounding mode bits. */ -#define _FPU_MASK_RN 0xfffffffffffffffcLL - -/* Mask everything but the rounding modes and non-IEEE arithmetic flags. */ -#define _FPU_MASK_NOT_RN_NI 0xffffffff00000807LL - -/* Mask restore rounding mode and exception enabled. */ -#define _FPU_MASK_TRAPS_RN 0xffffffffffffff00LL - -/* Mask FP result flags, preserve fraction rounded/inexact bits. */ -#define _FPU_MASK_FRAC_INEX_RET_CC 0xfffffffffff80fffLL + /* If the old env had any enabled exceptions and the new env has no enabled + exceptions, then mask SIGFPE in the MSR FE0/FE1 bits. This may allow the + FPU to run faster because it always takes the default action and can not + generate SIGFPE. */ +#define __TEST_AND_EXIT_NON_STOP(old, new) \ + do { \ + if ((old & FPSCR_ENABLES_MASK) != 0 && (new & FPSCR_ENABLES_MASK) == 0) \ + (void) __fe_mask_env (); \ + } while (0) static __always_inline void -__libc_feholdbits_ppc (fenv_t *envp, unsigned long long mask, - unsigned long long bits) +libc_feholdexcept_setround_ppc (fenv_t *envp, int r) { fenv_union_t old, new; old.fenv = *envp = fegetenv_register (); - new.l = (old.l & mask) | bits; - - /* If the old env had any enabled exceptions, then mask SIGFPE in the - MSR FE0/FE1 bits. This may allow the FPU to run faster because it - always takes the default action and can not generate SIGFPE. */ - if ((old.l & _FPU_ALL_TRAPS) != 0) - (void) __fe_mask_env (); + __TEST_AND_ENTER_NON_STOP (old.l, 0); + /* Clear everything and set the rounding mode. */ + new.l = r; fesetenv_register (new.fenv); } -static __always_inline void -libc_feholdexcept_ppc (fenv_t *envp) -{ - __libc_feholdbits_ppc (envp, _FPU_MASK_NOT_RN_NI, 0LL); -} - -static __always_inline void -libc_feholdexcept_setround_ppc (fenv_t *envp, int r) -{ - __libc_feholdbits_ppc (envp, _FPU_MASK_NOT_RN_NI & _FPU_MASK_RN, r); -} - -static __always_inline void -libc_fesetround_ppc (int r) -{ - __fesetround_inline (r); -} - -static __always_inline int -libc_fetestexcept_ppc (int e) -{ - fenv_union_t u; - u.fenv = fegetenv_register (); - return u.l & e; -} - -static __always_inline void -libc_feholdsetround_ppc (fenv_t *e, int r) -{ - __libc_feholdbits_ppc (e, _FPU_MASK_TRAPS_RN, r); -} - static __always_inline unsigned long long __libc_femergeenv_ppc (const fenv_t *envp, unsigned long long old_mask, unsigned long long new_mask) @@ -102,19 +69,8 @@ __libc_femergeenv_ppc (const fenv_t *envp, unsigned long long old_mask, /* Merge bits while masking unwanted bits from new and old env. */ new.l = (old.l & old_mask) | (new.l & new_mask); - /* If the old env has no enabled exceptions and the new env has any enabled - exceptions, then unmask SIGFPE in the MSR FE0/FE1 bits. This will put the - hardware into "precise mode" and may cause the FPU to run slower on some - hardware. */ - if ((old.l & _FPU_ALL_TRAPS) == 0 && (new.l & _FPU_ALL_TRAPS) != 0) - (void) __fe_nomask_env_priv (); - - /* If the old env had any enabled exceptions and the new env has no enabled - exceptions, then mask SIGFPE in the MSR FE0/FE1 bits. This may allow the - FPU to run faster because it always takes the default action and can not - generate SIGFPE. */ - if ((old.l & _FPU_ALL_TRAPS) != 0 && (new.l & _FPU_ALL_TRAPS) == 0) - (void) __fe_mask_env (); + __TEST_AND_EXIT_NON_STOP (old.l, new.l); + __TEST_AND_ENTER_NON_STOP (old.l, new.l); /* If requesting to keep status, replace control, and merge exceptions, and exceptions haven't changed, we can just set new control instead @@ -146,12 +102,7 @@ libc_feresetround_ppc (fenv_t *envp) { fenv_union_t new = { .fenv = *envp }; - /* If the old env has no enabled exceptions and the new env has any enabled - exceptions, then unmask SIGFPE in the MSR FE0/FE1 bits. This will put the - hardware into "precise mode" and may cause the FPU to run slower on some - hardware. */ - if ((new.l & _FPU_ALL_TRAPS) != 0) - (void) __fe_nomask_env_priv (); + __TEST_AND_EXIT_NON_STOP (0, new.l); /* Atomically enable and raise (if appropriate) exceptions set in `new'. */ fesetenv_mode (new.fenv); @@ -160,8 +111,8 @@ libc_feresetround_ppc (fenv_t *envp) static __always_inline int libc_feupdateenv_test_ppc (fenv_t *envp, int ex) { - return __libc_femergeenv_ppc (envp, _FPU_MASK_TRAPS_RN, - _FPU_MASK_FRAC_INEX_RET_CC) & ex; + return __libc_femergeenv_ppc (envp, ~FPSCR_CONTROL_MASK, + ~FPSCR_STATUS_MASK) & ex; } static __always_inline void @@ -205,8 +156,7 @@ libc_feholdsetround_ppc_ctx (struct rm_ctx *ctx, int r) ctx->env = old.fenv; if (__glibc_unlikely (new.l != old.l)) { - if ((old.l & _FPU_ALL_TRAPS) != 0) - (void) __fe_mask_env (); + __TEST_AND_ENTER_NON_STOP (old.l, 0); fesetenv_mode (new.fenv); ctx->updated_status = true; } @@ -226,8 +176,7 @@ libc_feholdsetround_noex_ppc_ctx (struct rm_ctx *ctx, int r) ctx->env = old.fenv; if (__glibc_unlikely (new.l != old.l)) { - if ((old.l & _FPU_ALL_TRAPS) != 0) - (void) __fe_mask_env (); + __TEST_AND_ENTER_NON_STOP (old.l, 0); fesetenv_register (new.fenv); ctx->updated_status = true; }