From patchwork Fri Nov 10 10:58:24 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Simek X-Patchwork-Id: 836674 X-Patchwork-Delegate: monstr@monstr.eu Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=monstr-eu.20150623.gappssmtp.com header.i=@monstr-eu.20150623.gappssmtp.com header.b="gf7jvoT4"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3yYH9s2skGz9sNr for ; Fri, 10 Nov 2017 22:00:01 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 2E8F2C21C2F; Fri, 10 Nov 2017 10:59:01 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id CD877C21D5B; Fri, 10 Nov 2017 10:58:40 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 60DF4C21C2F; Fri, 10 Nov 2017 10:58:39 +0000 (UTC) Received: from mail-wm0-f67.google.com (mail-wm0-f67.google.com [74.125.82.67]) by lists.denx.de (Postfix) with ESMTPS id 02669C21C2B for ; Fri, 10 Nov 2017 10:58:39 +0000 (UTC) Received: by mail-wm0-f67.google.com with SMTP id r68so1893292wmr.3 for ; Fri, 10 Nov 2017 02:58:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=monstr-eu.20150623.gappssmtp.com; s=20150623; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=Wzyv9Tj1078NItL6734itOl/KuHAW5zEf81K68m+H6w=; b=gf7jvoT41geltwCG0JZdtS/vzXqiCbZn+XPxB5C4gNCvdZJyq9vEHp/zQpBXdWCTGZ 6vwitNAAIKFb432xlXgyx/v1gmTL1LJdX1Izpu8ERWDdLU0uPn3vA4zy0yiRNHKR6zmu l1Ci5QRDChu6omXLuCk23scftrdoxqzIDkcuubKZl/faGSc7URdpFvMEOUwamR24pOc8 qgWZ9C0YiOz/4QGa597AAYG3gW4isFnEIovnK/wFFSz5pm++wPLZmgWIAsaX3O4FesLl eFRLiiTdah475/YNTS9NJrF2EAK+OSpqtAxy+QEILqhlfPjuZh6PfYvlFhVGhJpcRdAv frvA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:in-reply-to:references; bh=Wzyv9Tj1078NItL6734itOl/KuHAW5zEf81K68m+H6w=; b=DKhgA7nbFYZtGzR+a1twO2hF+OFh10fjBsPAptBsJopv8yOZXsZ5rk/urSbfUeic9v zgiZciGohoATX0kjjTEIXpXYMmHhodzvVYLMlcRnZBokcqCGKH+5h/o2AI+aN7Brnkp2 9h6NYbD6eOhFrWiG3bVSdt02wlXRuU84Vy5votw1/LvuwZeIGlW15OWe/9CSXGoua7zw CfO/DLqj1VFTC/jbPKTK9iKrCM0dknkmKJZgRfvnph8oqN1xyvTPTKNYu6Z9lypXg+VM jURrhMzUmb7xQWss3Fr9qttQI6c0FHtxRXm14U+7ZfOZzQD1TGeeRoQqUp8yVexjQDSB 2Qtw== X-Gm-Message-State: AJaThX5TdCuc94rSqqv96YHvcDfwKkfhpgeRPz+BPktZe45QP6wsLSHA D2l46zd4V2uCrTERHgw6H7ogjVRp X-Google-Smtp-Source: AGs4zMZOJnBnm1rK7o0pmILYG+C9k8ixSXMo5bcm8s+jhGlDB68JAgNK48F+nYJsyregdKuwAWz8rg== X-Received: by 10.28.57.4 with SMTP id g4mr769004wma.92.1510311518446; Fri, 10 Nov 2017 02:58:38 -0800 (PST) Received: from localhost (nat-35.starnet.cz. [178.255.168.35]) by smtp.gmail.com with ESMTPSA id u33sm4309013wrf.42.2017.11.10.02.58.37 (version=TLS1_2 cipher=AES128-SHA bits=128/128); Fri, 10 Nov 2017 02:58:37 -0800 (PST) From: Michal Simek To: u-boot@lists.denx.de Date: Fri, 10 Nov 2017 11:58:24 +0100 Message-Id: <8ea13e95b1bba7905750660bf8b0cff434b5f87c.1510311500.git.michal.simek@xilinx.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: References: In-Reply-To: References: Subject: [U-Boot] [PATCH 1/9] arm: zynq: Add missing ps7_post_config declaration X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add missing declaration to header. Warning log: arch/arm/mach-zynq/spl.c:94:12: warning: symbol 'ps7_post_config' was not declared. Should it be static? Signed-off-by: Michal Simek --- arch/arm/mach-zynq/include/mach/sys_proto.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/mach-zynq/include/mach/sys_proto.h b/arch/arm/mach-zynq/include/mach/sys_proto.h index 67238e7fbcfd..0ef688309da3 100644 --- a/arch/arm/mach-zynq/include/mach/sys_proto.h +++ b/arch/arm/mach-zynq/include/mach/sys_proto.h @@ -22,5 +22,6 @@ int zynq_board_read_rom_ethaddr(unsigned char *ethaddr); /* Driver extern functions */ extern void ps7_init(void); +int ps7_post_config(void); #endif /* _SYS_PROTO_H_ */ From patchwork Fri Nov 10 10:58:25 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Simek X-Patchwork-Id: 836673 X-Patchwork-Delegate: monstr@monstr.eu Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=monstr-eu.20150623.gappssmtp.com header.i=@monstr-eu.20150623.gappssmtp.com header.b="O2l23gza"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3yYH9f6q1kz9sNr for ; Fri, 10 Nov 2017 21:59:50 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id A83E5C21DD0; Fri, 10 Nov 2017 10:59:18 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id B5374C21C59; Fri, 10 Nov 2017 10:58:49 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id E1172C21CA5; Fri, 10 Nov 2017 10:58:44 +0000 (UTC) Received: from mail-wm0-f67.google.com (mail-wm0-f67.google.com [74.125.82.67]) by lists.denx.de (Postfix) with ESMTPS id 42093C21C58 for ; Fri, 10 Nov 2017 10:58:40 +0000 (UTC) Received: by mail-wm0-f67.google.com with SMTP id b14so1901082wme.2 for ; Fri, 10 Nov 2017 02:58:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=monstr-eu.20150623.gappssmtp.com; s=20150623; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=cCNVntmRtmB8a1mtY1Gcy6Ralz4vTYNWg9O12gwrshQ=; b=O2l23gza9kboyPEoKLDtdX7P0dm6pUxPuN11bDTs7Se8hQEj33MhmWU+5Qn9nS6c1Z wFaSDtwbgiUpuARr6KbnkXDlxGY5B0KX6K8ah8SkFkDFkekhs2ezbpkrl7wIIC7vIrJJ ipD1nnAHAbTg5PUZ+bT8NUCMpiZD6cbtJDWdU9ThqIylf00Eug5hKICMD2oXkXjg1H6z 8emp/EqLRUL5Fw6dRd02x1qyJM7CIMaHwajIduiisZWHZ2zNKTxqUnOrbvV9AMq/pev9 yYtaineY69oph+P6lPjcKYykQ48vyCPo2b13kHh0RBSj69wtfEkiioQbif8aB4NHfZTB hoxQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:in-reply-to:references; bh=cCNVntmRtmB8a1mtY1Gcy6Ralz4vTYNWg9O12gwrshQ=; b=je/0G9jgARanPCrDWfNytQMzCs/aaGlNnhJ5vOn1U+SsasMvBHZdvKomHWldRoivH2 2UEsNNfeQp+TNeCbDnEHjcxO1AIjQnU7VfG3FWdr0MCHY5f3B4IAAj5xok8US+od237A JGqy6KHCtvjFDpHjgNYNIudBSz/rodUJxr+lxNMQ219+leRf7cBo+yj5I18cph0FY9yL e608fOSEauL/Q90PYEJ4iTEApc8Ga6hdtvlEvztUyF2TwFq84R3/tfGpCgPX9e0OGwxQ yjrZAuZckLOwNsuLvHGzHLIY7ftmXu/FaMC09+Xcp77xsImxNc4IkfK0c0vUAtS0xKdx /jpg== X-Gm-Message-State: AJaThX5y1Z6pYP0HxQPuyB7CgydqESD/K+ROueDNYMfvaYRYcF7LkRP3 TPy96OdQpJFGPZ0bXfVXlr/RtUXn X-Google-Smtp-Source: AGs4zMbl9W4xX2P6HDY/woOE4bNXuNmGyP2UvdmJ36Wq/L4BEfqZdfE6R78Y60fxKTK3jn5ZDyHXdw== X-Received: by 10.28.111.19 with SMTP id k19mr775085wmc.84.1510311519778; Fri, 10 Nov 2017 02:58:39 -0800 (PST) Received: from localhost (nat-35.starnet.cz. [178.255.168.35]) by smtp.gmail.com with ESMTPSA id f10sm7928305wrg.20.2017.11.10.02.58.39 (version=TLS1_2 cipher=AES128-SHA bits=128/128); Fri, 10 Nov 2017 02:58:39 -0800 (PST) From: Michal Simek To: u-boot@lists.denx.de Date: Fri, 10 Nov 2017 11:58:25 +0100 Message-Id: <4016ada5399c2533a18aff14a104365b098b0291.1510311500.git.michal.simek@xilinx.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: References: In-Reply-To: References: Subject: [U-Boot] [PATCH 2/9] arm: zynq: Enable debug uart on zc706 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Enable debug uart by default. Signed-off-by: Michal Simek --- configs/zynq_zc706_defconfig | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/configs/zynq_zc706_defconfig b/configs/zynq_zc706_defconfig index bc6fe3a30695..52999debc115 100644 --- a/configs/zynq_zc706_defconfig +++ b/configs/zynq_zc706_defconfig @@ -3,6 +3,7 @@ CONFIG_SYS_CONFIG_NAME="zynq_zc70x" CONFIG_ARCH_ZYNQ=y CONFIG_SYS_TEXT_BASE=0x4000000 CONFIG_DEFAULT_DEVICE_TREE="zynq-zc706" +CONFIG_DEBUG_UART=y CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y @@ -51,6 +52,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_ZYNQ_GEM=y +CONFIG_DEBUG_UART_ZYNQ=y +CONFIG_DEBUG_UART_BASE=0xe0001000 +CONFIG_DEBUG_UART_CLOCK=50000000 +CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_ZYNQ_SERIAL=y CONFIG_ZYNQ_QSPI=y CONFIG_USB=y From patchwork Fri Nov 10 10:58:26 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Simek X-Patchwork-Id: 836675 X-Patchwork-Delegate: monstr@monstr.eu Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=monstr-eu.20150623.gappssmtp.com header.i=@monstr-eu.20150623.gappssmtp.com header.b="EASpQPJ7"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3yYHBM0tyYz9sNr for ; Fri, 10 Nov 2017 22:00:27 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id CFEB2C21E1E; Fri, 10 Nov 2017 10:59:40 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id C3C39C21DA9; Fri, 10 Nov 2017 10:58:55 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 5E722C21D92; Fri, 10 Nov 2017 10:58:47 +0000 (UTC) Received: from mail-wr0-f196.google.com (mail-wr0-f196.google.com [209.85.128.196]) by lists.denx.de (Postfix) with ESMTPS id 5FBCFC21DA9 for ; Fri, 10 Nov 2017 10:58:42 +0000 (UTC) Received: by mail-wr0-f196.google.com with SMTP id q66so8228145wrb.13 for ; Fri, 10 Nov 2017 02:58:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=monstr-eu.20150623.gappssmtp.com; s=20150623; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=USMccebe4pZfC9130BMIA9M8nvJUdENYDZKiCq2eZ8E=; b=EASpQPJ7QouhX9SPpYC9kgEXARPwg9wk4CThUNefIBXqLkLuQqYatSfzWv+6vGhTrU RlUwSBNM2bHiteK5DoNGpxFoQyoGzyiafCbyE/pvSUChH0kif8N37UUUbfrTRt+EtqdD B8F2S8X3yxsj2I49pGul5vlQ37wzWTYjOwPwZeJIEWcSVC08xLXTRJFZtIeasHgV6k2Y QNiyV1fqiyPkwvH1ybGg19pw29eTFpFZpwtl/pb9JIKMQeKAEl0LjJ8wAEWTthL3xANs hb98IFa259Tc+u5GKCrXk6b+99bz/qlSLZikd+i1ilqH4Ni1GXCps+sjAyaZhk76JyVx Sh8w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:in-reply-to:references; bh=USMccebe4pZfC9130BMIA9M8nvJUdENYDZKiCq2eZ8E=; b=GFNO+BhdRXytfPy4Z6935tlHL2Opa3BBFLQqdjYm7ODZ1nNpOaZuh7qYxZxz4QQaKu QyIYkTVwIRcW2zpsxor8uXqYVEPr6SqfMwSIWEeSkvagA3LHyg9OtvJyPoqf+0v/L5QL cJ14cz1lgIPOezftvZO8W6STsoiE3OLd0GvvyFWdOvc+wC9jP9Y70H1wDmRue108CxOL 0U1Snzg6MvCWoThrMZopzZgQcQLZc044UeBJ4TQqhgjGnoSIjC61kOAdSZ8miLVZ6rDo 4+o4UATVrDIH9j/2j/bFDrnXdSl2FeanG3j6xSlkiu00mZ47/wr4uoGvjvxkDBHw844v 3Zxg== X-Gm-Message-State: AJaThX58a6UCPO+Yto0F0a7K4HzGdr9r1EgTrHfE954HczTEGqlp/p3g pPxeC4MgIqhHH2S6Vr4bCpMe3PV1 X-Google-Smtp-Source: ABhQp+R9jSw33NngqEcEzFbVhe5PMybt0RocglQDjOTK2iiQ2/UsTV4YrGeryvu2CRHUwg9Z468jKQ== X-Received: by 10.223.144.226 with SMTP id i89mr2886322wri.217.1510311521396; Fri, 10 Nov 2017 02:58:41 -0800 (PST) Received: from localhost (nat-35.starnet.cz. [178.255.168.35]) by smtp.gmail.com with ESMTPSA id c17sm9739310wrg.26.2017.11.10.02.58.40 (version=TLS1_2 cipher=AES128-SHA bits=128/128); Fri, 10 Nov 2017 02:58:40 -0800 (PST) From: Michal Simek To: u-boot@lists.denx.de Date: Fri, 10 Nov 2017 11:58:26 +0100 Message-Id: X-Mailer: git-send-email 1.9.1 In-Reply-To: References: In-Reply-To: References: Subject: [U-Boot] [PATCH 3/9] arm: zynq: Remove ps7_debug code X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" SPL is not calling this code that's why it is dead code and can be removed. Signed-off-by: Michal Simek --- .../opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.c | 10 -- .../opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.h | 1 - board/xilinx/zynq/zynq-microzed/ps7_init_gpl.c | 112 -------------------- board/xilinx/zynq/zynq-microzed/ps7_init_gpl.h | 1 - board/xilinx/zynq/zynq-zc702/ps7_init_gpl.c | 112 -------------------- board/xilinx/zynq/zynq-zc702/ps7_init_gpl.h | 1 - board/xilinx/zynq/zynq-zc706/ps7_init_gpl.c | 112 -------------------- board/xilinx/zynq/zynq-zc706/ps7_init_gpl.h | 1 - board/xilinx/zynq/zynq-zed/ps7_init_gpl.c | 112 -------------------- board/xilinx/zynq/zynq-zed/ps7_init_gpl.h | 1 - board/xilinx/zynq/zynq-zybo/ps7_init_gpl.c | 114 --------------------- board/xilinx/zynq/zynq-zybo/ps7_init_gpl.h | 1 - 12 files changed, 578 deletions(-) diff --git a/board/opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.c b/board/opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.c index 7ae04758b7d5..f2a757a5cfeb 100644 --- a/board/opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.c +++ b/board/opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.c @@ -255,12 +255,6 @@ unsigned long ps7_post_config_3_0[] = { EMIT_EXIT(), }; -unsigned long ps7_debug_3_0[] = { - EMIT_WRITE(0XF8898FB0, 0xC5ACCE55U), - EMIT_WRITE(0XF8899FB0, 0xC5ACCE55U), - EMIT_WRITE(0XF8809FB0, 0xC5ACCE55U), - EMIT_EXIT(), -}; unsigned long ps7_reset_apu_3_0[] = { EMIT_MASKWRITE(0xF8000244, 0x00000022U, 0x00000022U), @@ -353,10 +347,6 @@ int ps7_post_config(void) return ps7_config(ps7_post_config_3_0); } -int ps7_debug(void) -{ - return ps7_config(ps7_debug_3_0); -} int ps7_reset_apu(void) { diff --git a/board/opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.h b/board/opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.h index 158c25f3ae9b..cffffa90bbc5 100644 --- a/board/opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.h +++ b/board/opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.h @@ -69,7 +69,6 @@ extern "C" { int ps7_config(unsigned long *); int ps7_init(void); int ps7_post_config(void); -int ps7_debug(void); void perf_start_clock(void); void perf_disable_clock(void); diff --git a/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.c b/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.c index eb290023a1eb..58c31b8a50cf 100644 --- a/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.c +++ b/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.c @@ -4121,37 +4121,6 @@ unsigned long ps7_post_config_3_0[] = { // }; -unsigned long ps7_debug_3_0[] = { - // START: top - // .. START: CROSS TRIGGER CONFIGURATIONS - // .. .. START: UNLOCKING CTI REGISTERS - // .. .. KEY = 0XC5ACCE55 - // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U - // .. .. - EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U), - // .. .. KEY = 0XC5ACCE55 - // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U - // .. .. - EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U), - // .. .. KEY = 0XC5ACCE55 - // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U - // .. .. - EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U), - // .. .. FINISH: UNLOCKING CTI REGISTERS - // .. .. START: ENABLING CTI MODULES AND CHANNELS - // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS - // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS - // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS - // .. FINISH: CROSS TRIGGER CONFIGURATIONS - // FINISH: top - // - EMIT_EXIT(), - - // -}; unsigned long ps7_pll_init_data_2_0[] = { // START: top @@ -8419,37 +8388,6 @@ unsigned long ps7_post_config_2_0[] = { // }; -unsigned long ps7_debug_2_0[] = { - // START: top - // .. START: CROSS TRIGGER CONFIGURATIONS - // .. .. START: UNLOCKING CTI REGISTERS - // .. .. KEY = 0XC5ACCE55 - // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U - // .. .. - EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U), - // .. .. KEY = 0XC5ACCE55 - // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U - // .. .. - EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U), - // .. .. KEY = 0XC5ACCE55 - // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U - // .. .. - EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U), - // .. .. FINISH: UNLOCKING CTI REGISTERS - // .. .. START: ENABLING CTI MODULES AND CHANNELS - // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS - // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS - // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS - // .. FINISH: CROSS TRIGGER CONFIGURATIONS - // FINISH: top - // - EMIT_EXIT(), - - // -}; unsigned long ps7_pll_init_data_1_0[] = { // START: top @@ -12650,37 +12588,6 @@ unsigned long ps7_post_config_1_0[] = { // }; -unsigned long ps7_debug_1_0[] = { - // START: top - // .. START: CROSS TRIGGER CONFIGURATIONS - // .. .. START: UNLOCKING CTI REGISTERS - // .. .. KEY = 0XC5ACCE55 - // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U - // .. .. - EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U), - // .. .. KEY = 0XC5ACCE55 - // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U - // .. .. - EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U), - // .. .. KEY = 0XC5ACCE55 - // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U - // .. .. - EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U), - // .. .. FINISH: UNLOCKING CTI REGISTERS - // .. .. START: ENABLING CTI MODULES AND CHANNELS - // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS - // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS - // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS - // .. FINISH: CROSS TRIGGER CONFIGURATIONS - // FINISH: top - // - EMIT_EXIT(), - - // -}; #include "xil_io.h" @@ -12844,25 +12751,6 @@ ps7_post_config() } int -ps7_debug() -{ - // Get the PS_VERSION on run time - unsigned long si_ver = ps7GetSiliconVersion (); - int ret = -1; - if (si_ver == PCW_SILICON_VERSION_1) { - ret = ps7_config (ps7_debug_1_0); - if (ret != PS7_INIT_SUCCESS) return ret; - } else if (si_ver == PCW_SILICON_VERSION_2) { - ret = ps7_config (ps7_debug_2_0); - if (ret != PS7_INIT_SUCCESS) return ret; - } else { - ret = ps7_config (ps7_debug_3_0); - if (ret != PS7_INIT_SUCCESS) return ret; - } - return PS7_INIT_SUCCESS; -} - -int ps7_init() { // Get the PS_VERSION on run time diff --git a/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.h b/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.h index bdea5a0443c0..d775a33d98cb 100644 --- a/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.h +++ b/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.h @@ -104,7 +104,6 @@ extern unsigned long * ps7_peripherals_init_data; int ps7_config( unsigned long*); int ps7_init(); int ps7_post_config(); -int ps7_debug(); char* getPS7MessageInfo(unsigned key); void perf_start_clock(void); diff --git a/board/xilinx/zynq/zynq-zc702/ps7_init_gpl.c b/board/xilinx/zynq/zynq-zc702/ps7_init_gpl.c index abfd91187df3..99cf4681f84b 100644 --- a/board/xilinx/zynq/zynq-zc702/ps7_init_gpl.c +++ b/board/xilinx/zynq/zynq-zc702/ps7_init_gpl.c @@ -4228,37 +4228,6 @@ unsigned long ps7_post_config_3_0[] = { // }; -unsigned long ps7_debug_3_0[] = { - // START: top - // .. START: CROSS TRIGGER CONFIGURATIONS - // .. .. START: UNLOCKING CTI REGISTERS - // .. .. KEY = 0XC5ACCE55 - // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U - // .. .. - EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U), - // .. .. KEY = 0XC5ACCE55 - // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U - // .. .. - EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U), - // .. .. KEY = 0XC5ACCE55 - // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U - // .. .. - EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U), - // .. .. FINISH: UNLOCKING CTI REGISTERS - // .. .. START: ENABLING CTI MODULES AND CHANNELS - // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS - // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS - // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS - // .. FINISH: CROSS TRIGGER CONFIGURATIONS - // FINISH: top - // - EMIT_EXIT(), - - // -}; unsigned long ps7_pll_init_data_2_0[] = { // START: top @@ -8639,37 +8608,6 @@ unsigned long ps7_post_config_2_0[] = { // }; -unsigned long ps7_debug_2_0[] = { - // START: top - // .. START: CROSS TRIGGER CONFIGURATIONS - // .. .. START: UNLOCKING CTI REGISTERS - // .. .. KEY = 0XC5ACCE55 - // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U - // .. .. - EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U), - // .. .. KEY = 0XC5ACCE55 - // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U - // .. .. - EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U), - // .. .. KEY = 0XC5ACCE55 - // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U - // .. .. - EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U), - // .. .. FINISH: UNLOCKING CTI REGISTERS - // .. .. START: ENABLING CTI MODULES AND CHANNELS - // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS - // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS - // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS - // .. FINISH: CROSS TRIGGER CONFIGURATIONS - // FINISH: top - // - EMIT_EXIT(), - - // -}; unsigned long ps7_pll_init_data_1_0[] = { // START: top @@ -12983,37 +12921,6 @@ unsigned long ps7_post_config_1_0[] = { // }; -unsigned long ps7_debug_1_0[] = { - // START: top - // .. START: CROSS TRIGGER CONFIGURATIONS - // .. .. START: UNLOCKING CTI REGISTERS - // .. .. KEY = 0XC5ACCE55 - // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U - // .. .. - EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U), - // .. .. KEY = 0XC5ACCE55 - // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U - // .. .. - EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U), - // .. .. KEY = 0XC5ACCE55 - // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U - // .. .. - EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U), - // .. .. FINISH: UNLOCKING CTI REGISTERS - // .. .. START: ENABLING CTI MODULES AND CHANNELS - // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS - // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS - // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS - // .. FINISH: CROSS TRIGGER CONFIGURATIONS - // FINISH: top - // - EMIT_EXIT(), - - // -}; #include "xil_io.h" @@ -13177,25 +13084,6 @@ ps7_post_config() } int -ps7_debug() -{ - // Get the PS_VERSION on run time - unsigned long si_ver = ps7GetSiliconVersion (); - int ret = -1; - if (si_ver == PCW_SILICON_VERSION_1) { - ret = ps7_config (ps7_debug_1_0); - if (ret != PS7_INIT_SUCCESS) return ret; - } else if (si_ver == PCW_SILICON_VERSION_2) { - ret = ps7_config (ps7_debug_2_0); - if (ret != PS7_INIT_SUCCESS) return ret; - } else { - ret = ps7_config (ps7_debug_3_0); - if (ret != PS7_INIT_SUCCESS) return ret; - } - return PS7_INIT_SUCCESS; -} - -int ps7_init() { // Get the PS_VERSION on run time diff --git a/board/xilinx/zynq/zynq-zc702/ps7_init_gpl.h b/board/xilinx/zynq/zynq-zc702/ps7_init_gpl.h index 16fa8104a415..beb3b58b0c4d 100644 --- a/board/xilinx/zynq/zynq-zc702/ps7_init_gpl.h +++ b/board/xilinx/zynq/zynq-zc702/ps7_init_gpl.h @@ -104,7 +104,6 @@ extern unsigned long * ps7_peripherals_init_data; int ps7_config( unsigned long*); int ps7_init(); int ps7_post_config(); -int ps7_debug(); char* getPS7MessageInfo(unsigned key); void perf_start_clock(void); diff --git a/board/xilinx/zynq/zynq-zc706/ps7_init_gpl.c b/board/xilinx/zynq/zynq-zc706/ps7_init_gpl.c index 77fd9499df76..c45cc6a6e514 100644 --- a/board/xilinx/zynq/zynq-zc706/ps7_init_gpl.c +++ b/board/xilinx/zynq/zynq-zc706/ps7_init_gpl.c @@ -4197,37 +4197,6 @@ unsigned long ps7_post_config_3_0[] = { // }; -unsigned long ps7_debug_3_0[] = { - // START: top - // .. START: CROSS TRIGGER CONFIGURATIONS - // .. .. START: UNLOCKING CTI REGISTERS - // .. .. KEY = 0XC5ACCE55 - // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U - // .. .. - EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U), - // .. .. KEY = 0XC5ACCE55 - // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U - // .. .. - EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U), - // .. .. KEY = 0XC5ACCE55 - // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U - // .. .. - EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U), - // .. .. FINISH: UNLOCKING CTI REGISTERS - // .. .. START: ENABLING CTI MODULES AND CHANNELS - // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS - // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS - // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS - // .. FINISH: CROSS TRIGGER CONFIGURATIONS - // FINISH: top - // - EMIT_EXIT(), - - // -}; unsigned long ps7_pll_init_data_2_0[] = { // START: top @@ -8577,37 +8546,6 @@ unsigned long ps7_post_config_2_0[] = { // }; -unsigned long ps7_debug_2_0[] = { - // START: top - // .. START: CROSS TRIGGER CONFIGURATIONS - // .. .. START: UNLOCKING CTI REGISTERS - // .. .. KEY = 0XC5ACCE55 - // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U - // .. .. - EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U), - // .. .. KEY = 0XC5ACCE55 - // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U - // .. .. - EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U), - // .. .. KEY = 0XC5ACCE55 - // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U - // .. .. - EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U), - // .. .. FINISH: UNLOCKING CTI REGISTERS - // .. .. START: ENABLING CTI MODULES AND CHANNELS - // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS - // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS - // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS - // .. FINISH: CROSS TRIGGER CONFIGURATIONS - // FINISH: top - // - EMIT_EXIT(), - - // -}; unsigned long ps7_pll_init_data_1_0[] = { // START: top @@ -12890,37 +12828,6 @@ unsigned long ps7_post_config_1_0[] = { // }; -unsigned long ps7_debug_1_0[] = { - // START: top - // .. START: CROSS TRIGGER CONFIGURATIONS - // .. .. START: UNLOCKING CTI REGISTERS - // .. .. KEY = 0XC5ACCE55 - // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U - // .. .. - EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U), - // .. .. KEY = 0XC5ACCE55 - // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U - // .. .. - EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U), - // .. .. KEY = 0XC5ACCE55 - // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U - // .. .. - EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U), - // .. .. FINISH: UNLOCKING CTI REGISTERS - // .. .. START: ENABLING CTI MODULES AND CHANNELS - // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS - // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS - // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS - // .. FINISH: CROSS TRIGGER CONFIGURATIONS - // FINISH: top - // - EMIT_EXIT(), - - // -}; #include "xil_io.h" @@ -13084,25 +12991,6 @@ ps7_post_config() } int -ps7_debug() -{ - // Get the PS_VERSION on run time - unsigned long si_ver = ps7GetSiliconVersion (); - int ret = -1; - if (si_ver == PCW_SILICON_VERSION_1) { - ret = ps7_config (ps7_debug_1_0); - if (ret != PS7_INIT_SUCCESS) return ret; - } else if (si_ver == PCW_SILICON_VERSION_2) { - ret = ps7_config (ps7_debug_2_0); - if (ret != PS7_INIT_SUCCESS) return ret; - } else { - ret = ps7_config (ps7_debug_3_0); - if (ret != PS7_INIT_SUCCESS) return ret; - } - return PS7_INIT_SUCCESS; -} - -int ps7_init() { // Get the PS_VERSION on run time diff --git a/board/xilinx/zynq/zynq-zc706/ps7_init_gpl.h b/board/xilinx/zynq/zynq-zc706/ps7_init_gpl.h index 8527eef447e7..694412a1e9d5 100644 --- a/board/xilinx/zynq/zynq-zc706/ps7_init_gpl.h +++ b/board/xilinx/zynq/zynq-zc706/ps7_init_gpl.h @@ -104,7 +104,6 @@ extern unsigned long * ps7_peripherals_init_data; int ps7_config( unsigned long*); int ps7_init(); int ps7_post_config(); -int ps7_debug(); char* getPS7MessageInfo(unsigned key); void perf_start_clock(void); diff --git a/board/xilinx/zynq/zynq-zed/ps7_init_gpl.c b/board/xilinx/zynq/zynq-zed/ps7_init_gpl.c index f4f45becd66a..783fd9a30b78 100644 --- a/board/xilinx/zynq/zynq-zed/ps7_init_gpl.c +++ b/board/xilinx/zynq/zynq-zed/ps7_init_gpl.c @@ -4087,37 +4087,6 @@ unsigned long ps7_post_config_3_0[] = { // }; -unsigned long ps7_debug_3_0[] = { - // START: top - // .. START: CROSS TRIGGER CONFIGURATIONS - // .. .. START: UNLOCKING CTI REGISTERS - // .. .. KEY = 0XC5ACCE55 - // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U - // .. .. - EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U), - // .. .. KEY = 0XC5ACCE55 - // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U - // .. .. - EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U), - // .. .. KEY = 0XC5ACCE55 - // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U - // .. .. - EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U), - // .. .. FINISH: UNLOCKING CTI REGISTERS - // .. .. START: ENABLING CTI MODULES AND CHANNELS - // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS - // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS - // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS - // .. FINISH: CROSS TRIGGER CONFIGURATIONS - // FINISH: top - // - EMIT_EXIT(), - - // -}; unsigned long ps7_pll_init_data_2_0[] = { // START: top @@ -8351,37 +8320,6 @@ unsigned long ps7_post_config_2_0[] = { // }; -unsigned long ps7_debug_2_0[] = { - // START: top - // .. START: CROSS TRIGGER CONFIGURATIONS - // .. .. START: UNLOCKING CTI REGISTERS - // .. .. KEY = 0XC5ACCE55 - // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U - // .. .. - EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U), - // .. .. KEY = 0XC5ACCE55 - // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U - // .. .. - EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U), - // .. .. KEY = 0XC5ACCE55 - // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U - // .. .. - EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U), - // .. .. FINISH: UNLOCKING CTI REGISTERS - // .. .. START: ENABLING CTI MODULES AND CHANNELS - // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS - // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS - // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS - // .. FINISH: CROSS TRIGGER CONFIGURATIONS - // FINISH: top - // - EMIT_EXIT(), - - // -}; unsigned long ps7_pll_init_data_1_0[] = { // START: top @@ -12548,37 +12486,6 @@ unsigned long ps7_post_config_1_0[] = { // }; -unsigned long ps7_debug_1_0[] = { - // START: top - // .. START: CROSS TRIGGER CONFIGURATIONS - // .. .. START: UNLOCKING CTI REGISTERS - // .. .. KEY = 0XC5ACCE55 - // .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U - // .. .. - EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU ,0xC5ACCE55U), - // .. .. KEY = 0XC5ACCE55 - // .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U - // .. .. - EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU ,0xC5ACCE55U), - // .. .. KEY = 0XC5ACCE55 - // .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U - // .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U - // .. .. - EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU ,0xC5ACCE55U), - // .. .. FINISH: UNLOCKING CTI REGISTERS - // .. .. START: ENABLING CTI MODULES AND CHANNELS - // .. .. FINISH: ENABLING CTI MODULES AND CHANNELS - // .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS - // .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS - // .. FINISH: CROSS TRIGGER CONFIGURATIONS - // FINISH: top - // - EMIT_EXIT(), - - // -}; #include "xil_io.h" @@ -12742,25 +12649,6 @@ ps7_post_config() } int -ps7_debug() -{ - // Get the PS_VERSION on run time - unsigned long si_ver = ps7GetSiliconVersion (); - int ret = -1; - if (si_ver == PCW_SILICON_VERSION_1) { - ret = ps7_config (ps7_debug_1_0); - if (ret != PS7_INIT_SUCCESS) return ret; - } else if (si_ver == PCW_SILICON_VERSION_2) { - ret = ps7_config (ps7_debug_2_0); - if (ret != PS7_INIT_SUCCESS) return ret; - } else { - ret = ps7_config (ps7_debug_3_0); - if (ret != PS7_INIT_SUCCESS) return ret; - } - return PS7_INIT_SUCCESS; -} - -int ps7_init() { // Get the PS_VERSION on run time diff --git a/board/xilinx/zynq/zynq-zed/ps7_init_gpl.h b/board/xilinx/zynq/zynq-zed/ps7_init_gpl.h index 9b41e286976b..6d89863854e2 100644 --- a/board/xilinx/zynq/zynq-zed/ps7_init_gpl.h +++ b/board/xilinx/zynq/zynq-zed/ps7_init_gpl.h @@ -104,7 +104,6 @@ extern unsigned long * ps7_peripherals_init_data; int ps7_config( unsigned long*); int ps7_init(); int ps7_post_config(); -int ps7_debug(); char* getPS7MessageInfo(unsigned key); void perf_start_clock(void); diff --git a/board/xilinx/zynq/zynq-zybo/ps7_init_gpl.c b/board/xilinx/zynq/zynq-zybo/ps7_init_gpl.c index 83daf7bf15b8..ed7c2a64e128 100644 --- a/board/xilinx/zynq/zynq-zybo/ps7_init_gpl.c +++ b/board/xilinx/zynq/zynq-zybo/ps7_init_gpl.c @@ -4141,37 +4141,6 @@ unsigned long ps7_post_config_3_0[] = { /* */ }; -unsigned long ps7_debug_3_0[] = { - /* START: top */ - /* .. START: CROSS TRIGGER CONFIGURATIONS */ - /* .. .. START: UNLOCKING CTI REGISTERS */ - /* .. .. KEY = 0XC5ACCE55 */ - /* .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U */ - /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU, 0xC5ACCE55U), - /* .. .. KEY = 0XC5ACCE55 */ - /* .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U */ - /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU, 0xC5ACCE55U), - /* .. .. KEY = 0XC5ACCE55 */ - /* .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U */ - /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU, 0xC5ACCE55U), - /* .. .. FINISH: UNLOCKING CTI REGISTERS */ - /* .. .. START: ENABLING CTI MODULES AND CHANNELS */ - /* .. .. FINISH: ENABLING CTI MODULES AND CHANNELS */ - /* .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS */ - /* .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS */ - /* .. FINISH: CROSS TRIGGER CONFIGURATIONS */ - /* FINISH: top */ - /* */ - EMIT_EXIT(), - - /* */ -}; unsigned long ps7_pll_init_data_2_0[] = { /* START: top */ @@ -8467,37 +8436,6 @@ unsigned long ps7_post_config_2_0[] = { /* */ }; -unsigned long ps7_debug_2_0[] = { - /* START: top */ - /* .. START: CROSS TRIGGER CONFIGURATIONS */ - /* .. .. START: UNLOCKING CTI REGISTERS */ - /* .. .. KEY = 0XC5ACCE55 */ - /* .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U */ - /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU, 0xC5ACCE55U), - /* .. .. KEY = 0XC5ACCE55 */ - /* .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U */ - /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU, 0xC5ACCE55U), - /* .. .. KEY = 0XC5ACCE55 */ - /* .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U */ - /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU, 0xC5ACCE55U), - /* .. .. FINISH: UNLOCKING CTI REGISTERS */ - /* .. .. START: ENABLING CTI MODULES AND CHANNELS */ - /* .. .. FINISH: ENABLING CTI MODULES AND CHANNELS */ - /* .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS */ - /* .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS */ - /* .. FINISH: CROSS TRIGGER CONFIGURATIONS */ - /* FINISH: top */ - /* */ - EMIT_EXIT(), - - /* */ -}; unsigned long ps7_pll_init_data_1_0[] = { /* START: top */ @@ -12726,37 +12664,6 @@ unsigned long ps7_post_config_1_0[] = { /* */ }; -unsigned long ps7_debug_1_0[] = { - /* START: top */ - /* .. START: CROSS TRIGGER CONFIGURATIONS */ - /* .. .. START: UNLOCKING CTI REGISTERS */ - /* .. .. KEY = 0XC5ACCE55 */ - /* .. .. ==> 0XF8898FB0[31:0] = 0xC5ACCE55U */ - /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8898FB0, 0xFFFFFFFFU, 0xC5ACCE55U), - /* .. .. KEY = 0XC5ACCE55 */ - /* .. .. ==> 0XF8899FB0[31:0] = 0xC5ACCE55U */ - /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8899FB0, 0xFFFFFFFFU, 0xC5ACCE55U), - /* .. .. KEY = 0XC5ACCE55 */ - /* .. .. ==> 0XF8809FB0[31:0] = 0xC5ACCE55U */ - /* .. .. ==> MASK : 0xFFFFFFFFU VAL : 0xC5ACCE55U */ - /* .. .. */ - EMIT_MASKWRITE(0XF8809FB0, 0xFFFFFFFFU, 0xC5ACCE55U), - /* .. .. FINISH: UNLOCKING CTI REGISTERS */ - /* .. .. START: ENABLING CTI MODULES AND CHANNELS */ - /* .. .. FINISH: ENABLING CTI MODULES AND CHANNELS */ - /* .. .. START: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS */ - /* .. .. FINISH: MAPPING CPU0, CPU1 AND FTM EVENTS TO CTM CHANNELS */ - /* .. FINISH: CROSS TRIGGER CONFIGURATIONS */ - /* FINISH: top */ - /* */ - EMIT_EXIT(), - - /* */ -}; #include "xil_io.h" #define PS7_MASK_POLL_TIME 100000000 @@ -12926,27 +12833,6 @@ int ps7_post_config(void) return PS7_INIT_SUCCESS; } -int ps7_debug(void) -{ - /* Get the PS_VERSION on run time */ - unsigned long si_ver = ps7GetSiliconVersion(); - int ret = -1; - if (si_ver == PCW_SILICON_VERSION_1) { - ret = ps7_config(ps7_debug_1_0); - if (ret != PS7_INIT_SUCCESS) - return ret; - } else if (si_ver == PCW_SILICON_VERSION_2) { - ret = ps7_config(ps7_debug_2_0); - if (ret != PS7_INIT_SUCCESS) - return ret; - } else { - ret = ps7_config(ps7_debug_3_0); - if (ret != PS7_INIT_SUCCESS) - return ret; - } - return PS7_INIT_SUCCESS; -} - int ps7_init(void) { /* Get the PS_VERSION on run time */ diff --git a/board/xilinx/zynq/zynq-zybo/ps7_init_gpl.h b/board/xilinx/zynq/zynq-zybo/ps7_init_gpl.h index 22d9fd9250e8..929251afc5f2 100644 --- a/board/xilinx/zynq/zynq-zybo/ps7_init_gpl.h +++ b/board/xilinx/zynq/zynq-zybo/ps7_init_gpl.h @@ -85,7 +85,6 @@ extern unsigned long *ps7_peripherals_init_data; int ps7_config(unsigned long *); int ps7_init(void); int ps7_post_config(void); -int ps7_debug(void); char *getPS7MessageInfo(unsigned key); void perf_start_clock(void); From patchwork Fri Nov 10 10:58:27 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Simek X-Patchwork-Id: 836677 X-Patchwork-Delegate: monstr@monstr.eu Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=monstr-eu.20150623.gappssmtp.com header.i=@monstr-eu.20150623.gappssmtp.com header.b="lyHhw3Rk"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3yYHFW0h4cz9rvt for ; Fri, 10 Nov 2017 22:03:11 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id ADE96C21DE4; Fri, 10 Nov 2017 11:00:33 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 0ACB0C21CB1; Fri, 10 Nov 2017 10:58:56 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 81D0BC21DA2; Fri, 10 Nov 2017 10:58:47 +0000 (UTC) Received: from mail-wm0-f65.google.com (mail-wm0-f65.google.com [74.125.82.65]) by lists.denx.de (Postfix) with ESMTPS id 9212BC21DB2 for ; Fri, 10 Nov 2017 10:58:43 +0000 (UTC) Received: by mail-wm0-f65.google.com with SMTP id p75so1893544wmg.3 for ; Fri, 10 Nov 2017 02:58:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=monstr-eu.20150623.gappssmtp.com; s=20150623; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=XqW5yuN+7kfHqiBsKAo7lL+/wqpeLvF3mwXBlkP7D6c=; b=lyHhw3RkMCpzxCtdaeuxe5KTmODZCN1UJsNJ2+84Y9hR8bN6qA2DV/BFPXtyWIr4VG bsjHOEFfksxTOJwU/C10PdijX4iZrtMUkJLG9FZDDCdAxxiOJXXB2F4xglj+T92dd2VD ret4tWRp23GHG28n74CA0frO6JiOUVY6wwvU15wgDQJK0NwU5n4E7YJs8yxMY5UbsnFK ZNQCJo9csBrcghCE1iZR5eAxCz5VWZGES/5YIV2lI4x/a5uQZkdSL+UKh1fPmo+rVUnU dOfNA+DmsQjmDHPwd8gNQYm9RDLxRD/7W8cnT6pmYxRIW1nDR95Hhiqx/c2vTVQuADqH fwFA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:in-reply-to:references; bh=XqW5yuN+7kfHqiBsKAo7lL+/wqpeLvF3mwXBlkP7D6c=; b=LFN31DDKjXAGW5K4B36LI33uUzPOb/B9DzuGPDMRcjvtmkMnFTBP4cMUDSm4jCxS4y R88dK2wTDZB6yRrtvWwb5FDdMWOZH47OJoEjobhzGRiXO797oT3hw81IwYbr7RtG38Bp Yj0EYXWqLkI0bPKzYHKZaBMdAn56YpCciMvenhALQoNb5pyMFDx+4IdwoJtI2TQ72+1J RT/oX7AiIPlATuwaMi9R4HuP8zdaDXXq1bDjw5X3cueSARV1vFMTS1YIAVOZxJxEAQzT ma/wWIruqPQ6g91ADWpKxtS5ABSCob85+Rg13evWNN0jjm170fspEq0ohg+BdbADDib9 Nt2w== X-Gm-Message-State: AJaThX59tF0Fb4STU7M4inr4S5bfz0lPffhuoPo9pbBewSSNfqEi6Zau IBh7kCD0nGWXvyPsJsYlhy69NDcW X-Google-Smtp-Source: AGs4zMZwlTrOnsjO55x67MjqXogha7ktFx2e8wTNzekFJtwN2v5Jcrjh2+woevUGE85Ip/2EPfPJoA== X-Received: by 10.28.87.17 with SMTP id l17mr848530wmb.158.1510311523025; Fri, 10 Nov 2017 02:58:43 -0800 (PST) Received: from localhost (nat-35.starnet.cz. [178.255.168.35]) by smtp.gmail.com with ESMTPSA id 19sm1779046wmn.15.2017.11.10.02.58.42 (version=TLS1_2 cipher=AES128-SHA bits=128/128); Fri, 10 Nov 2017 02:58:42 -0800 (PST) From: Michal Simek To: u-boot@lists.denx.de Date: Fri, 10 Nov 2017 11:58:27 +0100 Message-Id: X-Mailer: git-send-email 1.9.1 In-Reply-To: References: In-Reply-To: References: Subject: [U-Boot] [PATCH 4/9] arm: zynq: Move ps7_* to separate file X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Extract ps7_* from spl code to prepare for extension. And also return value. Signed-off-by: Michal Simek --- arch/arm/mach-zynq/Makefile | 2 +- arch/arm/mach-zynq/include/mach/ps7_init_gpl.h | 14 +++++++++++++ arch/arm/mach-zynq/include/mach/sys_proto.h | 4 ---- arch/arm/mach-zynq/ps7_spl_init.c | 27 ++++++++++++++++++++++++++ arch/arm/mach-zynq/spl.c | 18 +---------------- 5 files changed, 43 insertions(+), 22 deletions(-) create mode 100644 arch/arm/mach-zynq/include/mach/ps7_init_gpl.h create mode 100644 arch/arm/mach-zynq/ps7_spl_init.c diff --git a/arch/arm/mach-zynq/Makefile b/arch/arm/mach-zynq/Makefile index bf29b4d396d3..e3f0117da563 100644 --- a/arch/arm/mach-zynq/Makefile +++ b/arch/arm/mach-zynq/Makefile @@ -15,4 +15,4 @@ obj-y += slcr.o obj-y += clk.o obj-y += lowlevel_init.o AFLAGS_lowlevel_init.o := -mfpu=neon -obj-$(CONFIG_SPL_BUILD) += spl.o +obj-$(CONFIG_SPL_BUILD) += spl.o ps7_spl_init.o diff --git a/arch/arm/mach-zynq/include/mach/ps7_init_gpl.h b/arch/arm/mach-zynq/include/mach/ps7_init_gpl.h new file mode 100644 index 000000000000..6e30108b23f4 --- /dev/null +++ b/arch/arm/mach-zynq/include/mach/ps7_init_gpl.h @@ -0,0 +1,14 @@ +/* + * (c) Copyright 2010-2017 Xilinx, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ASM_ARCH_PS7_INIT_GPL_H +#define _ASM_ARCH_PS7_INIT_GPL_H + +/* Called by spl.c */ +int ps7_init(void); +int ps7_post_config(void); + +#endif /* _ASM_ARCH_PS7_INIT_GPL_H */ diff --git a/arch/arm/mach-zynq/include/mach/sys_proto.h b/arch/arm/mach-zynq/include/mach/sys_proto.h index 0ef688309da3..af61352dd110 100644 --- a/arch/arm/mach-zynq/include/mach/sys_proto.h +++ b/arch/arm/mach-zynq/include/mach/sys_proto.h @@ -20,8 +20,4 @@ extern unsigned int zynq_get_silicon_version(void); int zynq_board_read_rom_ethaddr(unsigned char *ethaddr); -/* Driver extern functions */ -extern void ps7_init(void); -int ps7_post_config(void); - #endif /* _SYS_PROTO_H_ */ diff --git a/arch/arm/mach-zynq/ps7_spl_init.c b/arch/arm/mach-zynq/ps7_spl_init.c new file mode 100644 index 000000000000..6adf852578a6 --- /dev/null +++ b/arch/arm/mach-zynq/ps7_spl_init.c @@ -0,0 +1,27 @@ +/* + * (c) Copyright 2010-2017 Xilinx, Inc. All rights reserved. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include +#include +#include + +__weak int ps7_init(void) +{ + /* + * This function is overridden by the one in + * board/xilinx/zynq/(platform)/ps7_init_gpl.c, if it exists. + */ + return 0; +} + +__weak int ps7_post_config(void) +{ + /* + * This function is overridden by the one in + * board/xilinx/zynq/(platform)/ps7_init_gpl.c, if it exists. + */ + return 0; +} diff --git a/arch/arm/mach-zynq/spl.c b/arch/arm/mach-zynq/spl.c index e8added15567..1672fa05c26a 100644 --- a/arch/arm/mach-zynq/spl.c +++ b/arch/arm/mach-zynq/spl.c @@ -11,6 +11,7 @@ #include #include #include +#include DECLARE_GLOBAL_DATA_PTR; @@ -83,23 +84,6 @@ int spl_start_uboot(void) } #endif -__weak void ps7_init(void) -{ - /* - * This function is overridden by the one in - * board/xilinx/zynq/(platform)/ps7_init_gpl.c, if it exists. - */ -} - -__weak int ps7_post_config(void) -{ - /* - * This function is overridden by the one in - * board/xilinx/zynq/(platform)/ps7_init_gpl.c, if it exists. - */ - return 0; -} - void spl_board_prepare_for_boot(void) { ps7_post_config(); From patchwork Fri Nov 10 10:58:28 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Simek X-Patchwork-Id: 836676 X-Patchwork-Delegate: monstr@monstr.eu Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=monstr-eu.20150623.gappssmtp.com header.i=@monstr-eu.20150623.gappssmtp.com header.b="l8UENfN5"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3yYHF96501z9rvt for ; Fri, 10 Nov 2017 22:02:53 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 75EB9C21C71; Fri, 10 Nov 2017 11:00:50 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 1AD3CC21C8F; Fri, 10 Nov 2017 10:59:03 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 5F6A5C21CA5; Fri, 10 Nov 2017 10:58:48 +0000 (UTC) Received: from mail-wm0-f66.google.com (mail-wm0-f66.google.com [74.125.82.66]) by lists.denx.de (Postfix) with ESMTPS id C9EFBC21D6A for ; Fri, 10 Nov 2017 10:58:44 +0000 (UTC) Received: by mail-wm0-f66.google.com with SMTP id b189so1868106wmd.4 for ; Fri, 10 Nov 2017 02:58:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=monstr-eu.20150623.gappssmtp.com; s=20150623; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=BB6FQBN90kehzDiQX5EAYFNtipgIXX8IzHYbNcqqMXw=; b=l8UENfN55n9HyNxVTOintD7zfvZpaU8OQ0Pz4yYDEAOlcEqH0nRCHVksW40Q43KKVC 48yv6g2yKqtRQztg/CD0fOI4+xzoPa1l2y7v4dEQ2TEHk++DcOuHf1idzhdK2a0hrfMk KQaNzdlorghyg5Z1w/tk4kvuGPFId+ZhHKOllBsjOeVZDSKNli1lunPswAeJJwZW6OKT w6pW7cNnpxhSHrPUufyN0MmFMNwE6EvCtMy+UuvTSjaJYA3H8qbDDEIlE56VCmncQAew qKArk0Qfbr/YuphMvBAlutpeaDnY5YFtaMeoeD3aUP1Ivr3Wg8x7S2Eo12/Xn39J67D1 GQDg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:in-reply-to:references; bh=BB6FQBN90kehzDiQX5EAYFNtipgIXX8IzHYbNcqqMXw=; b=ktqcn4z4ucmLZEBUzZwdOhvA92tNXnwHM1u1zBQ/ZUETTicy0z9Pvl5BqJ332hKq2D o56+8IJCP7p73hlfjmijgEkbyTLP0l83C4W86gKDMHQ8NF3ry4kUICpScBpGLNIV1clS qToI+asJu3TkZZ2cfJ/JkbuUQFa0ivaljFLnWAeAFy8PF/ngvhz7rPpDJkD72ED3I4rd daFEVLR3LvwT/3MXeZ2+9fxoeQfNfjx4mynlONPwvh+YHfzmhXoi8Pz3DjyirnsdyoaH fQi7MN2hb8G5iIBdWKsJ4qONfbSRdz/w4/uoFeSgyinxXC1G8Dz/UFHmz7emSZNgo9yR PBBA== X-Gm-Message-State: AJaThX7xmaXeU3mrkBFFKYTsDyEcNziyt1sQoACiHzxx41DPijYfBT8B HErB0nvml7CZ6PIsnUjSGRodhfgW X-Google-Smtp-Source: AGs4zMYSkj7yV7lnxUGxZ7EV1mmDi6jm5elkfht6oD2ptItwKxSs7Ep8IjKqYq6DTz4MP7xhBCVnPw== X-Received: by 10.28.141.211 with SMTP id p202mr791136wmd.61.1510311524339; Fri, 10 Nov 2017 02:58:44 -0800 (PST) Received: from localhost (nat-35.starnet.cz. [178.255.168.35]) by smtp.gmail.com with ESMTPSA id u52sm10518551wrb.68.2017.11.10.02.58.43 (version=TLS1_2 cipher=AES128-SHA bits=128/128); Fri, 10 Nov 2017 02:58:43 -0800 (PST) From: Michal Simek To: u-boot@lists.denx.de Date: Fri, 10 Nov 2017 11:58:28 +0100 Message-Id: X-Mailer: git-send-email 1.9.1 In-Reply-To: References: In-Reply-To: References: Subject: [U-Boot] [PATCH 5/9] arm: zynq: Get rid of ps7_reset_apu() for syzygy board X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" There is no reason to call separate function. Signed-off-by: Michal Simek --- board/opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.c | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/board/opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.c b/board/opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.c index f2a757a5cfeb..5aa3951b8017 100644 --- a/board/opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.c +++ b/board/opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.c @@ -347,17 +347,11 @@ int ps7_post_config(void) return ps7_config(ps7_post_config_3_0); } - -int ps7_reset_apu(void) -{ - return ps7_config(ps7_reset_apu_3_0); -} - int ps7_init(void) { int ret; - ret = ps7_reset_apu(); + ret = ps7_config(ps7_reset_apu_3_0); if (ret != PS7_INIT_SUCCESS) return ret; From patchwork Fri Nov 10 10:58:29 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Simek X-Patchwork-Id: 836682 X-Patchwork-Delegate: monstr@monstr.eu Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=monstr-eu.20150623.gappssmtp.com header.i=@monstr-eu.20150623.gappssmtp.com header.b="PXIGXGew"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3yYHHz6h4kz9rvt for ; Fri, 10 Nov 2017 22:05:19 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 76E14C21D88; Fri, 10 Nov 2017 11:01:41 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id EEC92C21D5D; Fri, 10 Nov 2017 10:59:10 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id E01C7C21C2B; Fri, 10 Nov 2017 10:58:50 +0000 (UTC) Received: from mail-wr0-f193.google.com (mail-wr0-f193.google.com [209.85.128.193]) by lists.denx.de (Postfix) with ESMTPS id 84424C21DA2 for ; Fri, 10 Nov 2017 10:58:46 +0000 (UTC) Received: by mail-wr0-f193.google.com with SMTP id y9so8255158wrb.2 for ; Fri, 10 Nov 2017 02:58:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=monstr-eu.20150623.gappssmtp.com; s=20150623; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=l2m/xay1Th+TDXgGzQHwBk2thhPZqYVAB0TAsaEqjcQ=; b=PXIGXGewxbIrnYhj233+Iis9tgMBDkw6B+O/W/cJvAditQpuQttWMK3pOJKKinHqbv i/TAmm9kwQG4z0jDfUSTmhRnseEkesHTxwF/6Gz0eNstNbYsAQ5MoaX2+XMpMT6UbQGz j+VFuALiJk063adl/XUY14lESQ26mVIRwWXGqWrFXvqPotFDhwNIvN5RodWns1cBLZEF fPxJet86V7qBwMXodpyg1NpglXEd+l/R25XIKFiDwswt8ZfdMBgJj44I2d9o+gG8Wd8x sWNXHhOZw0KGyP2ibXrgzPwhzIvH2k3vgfNKbg9IXBYDGYzfl9Y1SM22jJ36VCo/ZlvR PE7A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:in-reply-to:references; bh=l2m/xay1Th+TDXgGzQHwBk2thhPZqYVAB0TAsaEqjcQ=; b=txUAbpqgv1Jtvw456P7SoS2X+0mvVhsTRinIo4hH0DdG8E1rvtYsT44p0mvCGxnXsE bVWgSoJuaIiFQYBRQOoenDCgSZmB9rjK1d/I42WR1h8FnENPIirLw6+sUMZQL7cHzB3F rlcquQC+8oMpyTz+4aNMyyvOSTvVxusUydeGPErp8KRGP4KjkZs3KgQKM8DrypQ+d5JU hTz0JueOSpspVU1/hXqZXvEy+y3gaG3bahd0tkOZM6Yj/BALF2w/DHyY4E4QvbiNSeLP Ou0/uVX5CoJ2+sjkM9onmqmslIQ/AFGnaIIoqWIr/65RuI7tytqW3HNgCrBDaeRg1AV1 MOBA== X-Gm-Message-State: AJaThX6aU7Xk/nvKIaZg0e4ruWHcEKZKp/lykNIcFX21WQ6Rle/dJDSV 56nmT/76amY1gEsEbYPtuoy6FO4Y X-Google-Smtp-Source: ABhQp+SvbLTqIqH9MR1rp45VUnw06fNCWM0t6PNv3nfx9469lRYqm23M4C9+aEry4Wh8gyvqo22r6w== X-Received: by 10.223.197.201 with SMTP id v9mr2844357wrg.82.1510311525846; Fri, 10 Nov 2017 02:58:45 -0800 (PST) Received: from localhost (nat-35.starnet.cz. [178.255.168.35]) by smtp.gmail.com with ESMTPSA id 4sm6036716wrh.7.2017.11.10.02.58.45 (version=TLS1_2 cipher=AES128-SHA bits=128/128); Fri, 10 Nov 2017 02:58:45 -0800 (PST) From: Michal Simek To: u-boot@lists.denx.de Date: Fri, 10 Nov 2017 11:58:29 +0100 Message-Id: X-Mailer: git-send-email 1.9.1 In-Reply-To: References: In-Reply-To: References: Subject: [U-Boot] [PATCH 6/9] arm: zynq: Move common ps7_init* initialization to arch code X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This patch is based on work done in topic board where the first address word also storing operation which should be done. This is reducing size of configuration data. This patch is not breaking an option to copy default ps7_init_gpl* files from hdf file but it is doing preparation for ps7_init* consolidation. The patch is also marking ps7_config as weak function. Signed-off-by: Michal Simek --- arch/arm/mach-zynq/include/mach/ps7_init_gpl.h | 28 ++++- arch/arm/mach-zynq/ps7_spl_init.c | 109 +++++++++++++++++++ board/topic/zynq/Makefile | 2 +- board/topic/zynq/ps7_init_common.c | 117 --------------------- board/topic/zynq/ps7_init_gpl.h | 34 ------ board/topic/zynq/zynq-topic-miami/ps7_init_gpl.c | 2 +- .../topic/zynq/zynq-topic-miamilite/ps7_init_gpl.c | 2 +- .../topic/zynq/zynq-topic-miamiplus/ps7_init_gpl.c | 2 +- 8 files changed, 140 insertions(+), 156 deletions(-) delete mode 100644 board/topic/zynq/ps7_init_common.c delete mode 100644 board/topic/zynq/ps7_init_gpl.h diff --git a/arch/arm/mach-zynq/include/mach/ps7_init_gpl.h b/arch/arm/mach-zynq/include/mach/ps7_init_gpl.h index 6e30108b23f4..4269f1fe46d4 100644 --- a/arch/arm/mach-zynq/include/mach/ps7_init_gpl.h +++ b/arch/arm/mach-zynq/include/mach/ps7_init_gpl.h @@ -1,5 +1,6 @@ /* - * (c) Copyright 2010-2017 Xilinx, Inc. All rights reserved. + * (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. + * (c) Copyright 2016 Topic Embedded Products. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -7,8 +8,33 @@ #ifndef _ASM_ARCH_PS7_INIT_GPL_H #define _ASM_ARCH_PS7_INIT_GPL_H +/* Opcode exit is 0 all the time */ +#define OPCODE_EXIT 0U +#define OPCODE_MASKWRITE 0U +#define OPCODE_MASKPOLL 1U +#define OPCODE_MASKDELAY 2U +#define OPCODE_ADDRESS_MASK (~3U) + +/* Sentinel */ +#define EMIT_EXIT() OPCODE_EXIT +/* Opcode is in lower 2 bits of address, address is always 4-byte aligned */ +#define EMIT_MASKWRITE(addr, mask, val) OPCODE_MASKWRITE | addr, mask, val +#define EMIT_MASKPOLL(addr, mask) OPCODE_MASKPOLL | addr, mask +#define EMIT_MASKDELAY(addr, mask) OPCODE_MASKDELAY | addr, mask + +/* Returns codes of ps7_init* */ +#define PS7_INIT_SUCCESS (0) +#define PS7_INIT_CORRUPT (1) +#define PS7_INIT_TIMEOUT (2) +#define PS7_POLL_FAILED_DDR_INIT (3) +#define PS7_POLL_FAILED_DMA (4) +#define PS7_POLL_FAILED_PLL (5) + /* Called by spl.c */ int ps7_init(void); int ps7_post_config(void); +/* Defined in ps7_init_common.c */ +int ps7_config(unsigned long *ps7_config_init); + #endif /* _ASM_ARCH_PS7_INIT_GPL_H */ diff --git a/arch/arm/mach-zynq/ps7_spl_init.c b/arch/arm/mach-zynq/ps7_spl_init.c index 6adf852578a6..180099577b04 100644 --- a/arch/arm/mach-zynq/ps7_spl_init.c +++ b/arch/arm/mach-zynq/ps7_spl_init.c @@ -1,5 +1,6 @@ /* * (c) Copyright 2010-2017 Xilinx, Inc. All rights reserved. + * (c) Copyright 2016 Topic Embedded Products. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -25,3 +26,111 @@ __weak int ps7_post_config(void) */ return 0; } + +/* For delay calculation using global registers*/ +#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200 +#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204 +#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208 +#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218 +#define APU_FREQ 666666666 + +#define PS7_MASK_POLL_TIME 100000000 + +/* IO accessors. No memory barriers desired. */ +static inline void iowrite(unsigned long val, unsigned long addr) +{ + __raw_writel(val, addr); +} + +static inline unsigned long ioread(unsigned long addr) +{ + return __raw_readl(addr); +} + +/* start timer */ +static void perf_start_clock(void) +{ + iowrite((1 << 0) | /* Timer Enable */ + (1 << 3) | /* Auto-increment */ + (0 << 8), /* Pre-scale */ + SCU_GLOBAL_TIMER_CONTROL); +} + +/* Compute mask for given delay in miliseconds*/ +static int get_number_of_cycles_for_delay(unsigned int delay) +{ + return (APU_FREQ / (2 * 1000)) * delay; +} + +/* stop timer */ +static void perf_disable_clock(void) +{ + iowrite(0, SCU_GLOBAL_TIMER_CONTROL); +} + +/* stop timer and reset timer count regs */ +static void perf_reset_clock(void) +{ + perf_disable_clock(); + iowrite(0, SCU_GLOBAL_TIMER_COUNT_L32); + iowrite(0, SCU_GLOBAL_TIMER_COUNT_U32); +} + +static void perf_reset_and_start_timer(void) +{ + perf_reset_clock(); + perf_start_clock(); +} + +int __weak ps7_config(unsigned long *ps7_config_init) +{ + unsigned long *ptr = ps7_config_init; + unsigned long opcode; + unsigned long addr; + unsigned long val; + unsigned long mask; + unsigned int numargs; + int i; + int delay; + + for (;;) { + opcode = ptr[0]; + if (opcode == OPCODE_EXIT) + return PS7_INIT_SUCCESS; + addr = (opcode & OPCODE_ADDRESS_MASK); + + switch (opcode & ~OPCODE_ADDRESS_MASK) { + case OPCODE_MASKWRITE: + numargs = 3; + mask = ptr[1]; + val = ptr[2]; + iowrite((ioread(addr) & ~mask) | (val & mask), addr); + break; + + case OPCODE_MASKPOLL: + numargs = 2; + mask = ptr[1]; + i = 0; + while (!(ioread(addr) & mask)) { + if (i == PS7_MASK_POLL_TIME) + return PS7_INIT_TIMEOUT; + i++; + } + break; + + case OPCODE_MASKDELAY: + numargs = 2; + mask = ptr[1]; + delay = get_number_of_cycles_for_delay(mask); + perf_reset_and_start_timer(); + while (ioread(addr) < delay) + ; + break; + + default: + return PS7_INIT_CORRUPT; + } + + ptr += numargs; + } +} diff --git a/board/topic/zynq/Makefile b/board/topic/zynq/Makefile index eaf59cd55c6c..789348207535 100644 --- a/board/topic/zynq/Makefile +++ b/board/topic/zynq/Makefile @@ -7,4 +7,4 @@ obj-y := board.o # Remove quotes hw-platform-y :=$(shell echo $(CONFIG_DEFAULT_DEVICE_TREE)) -obj-$(CONFIG_SPL_BUILD) += $(hw-platform-y)/ps7_init_gpl.o ps7_init_common.o +obj-$(CONFIG_SPL_BUILD) += $(hw-platform-y)/ps7_init_gpl.o diff --git a/board/topic/zynq/ps7_init_common.c b/board/topic/zynq/ps7_init_common.c deleted file mode 100644 index b1d45c242f80..000000000000 --- a/board/topic/zynq/ps7_init_common.c +++ /dev/null @@ -1,117 +0,0 @@ -/* - * (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. - * (c) Copyright 2016 Topic Embedded Products. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include "ps7_init_gpl.h" -#include - -/* For delay calculation using global registers*/ -#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200 -#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204 -#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208 -#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218 -#define APU_FREQ 666666666 - -#define PS7_MASK_POLL_TIME 100000000 - -/* IO accessors. No memory barriers desired. */ -static inline void iowrite(unsigned long val, unsigned long addr) -{ - __raw_writel(val, addr); -} - -static inline unsigned long ioread(unsigned long addr) -{ - return __raw_readl(addr); -} - -/* start timer */ -static void perf_start_clock(void) -{ - iowrite((1 << 0) | /* Timer Enable */ - (1 << 3) | /* Auto-increment */ - (0 << 8), /* Pre-scale */ - SCU_GLOBAL_TIMER_CONTROL); -} - -/* Compute mask for given delay in miliseconds*/ -static int get_number_of_cycles_for_delay(unsigned int delay) -{ - return (APU_FREQ / (2 * 1000)) * delay; -} - -/* stop timer */ -static void perf_disable_clock(void) -{ - iowrite(0, SCU_GLOBAL_TIMER_CONTROL); -} - -/* stop timer and reset timer count regs */ -static void perf_reset_clock(void) -{ - perf_disable_clock(); - iowrite(0, SCU_GLOBAL_TIMER_COUNT_L32); - iowrite(0, SCU_GLOBAL_TIMER_COUNT_U32); -} - -static void perf_reset_and_start_timer(void) -{ - perf_reset_clock(); - perf_start_clock(); -} - -int ps7_config(unsigned long *ps7_config_init) -{ - unsigned long *ptr = ps7_config_init; - unsigned long opcode; - unsigned long addr; - unsigned long val; - unsigned long mask; - unsigned int numargs; - int i; - int delay; - - for (;;) { - opcode = ptr[0]; - if (opcode == OPCODE_EXIT) - return PS7_INIT_SUCCESS; - addr = (opcode & OPCODE_ADDRESS_MASK); - - switch (opcode & ~OPCODE_ADDRESS_MASK) { - case OPCODE_MASKWRITE: - numargs = 3; - mask = ptr[1]; - val = ptr[2]; - iowrite((ioread(addr) & ~mask) | (val & mask), addr); - break; - - case OPCODE_MASKPOLL: - numargs = 2; - mask = ptr[1]; - i = 0; - while (!(ioread(addr) & mask)) { - if (i == PS7_MASK_POLL_TIME) - return PS7_INIT_TIMEOUT; - i++; - } - break; - - case OPCODE_MASKDELAY: - numargs = 2; - mask = ptr[1]; - delay = get_number_of_cycles_for_delay(mask); - perf_reset_and_start_timer(); - while (ioread(addr) < delay) - ; - break; - - default: - return PS7_INIT_CORRUPT; - } - - ptr += numargs; - } -} diff --git a/board/topic/zynq/ps7_init_gpl.h b/board/topic/zynq/ps7_init_gpl.h deleted file mode 100644 index ef719acabadb..000000000000 --- a/board/topic/zynq/ps7_init_gpl.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. - * (c) Copyright 2016 Topic Embedded Products. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#define OPCODE_EXIT 0U -#define OPCODE_MASKWRITE 0U -#define OPCODE_MASKPOLL 1U -#define OPCODE_MASKDELAY 2U -#define OPCODE_ADDRESS_MASK (~3U) - -/* Sentinel */ -#define EMIT_EXIT() OPCODE_EXIT -/* Opcode is in lower 2 bits of address, address is always 4-byte aligned */ -#define EMIT_MASKWRITE(addr, mask, val) OPCODE_MASKWRITE | addr, mask, val -#define EMIT_MASKPOLL(addr, mask) OPCODE_MASKPOLL | addr, mask -#define EMIT_MASKDELAY(addr, mask) OPCODE_MASKDELAY | addr, mask - -/* Returns codes of ps7_init* */ -#define PS7_INIT_SUCCESS (0) -#define PS7_INIT_CORRUPT (1) -#define PS7_INIT_TIMEOUT (2) -#define PS7_POLL_FAILED_DDR_INIT (3) -#define PS7_POLL_FAILED_DMA (4) -#define PS7_POLL_FAILED_PLL (5) - -/* Called by spl.c */ -int ps7_init(void); -int ps7_post_config(void); - -/* Defined in ps7_init_common.c */ -int ps7_config(unsigned long *ps7_config_init); diff --git a/board/topic/zynq/zynq-topic-miami/ps7_init_gpl.c b/board/topic/zynq/zynq-topic-miami/ps7_init_gpl.c index b195d7a25bf4..ceed04383f5f 100644 --- a/board/topic/zynq/zynq-topic-miami/ps7_init_gpl.c +++ b/board/topic/zynq/zynq-topic-miami/ps7_init_gpl.c @@ -5,7 +5,7 @@ * SPDX-License-Identifier: GPL-2.0+ */ -#include "../ps7_init_gpl.h" +#include static unsigned long ps7_pll_init_data_3_0[] = { EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU), diff --git a/board/topic/zynq/zynq-topic-miamilite/ps7_init_gpl.c b/board/topic/zynq/zynq-topic-miamilite/ps7_init_gpl.c index ec0cc7d19d0c..1205d19d9a35 100644 --- a/board/topic/zynq/zynq-topic-miamilite/ps7_init_gpl.c +++ b/board/topic/zynq/zynq-topic-miamilite/ps7_init_gpl.c @@ -5,7 +5,7 @@ * SPDX-License-Identifier: GPL-2.0+ */ -#include "../ps7_init_gpl.h" +#include static unsigned long ps7_pll_init_data_3_0[] = { EMIT_MASKWRITE(0xF8000008, 0x0000FFFFU, 0x0000DF0DU), diff --git a/board/topic/zynq/zynq-topic-miamiplus/ps7_init_gpl.c b/board/topic/zynq/zynq-topic-miamiplus/ps7_init_gpl.c index 5a923366eb78..f42632b7fab5 100644 --- a/board/topic/zynq/zynq-topic-miamiplus/ps7_init_gpl.c +++ b/board/topic/zynq/zynq-topic-miamiplus/ps7_init_gpl.c @@ -5,7 +5,7 @@ * SPDX-License-Identifier: GPL-2.0+ */ -#include "../ps7_init_gpl.h" +#include static unsigned long ps7_pll_init_data_3_0[] = { EMIT_MASKWRITE(0XF8000008, 0x0000FFFFU, 0x0000DF0DU), From patchwork Fri Nov 10 10:58:30 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Simek X-Patchwork-Id: 836680 X-Patchwork-Delegate: monstr@monstr.eu Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=monstr-eu.20150623.gappssmtp.com header.i=@monstr-eu.20150623.gappssmtp.com header.b="Fj9ciiOF"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3yYHH0520nz9rvt for ; Fri, 10 Nov 2017 22:04:28 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 69EFFC21DAA; Fri, 10 Nov 2017 11:01:07 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 631DBC21C93; Fri, 10 Nov 2017 10:59:05 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id B32B3C21D82; Fri, 10 Nov 2017 10:58:51 +0000 (UTC) Received: from mail-wr0-f194.google.com (mail-wr0-f194.google.com [209.85.128.194]) by lists.denx.de (Postfix) with ESMTPS id C9375C21DA6 for ; Fri, 10 Nov 2017 10:58:47 +0000 (UTC) Received: by mail-wr0-f194.google.com with SMTP id o88so8230304wrb.6 for ; Fri, 10 Nov 2017 02:58:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=monstr-eu.20150623.gappssmtp.com; s=20150623; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=U23Zn4ua195zvEsYQ7iqN7JC3gUYBQrI7UT3Jv4d5vs=; b=Fj9ciiOFuQKrRkBgWAZssalWqQq2bTPsVxeXL40U+n6/TwxtzX3nFiIMdy4v9mydGF a3DdDVQO94hNU+cV2dVCbpj8HNDgxpGhTkAS0oT/8v3SwTaCiFzdRTxvpkASE9F0l6Rh 3nnzCq+B8Uv/Ia/6SgajypiqRbe62dRhIsWr8eRmZRuwz/1xAwZz0hPrje+3/MU3oQaS Xiett877in+4XP5En430Pim968OnDTkG0m77iVdSd2d8Ka941AT1Tt4ZsHNwCSbkK380 keGxibZFnremx3VmJ8A3yrxVkylUvUSwDs9IpCF/+4D7Nss5gk0Eg/RJmm4uOmzf5bey ycTg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:in-reply-to:references; bh=U23Zn4ua195zvEsYQ7iqN7JC3gUYBQrI7UT3Jv4d5vs=; b=tPgF48keSkMWWlEV/AwsAZyXF6OHl8HGPaFd9737agZd7XLvcv+DG3hEwjs2ZYsRW5 5w7MwPVTJ4Nta34Re7erL0x/D94ujsah8QhaIyND2wu5J7dYIMwFx+L4rrYgd9xYWzJp 1luf8wDv1j3Zc6nfp1kbCtO6MhplNfHam2jWtmX4gvJ7eZz/RIqlnu654RtMmT9XUPqH p3kC3PfNILkOBXrUoXV9zx9+oHC1D1TCfdutP+qhA0qMSRfxQTjhcUx3JRCdE8x3yfvJ 3TPxy6nd0UHsOnMFOfCQICR319m28tjKWMgrYwPFY95t989QSsb5mRppvDkvAenHqEEN okUA== X-Gm-Message-State: AJaThX4BhdtnQ0T+OPrCSC0bJCu57swkrrWsrxH04QHLYDtSuImagykz ZPVYskukyuMifEiDkXMzsFxn1r97 X-Google-Smtp-Source: ABhQp+RdkuTaH8tdhhJyf47Om9OW0aIPgeSMQ6DwDgDRlN7OalfT6id0BCIkH+gn+t8k0Rg19dWZWA== X-Received: by 10.223.173.4 with SMTP id p4mr2764387wrc.209.1510311527324; Fri, 10 Nov 2017 02:58:47 -0800 (PST) Received: from localhost (nat-35.starnet.cz. [178.255.168.35]) by smtp.gmail.com with ESMTPSA id d40sm1067647wma.48.2017.11.10.02.58.46 (version=TLS1_2 cipher=AES128-SHA bits=128/128); Fri, 10 Nov 2017 02:58:46 -0800 (PST) From: Michal Simek To: u-boot@lists.denx.de Date: Fri, 10 Nov 2017 11:58:30 +0100 Message-Id: <687edc16f2bc11e454551be6eec7006dfac3c371.1510311500.git.michal.simek@xilinx.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: References: In-Reply-To: References: Subject: [U-Boot] [PATCH 7/9] arm: zynq: Add ps7GetSiliconVersion() to ps7_spl_init X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Unfortunately camelcase is coming from ps7_init* format. Signed-off-by: Michal Simek --- arch/arm/mach-zynq/include/mach/ps7_init_gpl.h | 6 ++++++ arch/arm/mach-zynq/ps7_spl_init.c | 6 ++++++ 2 files changed, 12 insertions(+) diff --git a/arch/arm/mach-zynq/include/mach/ps7_init_gpl.h b/arch/arm/mach-zynq/include/mach/ps7_init_gpl.h index 4269f1fe46d4..0398ba098286 100644 --- a/arch/arm/mach-zynq/include/mach/ps7_init_gpl.h +++ b/arch/arm/mach-zynq/include/mach/ps7_init_gpl.h @@ -30,6 +30,10 @@ #define PS7_POLL_FAILED_DMA (4) #define PS7_POLL_FAILED_PLL (5) +#define PCW_SILICON_VERSION_1 0 +#define PCW_SILICON_VERSION_2 1 +#define PCW_SILICON_VERSION_3 2 + /* Called by spl.c */ int ps7_init(void); int ps7_post_config(void); @@ -37,4 +41,6 @@ int ps7_post_config(void); /* Defined in ps7_init_common.c */ int ps7_config(unsigned long *ps7_config_init); +unsigned long ps7GetSiliconVersion(void); + #endif /* _ASM_ARCH_PS7_INIT_GPL_H */ diff --git a/arch/arm/mach-zynq/ps7_spl_init.c b/arch/arm/mach-zynq/ps7_spl_init.c index 180099577b04..069827880d10 100644 --- a/arch/arm/mach-zynq/ps7_spl_init.c +++ b/arch/arm/mach-zynq/ps7_spl_init.c @@ -7,6 +7,7 @@ #include #include +#include #include __weak int ps7_init(void) @@ -134,3 +135,8 @@ int __weak ps7_config(unsigned long *ps7_config_init) ptr += numargs; } } + +unsigned long __weak __maybe_unused ps7GetSiliconVersion(void) +{ + return zynq_get_silicon_version(); +} From patchwork Fri Nov 10 10:58:31 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Simek X-Patchwork-Id: 836679 X-Patchwork-Delegate: monstr@monstr.eu Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=monstr-eu.20150623.gappssmtp.com header.i=@monstr-eu.20150623.gappssmtp.com header.b="m7aocX9o"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3yYHGq6gfcz9rvt for ; Fri, 10 Nov 2017 22:04:19 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 7AA4FC21E0F; Fri, 10 Nov 2017 11:01:23 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.0 required=5.0 tests=RCVD_IN_MSPIKE_H3, RCVD_IN_MSPIKE_WL, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 5F333C21DFA; Fri, 10 Nov 2017 10:59:06 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 8EFFAC21D92; Fri, 10 Nov 2017 10:58:52 +0000 (UTC) Received: from mail-wm0-f65.google.com (mail-wm0-f65.google.com [74.125.82.65]) by lists.denx.de (Postfix) with ESMTPS id 57629C21DDB for ; Fri, 10 Nov 2017 10:58:49 +0000 (UTC) Received: by mail-wm0-f65.google.com with SMTP id p75so1894116wmg.3 for ; Fri, 10 Nov 2017 02:58:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=monstr-eu.20150623.gappssmtp.com; s=20150623; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=AIqhNZ9aRsH9VthozJNyE8NryYxotI6tVoZRqud7Sro=; b=m7aocX9o+jQyd+57uEGG/fxyD3a+xc+HQhuKM6cw44expG6+C6K73UsLXyihUJwdN8 BoPP2XA4SKMRdn9PaCSaHa48KKtYTvnk2TY5R2flC9jrTbTybuXKcJd9y9KSSIOwUm+2 Ht1fU7Wh5euDkuMsLuxb90odAyPRnY/Hn+oy2ja8uvlDzu9sTDVBSxDktdOAKSOJpDUV 5KAsVfP5J1CLyhY9N/1ugIMMEnbvEfqDf0aWg9WIksX/geBgGDAODRylXeTasqCSkDCR cqSlD6X0wLm9OaCNNxPZqPK9+kDCTPksTeUW3j9RrwNriJIaRdz8/HLKP7f2PIMclWoR xXEQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:in-reply-to:references; bh=AIqhNZ9aRsH9VthozJNyE8NryYxotI6tVoZRqud7Sro=; b=Tkkb9urZeIeJU6MpsVQ5ZIKwy079mqasC24g6ccI9Ie2Z3ucw2gRLs5Zw2lkT26Rt3 GVOMihEWx1iQV88P3nv9WWqXtAQpF1iiojqnZI++BKjfWe1Ex2mCmAcDk/0Q7SpG1bXb hs67ZjC50HALsMiU0pT2BlviIKVSgoIZpk6aH82CW59LndgzM7+KEsvcU7UNB9icLsPN iz/KSYQ21ih1QWR4mR6SUSoQna5UYr83BQpvPDdMALbYUxcSN6YWUPzHQwgmaWkbaKn8 tRrfAt8E9Q3GbP87mrf35u4uwsJCuvl4Kf2m11dyLz5lWqfFw81s6yBw5HkaQdrHBwo0 6ncA== X-Gm-Message-State: AJaThX6D61YSCgYt2fwq71WhjFy4u1aXdIcosgSIfkz4dfcTYqh/fnIV vnz8MUQ6cIvrxhLfV0wGRMZl4zzo X-Google-Smtp-Source: AGs4zMbOuH/5jzhrqx1E/VRgfZVr+Tx1sj6QTewlG4LUy1yyaOChhdkiwwzsU4+B79QHA1OD2S+mSQ== X-Received: by 10.28.113.135 with SMTP id d7mr119859wmi.152.1510311528771; Fri, 10 Nov 2017 02:58:48 -0800 (PST) Received: from localhost (nat-35.starnet.cz. [178.255.168.35]) by smtp.gmail.com with ESMTPSA id w76sm3899315wrc.79.2017.11.10.02.58.48 (version=TLS1_2 cipher=AES128-SHA bits=128/128); Fri, 10 Nov 2017 02:58:48 -0800 (PST) From: Michal Simek To: u-boot@lists.denx.de Date: Fri, 10 Nov 2017 11:58:31 +0100 Message-Id: <7b674acfd41d965346d7fa430c1e5d7c76c88daf.1510311500.git.michal.simek@xilinx.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: References: In-Reply-To: References: Subject: [U-Boot] [PATCH 8/9] arm: zynq: Convert EMIT_WRITE to EMIT_MASKWRITE X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" In case that board ps7_init* files contain EMIT_WRITE convert it to MASKWRITE because default format has to work only with last two bits. Signed-off-by: Michal Simek --- arch/arm/mach-zynq/include/mach/ps7_init_gpl.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/mach-zynq/include/mach/ps7_init_gpl.h b/arch/arm/mach-zynq/include/mach/ps7_init_gpl.h index 0398ba098286..af1d8cb46a71 100644 --- a/arch/arm/mach-zynq/include/mach/ps7_init_gpl.h +++ b/arch/arm/mach-zynq/include/mach/ps7_init_gpl.h @@ -22,6 +22,8 @@ #define EMIT_MASKPOLL(addr, mask) OPCODE_MASKPOLL | addr, mask #define EMIT_MASKDELAY(addr, mask) OPCODE_MASKDELAY | addr, mask +#define EMIT_WRITE(addr, val) EMIT_MASKWRITE(addr, 0, val) + /* Returns codes of ps7_init* */ #define PS7_INIT_SUCCESS (0) #define PS7_INIT_CORRUPT (1) From patchwork Fri Nov 10 10:58:32 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michal Simek X-Patchwork-Id: 836678 X-Patchwork-Delegate: monstr@monstr.eu Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=monstr-eu.20150623.gappssmtp.com header.i=@monstr-eu.20150623.gappssmtp.com header.b="nrhliWCJ"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3yYHGW4dWyz9rvt for ; Fri, 10 Nov 2017 22:04:03 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 263CCC21D76; Fri, 10 Nov 2017 11:02:19 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 94D38C21E10; Fri, 10 Nov 2017 10:59:33 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 40EE3C21DA0; Fri, 10 Nov 2017 10:58:56 +0000 (UTC) Received: from mail-wr0-f174.google.com (mail-wr0-f174.google.com [209.85.128.174]) by lists.denx.de (Postfix) with ESMTPS id 0810FC21D7E for ; Fri, 10 Nov 2017 10:58:52 +0000 (UTC) Received: by mail-wr0-f174.google.com with SMTP id 15so8243847wrb.5 for ; Fri, 10 Nov 2017 02:58:52 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=monstr-eu.20150623.gappssmtp.com; s=20150623; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :in-reply-to:references; bh=sdCPtSxYsWgqQHbMdXQPU94W0rG8e93BYpKVXISi3EA=; b=nrhliWCJlXOK5lXJTQxXMxBjkFWBb6E0Mdpq+4gfCYJqV5lBPS5kYZhfapSfjopYJA oeRUcKG24bzjeoVHpfVOdaYqLoBILDRbLaKPaeyRkP9KS6tMnS6U5IlH2k1EMI8nQMbs 473vQ+TzMNgIPaePYNttf4Vd656ei2jcCp2r1prEXoOnJUvqh4ZTj329K9G0dzOeULtb P+SF2604snZ+oJ54fYRQnftzTq9t6y9450Nkmqv28apaNdf8lAlUSXn0kR/B7jIg/OB6 n/7yH3eMgKokk1KHrX7qjv1oINWqtBwzlaSlu6028QQwWuWiuleE/USM3+NSClijXag0 wI5Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:in-reply-to:references; bh=sdCPtSxYsWgqQHbMdXQPU94W0rG8e93BYpKVXISi3EA=; b=cb5DylVzH3iOQdaAGcYWUBwxoJatTiPxSleUZ7Hbn3SgLKSgnz9PYgRcqnHIZJYMuW n8aNxrClgiQG9in5NMKaBwmiJRr+hRw6WwhJHBPXWAF+b6Vbsqo+/7XMfiICxuEqPZWy eXQlGR784RFqq2tZsAXz5+jCmx57L3sgyl/pwSFB/uunflgRrDLIMFztgJh9YiNYrA8O Ho5LNtwDXwNi4LVgWINSCqkNAwyknygeEy//mSTqSne/7TGaPetuNeTATWKSPG+hQZPC V4zqHkA3GaNUpO9SscnilexjGzF1o2+jih4xcjONpfdrmSvQkyKKqFfbvNbjieiGcIXi 3yPQ== X-Gm-Message-State: AJaThX4Uy2f+XRXA8uW7jnADNF38FXobHNdHgDI4Z6sGMvBlBr69bnk4 x4QiW2wCKux5l+FBZQ3xo9Ha4CQO X-Google-Smtp-Source: ABhQp+QO6yQpvJuKtt+ah4aovoN5orFVfi4lQDjvojwmYZkl5S9001AYTiZynbBaOWkHHxaRuKxD6A== X-Received: by 10.223.201.5 with SMTP id m5mr3329329wrh.68.1510311530784; Fri, 10 Nov 2017 02:58:50 -0800 (PST) Received: from localhost (nat-35.starnet.cz. [178.255.168.35]) by smtp.gmail.com with ESMTPSA id y99sm1040504wmh.0.2017.11.10.02.58.49 (version=TLS1_2 cipher=AES128-SHA bits=128/128); Fri, 10 Nov 2017 02:58:49 -0800 (PST) From: Michal Simek To: u-boot@lists.denx.de Date: Fri, 10 Nov 2017 11:58:32 +0100 Message-Id: <9f4581bc96585d50b6a561cee55d67ef10209c78.1510311500.git.michal.simek@xilinx.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: References: In-Reply-To: References: Subject: [U-Boot] [PATCH 9/9] arm: zynq: Convert all board to use arch ps7_init code X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Use generic implementation. It will also reduce config data size for converted boards. Signed-off-by: Michal Simek --- .../opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.c | 120 +------------- .../opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.h | 80 --------- board/xilinx/zynq/zynq-microzed/ps7_init_gpl.c | 173 +------------------- board/xilinx/zynq/zynq-microzed/ps7_init_gpl.h | 116 -------------- board/xilinx/zynq/zynq-zc702/ps7_init_gpl.c | 177 +------------------- board/xilinx/zynq/zynq-zc702/ps7_init_gpl.h | 116 -------------- board/xilinx/zynq/zynq-zc706/ps7_init_gpl.c | 173 +------------------- board/xilinx/zynq/zynq-zc706/ps7_init_gpl.h | 116 -------------- board/xilinx/zynq/zynq-zed/ps7_init_gpl.c | 173 +------------------- board/xilinx/zynq/zynq-zed/ps7_init_gpl.h | 116 -------------- board/xilinx/zynq/zynq-zybo/ps7_init_gpl.c | 178 +-------------------- board/xilinx/zynq/zynq-zybo/ps7_init_gpl.h | 97 ----------- 12 files changed, 6 insertions(+), 1629 deletions(-) delete mode 100644 board/opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.h delete mode 100644 board/xilinx/zynq/zynq-microzed/ps7_init_gpl.h delete mode 100644 board/xilinx/zynq/zynq-zc702/ps7_init_gpl.h delete mode 100644 board/xilinx/zynq/zynq-zc706/ps7_init_gpl.h delete mode 100644 board/xilinx/zynq/zynq-zed/ps7_init_gpl.h delete mode 100644 board/xilinx/zynq/zynq-zybo/ps7_init_gpl.h diff --git a/board/opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.c b/board/opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.c index 5aa3951b8017..3bd02f3c83ec 100644 --- a/board/opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.c +++ b/board/opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.c @@ -5,8 +5,7 @@ * SPDX-License-Identifier: GPL-2.0+ *****************************************************************************/ -#include "ps7_init_gpl.h" -#include "asm/io.h" +#include unsigned long ps7_pll_init_data_3_0[] = { EMIT_WRITE(0XF8000008, 0x0000DF0DU), @@ -255,92 +254,11 @@ unsigned long ps7_post_config_3_0[] = { EMIT_EXIT(), }; - unsigned long ps7_reset_apu_3_0[] = { EMIT_MASKWRITE(0xF8000244, 0x00000022U, 0x00000022U), EMIT_EXIT(), }; -#define PS7_MASK_POLL_TIME 100000000 - -static inline void iowrite(unsigned long val, unsigned long addr) -{ - __raw_writel(val, addr); -} - -static inline unsigned long ioread(unsigned long addr) -{ - return __raw_readl(addr); -} - -int ps7_config(unsigned long *ps7_config_init) -{ - unsigned long *ptr = ps7_config_init; - - unsigned long opcode; /* current instruction .. */ - unsigned long args[16]; /* no opcode has so many args ... */ - int numargs; /* number of arguments of this instruction */ - int j; /* general purpose index */ - - unsigned long addr; - unsigned long val, mask; - - int finish = -1; /* loop while this is negative ! */ - int i = 0; /* Timeout variable */ - - while (finish < 0) { - numargs = ptr[0] & 0xF; - opcode = ptr[0] >> 4; - - for (j = 0; j < numargs; j++) - args[j] = ptr[j + 1]; - ptr += numargs + 1; - - switch (opcode) { - case OPCODE_EXIT: - finish = PS7_INIT_SUCCESS; - break; - - case OPCODE_WRITE: - addr = args[0]; - val = args[1]; - iowrite(val, addr); - break; - - case OPCODE_MASKWRITE: - addr = args[0]; - mask = args[1]; - val = args[2]; - iowrite((val & mask) | (ioread(addr) & ~mask) , addr); - break; - - case OPCODE_MASKPOLL: - addr = args[0]; - mask = args[1]; - i = 0; - while (!(ioread(addr) & mask)) { - if (i == PS7_MASK_POLL_TIME) { - finish = PS7_INIT_TIMEOUT; - break; - } - i++; - } - break; - case OPCODE_MASKDELAY: - addr = args[0]; - mask = args[1]; - int delay = get_number_of_cycles_for_delay(mask); - perf_reset_and_start_timer(); - while (ioread(addr) < delay) - ; - break; - default: - finish = PS7_INIT_CORRUPT; - break; - } - } - return finish; -} int ps7_post_config(void) { @@ -377,39 +295,3 @@ int ps7_init(void) return PS7_INIT_SUCCESS; } -/* For delay calculation using global timer */ - -/* start timer */ -void perf_start_clock(void) -{ - iowrite((1 << 0) | /* Timer Enable */ - (1 << 3) | /* Auto-increment */ - (0 << 8), /* Pre-scale */ - SCU_GLOBAL_TIMER_CONTROL); -} - -/* stop timer and reset timer count regs */ -void perf_reset_clock(void) -{ - perf_disable_clock(); - iowrite(0, SCU_GLOBAL_TIMER_COUNT_L32); - iowrite(0, SCU_GLOBAL_TIMER_COUNT_U32); -} - -/* Compute mask for given delay in miliseconds*/ -int get_number_of_cycles_for_delay(unsigned int delay) -{ - return APU_FREQ * delay / (2 * 1000); -} - -/* stop timer */ -void perf_disable_clock(void) -{ - iowrite(0, SCU_GLOBAL_TIMER_CONTROL); -} - -void perf_reset_and_start_timer(void) -{ - perf_reset_clock(); - perf_start_clock(); -} diff --git a/board/opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.h b/board/opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.h deleted file mode 100644 index cffffa90bbc5..000000000000 --- a/board/opalkelly/zynq/zynq-syzygy-hub/ps7_init_gpl.h +++ /dev/null @@ -1,80 +0,0 @@ -/****************************************************************************** -* -* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. -* -* SPDX-License-Identifier: GPL-2.0+ -*****************************************************************************/ - -#ifdef __cplusplus -extern "C" { -#endif - -#define OPCODE_EXIT 0U -#define OPCODE_CLEAR 1U -#define OPCODE_WRITE 2U -#define OPCODE_MASKWRITE 3U -#define OPCODE_MASKPOLL 4U -#define OPCODE_MASKDELAY 5U - -/* Encode number of arguments in last nibble */ -#define EMIT_EXIT() ((OPCODE_EXIT << 4) | 0) -#define EMIT_WRITE(addr, val) ((OPCODE_WRITE << 4) | 2) , addr, val -#define EMIT_MASKWRITE(addr, mask, val) ((OPCODE_MASKWRITE << 4) | 3) ,\ - addr, mask, val -#define EMIT_MASKPOLL(addr, mask) ((OPCODE_MASKPOLL << 4) | 2) ,\ - addr, mask -#define EMIT_MASKDELAY(addr, mask) ((OPCODE_MASKDELAY << 4) | 2) ,\ - addr, mask - -/* Returns codes of PS7_Init */ -#define PS7_INIT_SUCCESS (0) -#define PS7_INIT_CORRUPT (1) -#define PS7_INIT_TIMEOUT (2) -#define PS7_POLL_FAILED_DDR_INIT (3) -#define PS7_POLL_FAILED_DMA (4) -#define PS7_POLL_FAILED_PLL (5) - -/* Freq of all peripherals */ - -#define APU_FREQ 650000000 -#define DDR_FREQ 525000000 -#define DCI_FREQ 10096154 -#define QSPI_FREQ 200000000 -#define SMC_FREQ 10000000 -#define ENET0_FREQ 125000000 -#define ENET1_FREQ 10000000 -#define USB0_FREQ 60000000 -#define USB1_FREQ 60000000 -#define SDIO_FREQ 100000000 -#define UART_FREQ 100000000 -#define SPI_FREQ 10000000 -#define I2C_FREQ 108333336 -#define WDT_FREQ 108333336 -#define TTC_FREQ 50000000 -#define CAN_FREQ 10000000 -#define PCAP_FREQ 200000000 -#define TPIU_FREQ 200000000 -#define FPGA0_FREQ 50000000 -#define FPGA1_FREQ 10000000 -#define FPGA2_FREQ 10000000 -#define FPGA3_FREQ 10000000 - - -/* For delay calculation using global registers*/ -#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200 -#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204 -#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208 -#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218 - -int ps7_config(unsigned long *); -int ps7_init(void); -int ps7_post_config(void); - -void perf_start_clock(void); -void perf_disable_clock(void); -void perf_reset_clock(void); -void perf_reset_and_start_timer(void); -int get_number_of_cycles_for_delay(unsigned int delay); -#ifdef __cplusplus -} -#endif diff --git a/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.c b/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.c index 58c31b8a50cf..5cf627d2233d 100644 --- a/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.c +++ b/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.c @@ -14,7 +14,7 @@ * *****************************************************************************/ -#include "ps7_init_gpl.h" +#include unsigned long ps7_pll_init_data_3_0[] = { // START: top @@ -12591,139 +12591,6 @@ unsigned long ps7_post_config_1_0[] = { #include "xil_io.h" -#define PS7_MASK_POLL_TIME 100000000 - -char* -getPS7MessageInfo(unsigned key) { - - char* err_msg = ""; - switch (key) { - case PS7_INIT_SUCCESS: err_msg = "PS7 initialization successful"; break; - case PS7_INIT_CORRUPT: err_msg = "PS7 init Data Corrupted"; break; - case PS7_INIT_TIMEOUT: err_msg = "PS7 init mask poll timeout"; break; - case PS7_POLL_FAILED_DDR_INIT: err_msg = "Mask Poll failed for DDR Init"; break; - case PS7_POLL_FAILED_DMA: err_msg = "Mask Poll failed for PLL Init"; break; - case PS7_POLL_FAILED_PLL: err_msg = "Mask Poll failed for DMA done bit"; break; - default: err_msg = "Undefined error status"; break; - } - - return err_msg; -} - -unsigned long -ps7GetSiliconVersion () { - // Read PS version from MCTRL register [31:28] - unsigned long mask = 0xF0000000; - unsigned long *addr = (unsigned long*) 0XF8007080; - unsigned long ps_version = (*addr & mask) >> 28; - return ps_version; -} - -void mask_write (unsigned long add , unsigned long mask, unsigned long val ) { - unsigned long *addr = (unsigned long*) add; - *addr = ( val & mask ) | ( *addr & ~mask); - //xil_printf("MaskWrite : 0x%x--> 0x%x \n \r" ,add, *addr); -} - - -int mask_poll(unsigned long add , unsigned long mask ) { - volatile unsigned long *addr = (volatile unsigned long*) add; - int i = 0; - while (!(*addr & mask)) { - if (i == PS7_MASK_POLL_TIME) { - return -1; - } - i++; - } - return 1; - //xil_printf("MaskPoll : 0x%x --> 0x%x \n \r" , add, *addr); -} - -unsigned long mask_read(unsigned long add , unsigned long mask ) { - unsigned long *addr = (unsigned long*) add; - unsigned long val = (*addr & mask); - //xil_printf("MaskRead : 0x%x --> 0x%x \n \r" , add, val); - return val; -} - - - -int -ps7_config(unsigned long * ps7_config_init) -{ - unsigned long *ptr = ps7_config_init; - - unsigned long opcode; // current instruction .. - unsigned long args[16]; // no opcode has so many args ... - int numargs; // number of arguments of this instruction - int j; // general purpose index - - volatile unsigned long *addr; // some variable to make code readable - unsigned long val,mask; // some variable to make code readable - - int finish = -1 ; // loop while this is negative ! - int i = 0; // Timeout variable - - while( finish < 0 ) { - numargs = ptr[0] & 0xF; - opcode = ptr[0] >> 4; - - for( j = 0 ; j < numargs ; j ++ ) - args[j] = ptr[j+1]; - ptr += numargs + 1; - - - switch ( opcode ) { - - case OPCODE_EXIT: - finish = PS7_INIT_SUCCESS; - break; - - case OPCODE_CLEAR: - addr = (unsigned long*) args[0]; - *addr = 0; - break; - - case OPCODE_WRITE: - addr = (unsigned long*) args[0]; - val = args[1]; - *addr = val; - break; - - case OPCODE_MASKWRITE: - addr = (unsigned long*) args[0]; - mask = args[1]; - val = args[2]; - *addr = ( val & mask ) | ( *addr & ~mask); - break; - - case OPCODE_MASKPOLL: - addr = (unsigned long*) args[0]; - mask = args[1]; - i = 0; - while (!(*addr & mask)) { - if (i == PS7_MASK_POLL_TIME) { - finish = PS7_INIT_TIMEOUT; - break; - } - i++; - } - break; - case OPCODE_MASKDELAY: - addr = (unsigned long*) args[0]; - mask = args[1]; - int delay = get_number_of_cycles_for_delay(mask); - perf_reset_and_start_timer(); - while ((*addr < delay)) { - } - break; - default: - finish = PS7_INIT_CORRUPT; - break; - } - } - return finish; -} unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0; unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0; @@ -12811,41 +12678,3 @@ ps7_init() -/* For delay calculation using global timer */ - -/* start timer */ - void perf_start_clock(void) -{ - *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = ((1 << 0) | // Timer Enable - (1 << 3) | // Auto-increment - (0 << 8) // Pre-scale - ); -} - -/* stop timer and reset timer count regs */ - void perf_reset_clock(void) -{ - perf_disable_clock(); - *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_L32 = 0; - *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_U32 = 0; -} - -/* Compute mask for given delay in miliseconds*/ -int get_number_of_cycles_for_delay(unsigned int delay) -{ - // GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x) - return (APU_FREQ*delay/(2*1000)); - -} - -/* stop timer */ - void perf_disable_clock(void) -{ - *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = 0; -} - -void perf_reset_and_start_timer() -{ - perf_reset_clock(); - perf_start_clock(); -} diff --git a/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.h b/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.h deleted file mode 100644 index d775a33d98cb..000000000000 --- a/board/xilinx/zynq/zynq-microzed/ps7_init_gpl.h +++ /dev/null @@ -1,116 +0,0 @@ - -/****************************************************************************** -* -* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. -* -* SPDX-License-Identifier: GPL-2.0+ -* -* -*******************************************************************************/ -/****************************************************************************/ -/** -* -* @file ps7_init.h -* -* This file can be included in FSBL code -* to get prototype of ps7_init() function -* and error codes -* -*****************************************************************************/ - -#ifdef __cplusplus -extern "C" { -#endif - - -//typedef unsigned int u32; - - -/** do we need to make this name more unique ? **/ -//extern u32 ps7_init_data[]; -extern unsigned long * ps7_ddr_init_data; -extern unsigned long * ps7_mio_init_data; -extern unsigned long * ps7_pll_init_data; -extern unsigned long * ps7_clock_init_data; -extern unsigned long * ps7_peripherals_init_data; - - - -#define OPCODE_EXIT 0U -#define OPCODE_CLEAR 1U -#define OPCODE_WRITE 2U -#define OPCODE_MASKWRITE 3U -#define OPCODE_MASKPOLL 4U -#define OPCODE_MASKDELAY 5U -#define NEW_PS7_ERR_CODE 1 - -/* Encode number of arguments in last nibble */ -#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 ) -#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr -#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val -#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val -#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask -#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask - -/* Returns codes of PS7_Init */ -#define PS7_INIT_SUCCESS (0) // 0 is success in good old C -#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now -#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out -#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init -#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit -#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init - - -/* Silicon Versions */ -#define PCW_SILICON_VERSION_1 0 -#define PCW_SILICON_VERSION_2 1 -#define PCW_SILICON_VERSION_3 2 - -/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */ -#define PS7_POST_CONFIG - -/* Freq of all peripherals */ - -#define APU_FREQ 666666687 -#define DDR_FREQ 533333374 -#define DCI_FREQ 10158731 -#define QSPI_FREQ 200000000 -#define SMC_FREQ 10000000 -#define ENET0_FREQ 125000000 -#define ENET1_FREQ 10000000 -#define USB0_FREQ 60000000 -#define USB1_FREQ 60000000 -#define SDIO_FREQ 50000000 -#define UART_FREQ 50000000 -#define SPI_FREQ 10000000 -#define I2C_FREQ 111111115 -#define WDT_FREQ 111111115 -#define TTC_FREQ 50000000 -#define CAN_FREQ 10000000 -#define PCAP_FREQ 200000000 -#define TPIU_FREQ 200000000 -#define FPGA0_FREQ 100000000 -#define FPGA1_FREQ 100000000 -#define FPGA2_FREQ 33333336 -#define FPGA3_FREQ 50000000 - - -/* For delay calculation using global registers*/ -#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200 -#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204 -#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208 -#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218 - -int ps7_config( unsigned long*); -int ps7_init(); -int ps7_post_config(); -char* getPS7MessageInfo(unsigned key); - -void perf_start_clock(void); -void perf_disable_clock(void); -void perf_reset_clock(void); -void perf_reset_and_start_timer(); -int get_number_of_cycles_for_delay(unsigned int delay); -#ifdef __cplusplus -} -#endif diff --git a/board/xilinx/zynq/zynq-zc702/ps7_init_gpl.c b/board/xilinx/zynq/zynq-zc702/ps7_init_gpl.c index 99cf4681f84b..fc325a6b028a 100644 --- a/board/xilinx/zynq/zynq-zc702/ps7_init_gpl.c +++ b/board/xilinx/zynq/zynq-zc702/ps7_init_gpl.c @@ -14,7 +14,7 @@ * *****************************************************************************/ -#include "ps7_init_gpl.h" +#include unsigned long ps7_pll_init_data_3_0[] = { // START: top @@ -12924,139 +12924,6 @@ unsigned long ps7_post_config_1_0[] = { #include "xil_io.h" -#define PS7_MASK_POLL_TIME 100000000 - -char* -getPS7MessageInfo(unsigned key) { - - char* err_msg = ""; - switch (key) { - case PS7_INIT_SUCCESS: err_msg = "PS7 initialization successful"; break; - case PS7_INIT_CORRUPT: err_msg = "PS7 init Data Corrupted"; break; - case PS7_INIT_TIMEOUT: err_msg = "PS7 init mask poll timeout"; break; - case PS7_POLL_FAILED_DDR_INIT: err_msg = "Mask Poll failed for DDR Init"; break; - case PS7_POLL_FAILED_DMA: err_msg = "Mask Poll failed for PLL Init"; break; - case PS7_POLL_FAILED_PLL: err_msg = "Mask Poll failed for DMA done bit"; break; - default: err_msg = "Undefined error status"; break; - } - - return err_msg; -} - -unsigned long -ps7GetSiliconVersion () { - // Read PS version from MCTRL register [31:28] - unsigned long mask = 0xF0000000; - unsigned long *addr = (unsigned long*) 0XF8007080; - unsigned long ps_version = (*addr & mask) >> 28; - return ps_version; -} - -void mask_write (unsigned long add , unsigned long mask, unsigned long val ) { - unsigned long *addr = (unsigned long*) add; - *addr = ( val & mask ) | ( *addr & ~mask); - //xil_printf("MaskWrite : 0x%x--> 0x%x \n \r" ,add, *addr); -} - - -int mask_poll(unsigned long add , unsigned long mask ) { - volatile unsigned long *addr = (volatile unsigned long*) add; - int i = 0; - while (!(*addr & mask)) { - if (i == PS7_MASK_POLL_TIME) { - return -1; - } - i++; - } - return 1; - //xil_printf("MaskPoll : 0x%x --> 0x%x \n \r" , add, *addr); -} - -unsigned long mask_read(unsigned long add , unsigned long mask ) { - unsigned long *addr = (unsigned long*) add; - unsigned long val = (*addr & mask); - //xil_printf("MaskRead : 0x%x --> 0x%x \n \r" , add, val); - return val; -} - - - -int -ps7_config(unsigned long * ps7_config_init) -{ - unsigned long *ptr = ps7_config_init; - - unsigned long opcode; // current instruction .. - unsigned long args[16]; // no opcode has so many args ... - int numargs; // number of arguments of this instruction - int j; // general purpose index - - volatile unsigned long *addr; // some variable to make code readable - unsigned long val,mask; // some variable to make code readable - - int finish = -1 ; // loop while this is negative ! - int i = 0; // Timeout variable - - while( finish < 0 ) { - numargs = ptr[0] & 0xF; - opcode = ptr[0] >> 4; - - for( j = 0 ; j < numargs ; j ++ ) - args[j] = ptr[j+1]; - ptr += numargs + 1; - - - switch ( opcode ) { - - case OPCODE_EXIT: - finish = PS7_INIT_SUCCESS; - break; - - case OPCODE_CLEAR: - addr = (unsigned long*) args[0]; - *addr = 0; - break; - - case OPCODE_WRITE: - addr = (unsigned long*) args[0]; - val = args[1]; - *addr = val; - break; - - case OPCODE_MASKWRITE: - addr = (unsigned long*) args[0]; - mask = args[1]; - val = args[2]; - *addr = ( val & mask ) | ( *addr & ~mask); - break; - - case OPCODE_MASKPOLL: - addr = (unsigned long*) args[0]; - mask = args[1]; - i = 0; - while (!(*addr & mask)) { - if (i == PS7_MASK_POLL_TIME) { - finish = PS7_INIT_TIMEOUT; - break; - } - i++; - } - break; - case OPCODE_MASKDELAY: - addr = (unsigned long*) args[0]; - mask = args[1]; - int delay = get_number_of_cycles_for_delay(mask); - perf_reset_and_start_timer(); - while ((*addr < delay)) { - } - break; - default: - finish = PS7_INIT_CORRUPT; - break; - } - } - return finish; -} unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0; unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0; @@ -13140,45 +13007,3 @@ ps7_init() //xil_printf ("\n PCW Silicon Version : %d.0", pcw_ver); return PS7_INIT_SUCCESS; } - - - - -/* For delay calculation using global timer */ - -/* start timer */ - void perf_start_clock(void) -{ - *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = ((1 << 0) | // Timer Enable - (1 << 3) | // Auto-increment - (0 << 8) // Pre-scale - ); -} - -/* stop timer and reset timer count regs */ - void perf_reset_clock(void) -{ - perf_disable_clock(); - *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_L32 = 0; - *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_U32 = 0; -} - -/* Compute mask for given delay in miliseconds*/ -int get_number_of_cycles_for_delay(unsigned int delay) -{ - // GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x) - return (APU_FREQ*delay/(2*1000)); - -} - -/* stop timer */ - void perf_disable_clock(void) -{ - *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = 0; -} - -void perf_reset_and_start_timer() -{ - perf_reset_clock(); - perf_start_clock(); -} diff --git a/board/xilinx/zynq/zynq-zc702/ps7_init_gpl.h b/board/xilinx/zynq/zynq-zc702/ps7_init_gpl.h deleted file mode 100644 index beb3b58b0c4d..000000000000 --- a/board/xilinx/zynq/zynq-zc702/ps7_init_gpl.h +++ /dev/null @@ -1,116 +0,0 @@ - -/****************************************************************************** -* -* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. -* -* SPDX-License-Identifier: GPL-2.0+ -* -* -*******************************************************************************/ -/****************************************************************************/ -/** -* -* @file ps7_init.h -* -* This file can be included in FSBL code -* to get prototype of ps7_init() function -* and error codes -* -*****************************************************************************/ - -#ifdef __cplusplus -extern "C" { -#endif - - -//typedef unsigned int u32; - - -/** do we need to make this name more unique ? **/ -//extern u32 ps7_init_data[]; -extern unsigned long * ps7_ddr_init_data; -extern unsigned long * ps7_mio_init_data; -extern unsigned long * ps7_pll_init_data; -extern unsigned long * ps7_clock_init_data; -extern unsigned long * ps7_peripherals_init_data; - - - -#define OPCODE_EXIT 0U -#define OPCODE_CLEAR 1U -#define OPCODE_WRITE 2U -#define OPCODE_MASKWRITE 3U -#define OPCODE_MASKPOLL 4U -#define OPCODE_MASKDELAY 5U -#define NEW_PS7_ERR_CODE 1 - -/* Encode number of arguments in last nibble */ -#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 ) -#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr -#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val -#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val -#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask -#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask - -/* Returns codes of PS7_Init */ -#define PS7_INIT_SUCCESS (0) // 0 is success in good old C -#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now -#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out -#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init -#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit -#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init - - -/* Silicon Versions */ -#define PCW_SILICON_VERSION_1 0 -#define PCW_SILICON_VERSION_2 1 -#define PCW_SILICON_VERSION_3 2 - -/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */ -#define PS7_POST_CONFIG - -/* Freq of all peripherals */ - -#define APU_FREQ 666666687 -#define DDR_FREQ 533333374 -#define DCI_FREQ 10158731 -#define QSPI_FREQ 200000000 -#define SMC_FREQ 10000000 -#define ENET0_FREQ 25000000 -#define ENET1_FREQ 10000000 -#define USB0_FREQ 60000000 -#define USB1_FREQ 60000000 -#define SDIO_FREQ 50000000 -#define UART_FREQ 50000000 -#define SPI_FREQ 10000000 -#define I2C_FREQ 111111115 -#define WDT_FREQ 111111115 -#define TTC_FREQ 50000000 -#define CAN_FREQ 23809523 -#define PCAP_FREQ 200000000 -#define TPIU_FREQ 200000000 -#define FPGA0_FREQ 50000000 -#define FPGA1_FREQ 50000000 -#define FPGA2_FREQ 50000000 -#define FPGA3_FREQ 50000000 - - -/* For delay calculation using global registers*/ -#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200 -#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204 -#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208 -#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218 - -int ps7_config( unsigned long*); -int ps7_init(); -int ps7_post_config(); -char* getPS7MessageInfo(unsigned key); - -void perf_start_clock(void); -void perf_disable_clock(void); -void perf_reset_clock(void); -void perf_reset_and_start_timer(); -int get_number_of_cycles_for_delay(unsigned int delay); -#ifdef __cplusplus -} -#endif diff --git a/board/xilinx/zynq/zynq-zc706/ps7_init_gpl.c b/board/xilinx/zynq/zynq-zc706/ps7_init_gpl.c index c45cc6a6e514..ca5490f0b0e3 100644 --- a/board/xilinx/zynq/zynq-zc706/ps7_init_gpl.c +++ b/board/xilinx/zynq/zynq-zc706/ps7_init_gpl.c @@ -14,7 +14,7 @@ * *****************************************************************************/ -#include "ps7_init_gpl.h" +#include unsigned long ps7_pll_init_data_3_0[] = { // START: top @@ -12831,139 +12831,6 @@ unsigned long ps7_post_config_1_0[] = { #include "xil_io.h" -#define PS7_MASK_POLL_TIME 100000000 - -char* -getPS7MessageInfo(unsigned key) { - - char* err_msg = ""; - switch (key) { - case PS7_INIT_SUCCESS: err_msg = "PS7 initialization successful"; break; - case PS7_INIT_CORRUPT: err_msg = "PS7 init Data Corrupted"; break; - case PS7_INIT_TIMEOUT: err_msg = "PS7 init mask poll timeout"; break; - case PS7_POLL_FAILED_DDR_INIT: err_msg = "Mask Poll failed for DDR Init"; break; - case PS7_POLL_FAILED_DMA: err_msg = "Mask Poll failed for PLL Init"; break; - case PS7_POLL_FAILED_PLL: err_msg = "Mask Poll failed for DMA done bit"; break; - default: err_msg = "Undefined error status"; break; - } - - return err_msg; -} - -unsigned long -ps7GetSiliconVersion () { - // Read PS version from MCTRL register [31:28] - unsigned long mask = 0xF0000000; - unsigned long *addr = (unsigned long*) 0XF8007080; - unsigned long ps_version = (*addr & mask) >> 28; - return ps_version; -} - -void mask_write (unsigned long add , unsigned long mask, unsigned long val ) { - unsigned long *addr = (unsigned long*) add; - *addr = ( val & mask ) | ( *addr & ~mask); - //xil_printf("MaskWrite : 0x%x--> 0x%x \n \r" ,add, *addr); -} - - -int mask_poll(unsigned long add , unsigned long mask ) { - volatile unsigned long *addr = (volatile unsigned long*) add; - int i = 0; - while (!(*addr & mask)) { - if (i == PS7_MASK_POLL_TIME) { - return -1; - } - i++; - } - return 1; - //xil_printf("MaskPoll : 0x%x --> 0x%x \n \r" , add, *addr); -} - -unsigned long mask_read(unsigned long add , unsigned long mask ) { - unsigned long *addr = (unsigned long*) add; - unsigned long val = (*addr & mask); - //xil_printf("MaskRead : 0x%x --> 0x%x \n \r" , add, val); - return val; -} - - - -int -ps7_config(unsigned long * ps7_config_init) -{ - unsigned long *ptr = ps7_config_init; - - unsigned long opcode; // current instruction .. - unsigned long args[16]; // no opcode has so many args ... - int numargs; // number of arguments of this instruction - int j; // general purpose index - - volatile unsigned long *addr; // some variable to make code readable - unsigned long val,mask; // some variable to make code readable - - int finish = -1 ; // loop while this is negative ! - int i = 0; // Timeout variable - - while( finish < 0 ) { - numargs = ptr[0] & 0xF; - opcode = ptr[0] >> 4; - - for( j = 0 ; j < numargs ; j ++ ) - args[j] = ptr[j+1]; - ptr += numargs + 1; - - - switch ( opcode ) { - - case OPCODE_EXIT: - finish = PS7_INIT_SUCCESS; - break; - - case OPCODE_CLEAR: - addr = (unsigned long*) args[0]; - *addr = 0; - break; - - case OPCODE_WRITE: - addr = (unsigned long*) args[0]; - val = args[1]; - *addr = val; - break; - - case OPCODE_MASKWRITE: - addr = (unsigned long*) args[0]; - mask = args[1]; - val = args[2]; - *addr = ( val & mask ) | ( *addr & ~mask); - break; - - case OPCODE_MASKPOLL: - addr = (unsigned long*) args[0]; - mask = args[1]; - i = 0; - while (!(*addr & mask)) { - if (i == PS7_MASK_POLL_TIME) { - finish = PS7_INIT_TIMEOUT; - break; - } - i++; - } - break; - case OPCODE_MASKDELAY: - addr = (unsigned long*) args[0]; - mask = args[1]; - int delay = get_number_of_cycles_for_delay(mask); - perf_reset_and_start_timer(); - while ((*addr < delay)) { - } - break; - default: - finish = PS7_INIT_CORRUPT; - break; - } - } - return finish; -} unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0; unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0; @@ -13051,41 +12918,3 @@ ps7_init() -/* For delay calculation using global timer */ - -/* start timer */ - void perf_start_clock(void) -{ - *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = ((1 << 0) | // Timer Enable - (1 << 3) | // Auto-increment - (0 << 8) // Pre-scale - ); -} - -/* stop timer and reset timer count regs */ - void perf_reset_clock(void) -{ - perf_disable_clock(); - *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_L32 = 0; - *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_U32 = 0; -} - -/* Compute mask for given delay in miliseconds*/ -int get_number_of_cycles_for_delay(unsigned int delay) -{ - // GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x) - return (APU_FREQ*delay/(2*1000)); - -} - -/* stop timer */ - void perf_disable_clock(void) -{ - *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = 0; -} - -void perf_reset_and_start_timer() -{ - perf_reset_clock(); - perf_start_clock(); -} diff --git a/board/xilinx/zynq/zynq-zc706/ps7_init_gpl.h b/board/xilinx/zynq/zynq-zc706/ps7_init_gpl.h deleted file mode 100644 index 694412a1e9d5..000000000000 --- a/board/xilinx/zynq/zynq-zc706/ps7_init_gpl.h +++ /dev/null @@ -1,116 +0,0 @@ - -/****************************************************************************** -* -* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. -* -* SPDX-License-Identifier: GPL-2.0+ -* -* -*******************************************************************************/ -/****************************************************************************/ -/** -* -* @file ps7_init.h -* -* This file can be included in FSBL code -* to get prototype of ps7_init() function -* and error codes -* -*****************************************************************************/ - -#ifdef __cplusplus -extern "C" { -#endif - - -//typedef unsigned int u32; - - -/** do we need to make this name more unique ? **/ -//extern u32 ps7_init_data[]; -extern unsigned long * ps7_ddr_init_data; -extern unsigned long * ps7_mio_init_data; -extern unsigned long * ps7_pll_init_data; -extern unsigned long * ps7_clock_init_data; -extern unsigned long * ps7_peripherals_init_data; - - - -#define OPCODE_EXIT 0U -#define OPCODE_CLEAR 1U -#define OPCODE_WRITE 2U -#define OPCODE_MASKWRITE 3U -#define OPCODE_MASKPOLL 4U -#define OPCODE_MASKDELAY 5U -#define NEW_PS7_ERR_CODE 1 - -/* Encode number of arguments in last nibble */ -#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 ) -#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr -#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val -#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val -#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask -#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask - -/* Returns codes of PS7_Init */ -#define PS7_INIT_SUCCESS (0) // 0 is success in good old C -#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now -#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out -#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init -#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit -#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init - - -/* Silicon Versions */ -#define PCW_SILICON_VERSION_1 0 -#define PCW_SILICON_VERSION_2 1 -#define PCW_SILICON_VERSION_3 2 - -/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */ -#define PS7_POST_CONFIG - -/* Freq of all peripherals */ - -#define APU_FREQ 666666687 -#define DDR_FREQ 533333374 -#define DCI_FREQ 10158731 -#define QSPI_FREQ 200000000 -#define SMC_FREQ 10000000 -#define ENET0_FREQ 25000000 -#define ENET1_FREQ 10000000 -#define USB0_FREQ 60000000 -#define USB1_FREQ 60000000 -#define SDIO_FREQ 50000000 -#define UART_FREQ 50000000 -#define SPI_FREQ 10000000 -#define I2C_FREQ 111111115 -#define WDT_FREQ 111111115 -#define TTC_FREQ 50000000 -#define CAN_FREQ 10000000 -#define PCAP_FREQ 200000000 -#define TPIU_FREQ 200000000 -#define FPGA0_FREQ 50000000 -#define FPGA1_FREQ 50000000 -#define FPGA2_FREQ 50000000 -#define FPGA3_FREQ 50000000 - - -/* For delay calculation using global registers*/ -#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200 -#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204 -#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208 -#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218 - -int ps7_config( unsigned long*); -int ps7_init(); -int ps7_post_config(); -char* getPS7MessageInfo(unsigned key); - -void perf_start_clock(void); -void perf_disable_clock(void); -void perf_reset_clock(void); -void perf_reset_and_start_timer(); -int get_number_of_cycles_for_delay(unsigned int delay); -#ifdef __cplusplus -} -#endif diff --git a/board/xilinx/zynq/zynq-zed/ps7_init_gpl.c b/board/xilinx/zynq/zynq-zed/ps7_init_gpl.c index 783fd9a30b78..54c803cfa659 100644 --- a/board/xilinx/zynq/zynq-zed/ps7_init_gpl.c +++ b/board/xilinx/zynq/zynq-zed/ps7_init_gpl.c @@ -14,7 +14,7 @@ * *****************************************************************************/ -#include "ps7_init_gpl.h" +#include unsigned long ps7_pll_init_data_3_0[] = { // START: top @@ -12489,139 +12489,6 @@ unsigned long ps7_post_config_1_0[] = { #include "xil_io.h" -#define PS7_MASK_POLL_TIME 100000000 - -char* -getPS7MessageInfo(unsigned key) { - - char* err_msg = ""; - switch (key) { - case PS7_INIT_SUCCESS: err_msg = "PS7 initialization successful"; break; - case PS7_INIT_CORRUPT: err_msg = "PS7 init Data Corrupted"; break; - case PS7_INIT_TIMEOUT: err_msg = "PS7 init mask poll timeout"; break; - case PS7_POLL_FAILED_DDR_INIT: err_msg = "Mask Poll failed for DDR Init"; break; - case PS7_POLL_FAILED_DMA: err_msg = "Mask Poll failed for PLL Init"; break; - case PS7_POLL_FAILED_PLL: err_msg = "Mask Poll failed for DMA done bit"; break; - default: err_msg = "Undefined error status"; break; - } - - return err_msg; -} - -unsigned long -ps7GetSiliconVersion () { - // Read PS version from MCTRL register [31:28] - unsigned long mask = 0xF0000000; - unsigned long *addr = (unsigned long*) 0XF8007080; - unsigned long ps_version = (*addr & mask) >> 28; - return ps_version; -} - -void mask_write (unsigned long add , unsigned long mask, unsigned long val ) { - unsigned long *addr = (unsigned long*) add; - *addr = ( val & mask ) | ( *addr & ~mask); - //xil_printf("MaskWrite : 0x%x--> 0x%x \n \r" ,add, *addr); -} - - -int mask_poll(unsigned long add , unsigned long mask ) { - volatile unsigned long *addr = (volatile unsigned long*) add; - int i = 0; - while (!(*addr & mask)) { - if (i == PS7_MASK_POLL_TIME) { - return -1; - } - i++; - } - return 1; - //xil_printf("MaskPoll : 0x%x --> 0x%x \n \r" , add, *addr); -} - -unsigned long mask_read(unsigned long add , unsigned long mask ) { - unsigned long *addr = (unsigned long*) add; - unsigned long val = (*addr & mask); - //xil_printf("MaskRead : 0x%x --> 0x%x \n \r" , add, val); - return val; -} - - - -int -ps7_config(unsigned long * ps7_config_init) -{ - unsigned long *ptr = ps7_config_init; - - unsigned long opcode; // current instruction .. - unsigned long args[16]; // no opcode has so many args ... - int numargs; // number of arguments of this instruction - int j; // general purpose index - - volatile unsigned long *addr; // some variable to make code readable - unsigned long val,mask; // some variable to make code readable - - int finish = -1 ; // loop while this is negative ! - int i = 0; // Timeout variable - - while( finish < 0 ) { - numargs = ptr[0] & 0xF; - opcode = ptr[0] >> 4; - - for( j = 0 ; j < numargs ; j ++ ) - args[j] = ptr[j+1]; - ptr += numargs + 1; - - - switch ( opcode ) { - - case OPCODE_EXIT: - finish = PS7_INIT_SUCCESS; - break; - - case OPCODE_CLEAR: - addr = (unsigned long*) args[0]; - *addr = 0; - break; - - case OPCODE_WRITE: - addr = (unsigned long*) args[0]; - val = args[1]; - *addr = val; - break; - - case OPCODE_MASKWRITE: - addr = (unsigned long*) args[0]; - mask = args[1]; - val = args[2]; - *addr = ( val & mask ) | ( *addr & ~mask); - break; - - case OPCODE_MASKPOLL: - addr = (unsigned long*) args[0]; - mask = args[1]; - i = 0; - while (!(*addr & mask)) { - if (i == PS7_MASK_POLL_TIME) { - finish = PS7_INIT_TIMEOUT; - break; - } - i++; - } - break; - case OPCODE_MASKDELAY: - addr = (unsigned long*) args[0]; - mask = args[1]; - int delay = get_number_of_cycles_for_delay(mask); - perf_reset_and_start_timer(); - while ((*addr < delay)) { - } - break; - default: - finish = PS7_INIT_CORRUPT; - break; - } - } - return finish; -} unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0; unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0; @@ -12709,41 +12576,3 @@ ps7_init() -/* For delay calculation using global timer */ - -/* start timer */ - void perf_start_clock(void) -{ - *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = ((1 << 0) | // Timer Enable - (1 << 3) | // Auto-increment - (0 << 8) // Pre-scale - ); -} - -/* stop timer and reset timer count regs */ - void perf_reset_clock(void) -{ - perf_disable_clock(); - *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_L32 = 0; - *(volatile unsigned int*)SCU_GLOBAL_TIMER_COUNT_U32 = 0; -} - -/* Compute mask for given delay in miliseconds*/ -int get_number_of_cycles_for_delay(unsigned int delay) -{ - // GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x) - return (APU_FREQ*delay/(2*1000)); - -} - -/* stop timer */ - void perf_disable_clock(void) -{ - *(volatile unsigned int*)SCU_GLOBAL_TIMER_CONTROL = 0; -} - -void perf_reset_and_start_timer() -{ - perf_reset_clock(); - perf_start_clock(); -} diff --git a/board/xilinx/zynq/zynq-zed/ps7_init_gpl.h b/board/xilinx/zynq/zynq-zed/ps7_init_gpl.h deleted file mode 100644 index 6d89863854e2..000000000000 --- a/board/xilinx/zynq/zynq-zed/ps7_init_gpl.h +++ /dev/null @@ -1,116 +0,0 @@ - -/****************************************************************************** -* -* (c) Copyright 2010-2014 Xilinx, Inc. All rights reserved. -* -* SPDX-License-Identifier: GPL-2.0+ -* -* -*******************************************************************************/ -/****************************************************************************/ -/** -* -* @file ps7_init.h -* -* This file can be included in FSBL code -* to get prototype of ps7_init() function -* and error codes -* -*****************************************************************************/ - -#ifdef __cplusplus -extern "C" { -#endif - - -//typedef unsigned int u32; - - -/** do we need to make this name more unique ? **/ -//extern u32 ps7_init_data[]; -extern unsigned long * ps7_ddr_init_data; -extern unsigned long * ps7_mio_init_data; -extern unsigned long * ps7_pll_init_data; -extern unsigned long * ps7_clock_init_data; -extern unsigned long * ps7_peripherals_init_data; - - - -#define OPCODE_EXIT 0U -#define OPCODE_CLEAR 1U -#define OPCODE_WRITE 2U -#define OPCODE_MASKWRITE 3U -#define OPCODE_MASKPOLL 4U -#define OPCODE_MASKDELAY 5U -#define NEW_PS7_ERR_CODE 1 - -/* Encode number of arguments in last nibble */ -#define EMIT_EXIT() ( (OPCODE_EXIT << 4 ) | 0 ) -#define EMIT_CLEAR(addr) ( (OPCODE_CLEAR << 4 ) | 1 ) , addr -#define EMIT_WRITE(addr,val) ( (OPCODE_WRITE << 4 ) | 2 ) , addr, val -#define EMIT_MASKWRITE(addr,mask,val) ( (OPCODE_MASKWRITE << 4 ) | 3 ) , addr, mask, val -#define EMIT_MASKPOLL(addr,mask) ( (OPCODE_MASKPOLL << 4 ) | 2 ) , addr, mask -#define EMIT_MASKDELAY(addr,mask) ( (OPCODE_MASKDELAY << 4 ) | 2 ) , addr, mask - -/* Returns codes of PS7_Init */ -#define PS7_INIT_SUCCESS (0) // 0 is success in good old C -#define PS7_INIT_CORRUPT (1) // 1 the data is corrupted, and slcr reg are in corrupted state now -#define PS7_INIT_TIMEOUT (2) // 2 when a poll operation timed out -#define PS7_POLL_FAILED_DDR_INIT (3) // 3 when a poll operation timed out for ddr init -#define PS7_POLL_FAILED_DMA (4) // 4 when a poll operation timed out for dma done bit -#define PS7_POLL_FAILED_PLL (5) // 5 when a poll operation timed out for pll sequence init - - -/* Silicon Versions */ -#define PCW_SILICON_VERSION_1 0 -#define PCW_SILICON_VERSION_2 1 -#define PCW_SILICON_VERSION_3 2 - -/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */ -#define PS7_POST_CONFIG - -/* Freq of all peripherals */ - -#define APU_FREQ 666666687 -#define DDR_FREQ 533333374 -#define DCI_FREQ 10158731 -#define QSPI_FREQ 200000000 -#define SMC_FREQ 10000000 -#define ENET0_FREQ 125000000 -#define ENET1_FREQ 10000000 -#define USB0_FREQ 60000000 -#define USB1_FREQ 60000000 -#define SDIO_FREQ 50000000 -#define UART_FREQ 50000000 -#define SPI_FREQ 10000000 -#define I2C_FREQ 111111115 -#define WDT_FREQ 111111115 -#define TTC_FREQ 50000000 -#define CAN_FREQ 10000000 -#define PCAP_FREQ 200000000 -#define TPIU_FREQ 200000000 -#define FPGA0_FREQ 100000000 -#define FPGA1_FREQ 142857132 -#define FPGA2_FREQ 50000000 -#define FPGA3_FREQ 50000000 - - -/* For delay calculation using global registers*/ -#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200 -#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204 -#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208 -#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218 - -int ps7_config( unsigned long*); -int ps7_init(); -int ps7_post_config(); -char* getPS7MessageInfo(unsigned key); - -void perf_start_clock(void); -void perf_disable_clock(void); -void perf_reset_clock(void); -void perf_reset_and_start_timer(); -int get_number_of_cycles_for_delay(unsigned int delay); -#ifdef __cplusplus -} -#endif diff --git a/board/xilinx/zynq/zynq-zybo/ps7_init_gpl.c b/board/xilinx/zynq/zynq-zybo/ps7_init_gpl.c index ed7c2a64e128..84625f07462e 100644 --- a/board/xilinx/zynq/zynq-zybo/ps7_init_gpl.c +++ b/board/xilinx/zynq/zynq-zybo/ps7_init_gpl.c @@ -4,7 +4,7 @@ * SPDX-License-Identifier: GPL-2.0+ */ -#include "ps7_init_gpl.h" +#include unsigned long ps7_pll_init_data_3_0[] = { /* START: top */ @@ -12666,145 +12666,6 @@ unsigned long ps7_post_config_1_0[] = { #include "xil_io.h" -#define PS7_MASK_POLL_TIME 100000000 - -char *getPS7MessageInfo(unsigned key) -{ - char *err_msg = ""; - switch (key) { - case PS7_INIT_SUCCESS: - err_msg = "PS7 initialization successful"; - break; - case PS7_INIT_CORRUPT: - err_msg = "PS7 init Data Corrupted"; - break; - case PS7_INIT_TIMEOUT: - err_msg = "PS7 init mask poll timeout"; - break; - case PS7_POLL_FAILED_DDR_INIT: - err_msg = "Mask Poll failed for DDR Init"; - break; - case PS7_POLL_FAILED_DMA: - err_msg = "Mask Poll failed for PLL Init"; - break; - case PS7_POLL_FAILED_PLL: - err_msg = "Mask Poll failed for DMA done bit"; - break; - default: - err_msg = "Undefined error status"; - break; - } - - return err_msg; -} - -unsigned long ps7GetSiliconVersion(void) -{ - /* Read PS version from MCTRL register [31:28] */ - unsigned long mask = 0xF0000000; - unsigned long *addr = (unsigned long *)0XF8007080; - unsigned long ps_version = (*addr & mask) >> 28; - return ps_version; -} - -void mask_write(unsigned long add, unsigned long mask, unsigned long val) -{ - unsigned long *addr = (unsigned long *)add; - *addr = (val & mask) | (*addr & ~mask); -} - -int mask_poll(unsigned long add, unsigned long mask) -{ - volatile unsigned long *addr = (volatile unsigned long *)add; - int i = 0; - while (!(*addr & mask)) { - if (i == PS7_MASK_POLL_TIME) - return -1; - i++; - } - return 1; -} - -unsigned long mask_read(unsigned long add, unsigned long mask) -{ - unsigned long *addr = (unsigned long *)add; - unsigned long val = (*addr & mask); - return val; -} - -int ps7_config(unsigned long *ps7_config_init) -{ - unsigned long *ptr = ps7_config_init; - - unsigned long opcode; /* current instruction .. */ - unsigned long args[16]; /* no opcode has so many args ... */ - int numargs; /* number of arguments of this instruction */ - int j; /* general purpose index */ - - volatile unsigned long *addr; /* some variable to make code readable */ - unsigned long val, mask; /* some variable to make code readable */ - - int finish = -1; /* loop while this is negative ! */ - int i = 0; /* Timeout variable */ - - while (finish < 0) { - numargs = ptr[0] & 0xF; - opcode = ptr[0] >> 4; - - for (j = 0; j < numargs; j++) - args[j] = ptr[j + 1]; - ptr += numargs + 1; - - switch (opcode) { - case OPCODE_EXIT: - finish = PS7_INIT_SUCCESS; - break; - - case OPCODE_CLEAR: - addr = (unsigned long *)args[0]; - *addr = 0; - break; - - case OPCODE_WRITE: - addr = (unsigned long *)args[0]; - val = args[1]; - *addr = val; - break; - - case OPCODE_MASKWRITE: - addr = (unsigned long *)args[0]; - mask = args[1]; - val = args[2]; - *addr = (val & mask) | (*addr & ~mask); - break; - - case OPCODE_MASKPOLL: - addr = (unsigned long *)args[0]; - mask = args[1]; - i = 0; - while (!(*addr & mask)) { - if (i == PS7_MASK_POLL_TIME) { - finish = PS7_INIT_TIMEOUT; - break; - } - i++; - } - break; - case OPCODE_MASKDELAY: - addr = (unsigned long *)args[0]; - mask = args[1]; - int delay = get_number_of_cycles_for_delay(mask); - perf_reset_and_start_timer(); - while ((*addr < delay)) - ; - break; - default: - finish = PS7_INIT_CORRUPT; - break; - } - } - return finish; -} unsigned long *ps7_mio_init_data = ps7_mio_init_data_3_0; unsigned long *ps7_pll_init_data = ps7_pll_init_data_3_0; @@ -12892,40 +12753,3 @@ int ps7_init(void) return PS7_INIT_SUCCESS; } -/* For delay calculation using global timer */ - -/* start timer */ -void perf_start_clock(void) -{ - *(volatile unsigned int *)SCU_GLOBAL_TIMER_CONTROL = ((1 << 0) | /* Timer Enable */ - (1 << 3) | /* Auto-increment */ - (0 << 8) /* Pre-scale */ - ); -} - -/* stop timer and reset timer count regs */ -void perf_reset_clock(void) -{ - perf_disable_clock(); - *(volatile unsigned int *)SCU_GLOBAL_TIMER_COUNT_L32 = 0; - *(volatile unsigned int *)SCU_GLOBAL_TIMER_COUNT_U32 = 0; -} - -/* Compute mask for given delay in miliseconds*/ -int get_number_of_cycles_for_delay(unsigned int delay) -{ - /* GTC is always clocked at 1/2 of the CPU frequency (CPU_3x2x) */ - return APU_FREQ * delay / (2 * 1000); -} - -/* stop timer */ -void perf_disable_clock(void) -{ - *(volatile unsigned int *)SCU_GLOBAL_TIMER_CONTROL = 0; -} - -void perf_reset_and_start_timer(void) -{ - perf_reset_clock(); - perf_start_clock(); -} diff --git a/board/xilinx/zynq/zynq-zybo/ps7_init_gpl.h b/board/xilinx/zynq/zynq-zybo/ps7_init_gpl.h deleted file mode 100644 index 929251afc5f2..000000000000 --- a/board/xilinx/zynq/zynq-zybo/ps7_init_gpl.h +++ /dev/null @@ -1,97 +0,0 @@ -/* - * Copyright (c) Xilinx, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifdef __cplusplus -extern "C" { -#endif - -/*typedef unsigned int u32; */ - -/** do we need to make this name more unique ? **/ -/*extern u32 ps7_init_data[]; */ -extern unsigned long *ps7_ddr_init_data; -extern unsigned long *ps7_mio_init_data; -extern unsigned long *ps7_pll_init_data; -extern unsigned long *ps7_clock_init_data; -extern unsigned long *ps7_peripherals_init_data; - -#define OPCODE_EXIT 0U -#define OPCODE_CLEAR 1U -#define OPCODE_WRITE 2U -#define OPCODE_MASKWRITE 3U -#define OPCODE_MASKPOLL 4U -#define OPCODE_MASKDELAY 5U -#define NEW_PS7_ERR_CODE 1 - -/* Encode number of arguments in last nibble */ -#define EMIT_EXIT() ((OPCODE_EXIT << 4) | 0) -#define EMIT_CLEAR(addr) ((OPCODE_CLEAR << 4) | 1) , addr -#define EMIT_WRITE(addr, val) ((OPCODE_WRITE << 4) | 2) , addr, val -#define EMIT_MASKWRITE(addr, mask, val) ((OPCODE_MASKWRITE << 4) | 3) , addr, mask, val -#define EMIT_MASKPOLL(addr, mask) ((OPCODE_MASKPOLL << 4) | 2) , addr, mask -#define EMIT_MASKDELAY(addr, mask) ((OPCODE_MASKDELAY << 4) | 2) , addr, mask - -/* Returns codes of PS7_Init */ -#define PS7_INIT_SUCCESS (0) /* 0 is success in good old C */ -#define PS7_INIT_CORRUPT (1) /* 1 the data is corrupted, and slcr reg are in corrupted state now */ -#define PS7_INIT_TIMEOUT (2) /* 2 when a poll operation timed out */ -#define PS7_POLL_FAILED_DDR_INIT (3) /* 3 when a poll operation timed out for ddr init */ -#define PS7_POLL_FAILED_DMA (4) /* 4 when a poll operation timed out for dma done bit */ -#define PS7_POLL_FAILED_PLL (5) /* 5 when a poll operation timed out for pll sequence init */ - -/* Silicon Versions */ -#define PCW_SILICON_VERSION_1 0 -#define PCW_SILICON_VERSION_2 1 -#define PCW_SILICON_VERSION_3 2 - -/* This flag to be used by FSBL to check whether ps7_post_config() proc exixts */ -#define PS7_POST_CONFIG - -/* Freq of all peripherals */ - -#define APU_FREQ 650000000 -#define DDR_FREQ 525000000 -#define DCI_FREQ 10096154 -#define QSPI_FREQ 200000000 -#define SMC_FREQ 10000000 -#define ENET0_FREQ 125000000 -#define ENET1_FREQ 10000000 -#define USB0_FREQ 60000000 -#define USB1_FREQ 60000000 -#define SDIO_FREQ 50000000 -#define UART_FREQ 100000000 -#define SPI_FREQ 10000000 -#define I2C_FREQ 108333336 -#define WDT_FREQ 108333336 -#define TTC_FREQ 50000000 -#define CAN_FREQ 10000000 -#define PCAP_FREQ 200000000 -#define TPIU_FREQ 200000000 -#define FPGA0_FREQ 100000000 -#define FPGA1_FREQ 142857132 -#define FPGA2_FREQ 200000000 -#define FPGA3_FREQ 50000000 - - -/* For delay calculation using global registers*/ -#define SCU_GLOBAL_TIMER_COUNT_L32 0xF8F00200 -#define SCU_GLOBAL_TIMER_COUNT_U32 0xF8F00204 -#define SCU_GLOBAL_TIMER_CONTROL 0xF8F00208 -#define SCU_GLOBAL_TIMER_AUTO_INC 0xF8F00218 - -int ps7_config(unsigned long *); -int ps7_init(void); -int ps7_post_config(void); -char *getPS7MessageInfo(unsigned key); - -void perf_start_clock(void); -void perf_disable_clock(void); -void perf_reset_clock(void); -void perf_reset_and_start_timer(void); -int get_number_of_cycles_for_delay(unsigned int delay); -#ifdef __cplusplus -} -#endif