From patchwork Fri Sep 6 10:11:23 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jerry-ch Chen X-Patchwork-Id: 1158927 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 46Ptf36S13z9s7T for ; Fri, 6 Sep 2019 20:12:27 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2390874AbfIFKM1 (ORCPT ); Fri, 6 Sep 2019 06:12:27 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:1479 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S2390594AbfIFKM0 (ORCPT ); Fri, 6 Sep 2019 06:12:26 -0400 X-UUID: a6ddb811795342f8b516dde5150b2329-20190906 X-UUID: a6ddb811795342f8b516dde5150b2329-20190906 Received: from mtkcas06.mediatek.inc [(172.21.101.30)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 1994393036; Fri, 06 Sep 2019 18:12:20 +0800 Received: from mtkcas09.mediatek.inc (172.21.101.178) by mtkmbs06n1.mediatek.inc (172.21.101.129) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Fri, 6 Sep 2019 18:11:57 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas09.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Fri, 6 Sep 2019 18:11:54 +0800 From: Jerry-ch Chen To: , , , , , CC: , , , , , , , , , , , , , , , , Jerry-ch Chen Subject: [RFC PATCH V3 1/3] dt-bindings: mt8183: Added FD dt-bindings Date: Fri, 6 Sep 2019 18:11:23 +0800 Message-ID: <20190906101125.3784-2-Jerry-Ch.chen@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20190906101125.3784-1-Jerry-Ch.chen@mediatek.com> References: <20190906101125.3784-1-Jerry-Ch.chen@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Jerry-ch Chen This patch adds DT binding documentation for the Face Detection (FD) unit of the Mediatek's mt8183 SoC. Signed-off-by: Jerry-ch Chen Reviewed-by: Rob Herring --- .../bindings/media/mediatek,mt8183-fd.txt | 34 +++++++++++++++++++ 1 file changed, 34 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/mediatek,mt8183-fd.txt diff --git a/Documentation/devicetree/bindings/media/mediatek,mt8183-fd.txt b/Documentation/devicetree/bindings/media/mediatek,mt8183-fd.txt new file mode 100644 index 000000000000..46464175b95a --- /dev/null +++ b/Documentation/devicetree/bindings/media/mediatek,mt8183-fd.txt @@ -0,0 +1,34 @@ +* Mediatek Face Detection Unit (FD) + +Face Detection (FD) unit is a typical memory-to-memory HW device. +It provides hardware accelerated face detection function, and it +is able to detect different poses of faces. FD will writre result +of detected face into memory as output. + +Required properties: +- compatible: "mediatek,mt8183-fd" +- mediatek,scp : the node of system control processor (SCP), see + Documentation/devicetree/bindings/remoteproc/mtk,scp.txt for details. +- iommus: should point to the 3 entries: M4U_PORT_CAM_FDVT_RP, + M4U_PORT_CAM_FDVT_WR and M4U_PORT_CAM_FDVT_RB. (Please see + Documentation/devicetree/bindings/iommu/mediatek,iommu.txt for details.) +- reg: Physical base address and length of the register space. +- interrupts: interrupt number to the cpu. +- clocks : must contain the FDVT clock, see + Documentation/devicetree/bindings/clock/clock-bindings.txt for details. +- clock-names: must be "fd". +- power-domain: must be "MT8183_POWER_DOMAIN_ISP". + +Example: + fd: fd@1502b000 { + compatible = "mediatek,mt8183-fd"; + mediatek,scp = <&scp>; + iommus = <&iommu M4U_PORT_CAM_FDVT_RP>, + <&iommu M4U_PORT_CAM_FDVT_WR>, + <&iommu M4U_PORT_CAM_FDVT_RB>; + reg = <0 0x1502b000 0 0x1000>; + interrupts = ; + clocks = <&imgsys CLK_IMG_FDVT>; + clock-names = "fd"; + power-domains = <&scpsys MT8183_POWER_DOMAIN_ISP>; + };