From patchwork Tue Sep 3 08:35:45 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Shaokun Zhang X-Patchwork-Id: 1156880 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-508206-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=hisilicon.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="ezczfgVw"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 46N0j970x2z9s7T for ; Tue, 3 Sep 2019 18:38:36 +1000 (AEST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:mime-version:content-type; q=dns; s=default; b=DhEL9VTd9+R/6tnWiiYEHmzZLz+P4xuAocHSxnPro5Lz8n0U+N xf8KVwY/BM2RNtAhklmYu1BIcf7UBO63RVAqd0IlRyynl6UBhsqaEnQW5irnZRcD kaLZDg82ccD1pvddiPTfln7hXqxYHLvm+Yj2FJ9WoAoYdrOZ8cIDDrF94= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:mime-version:content-type; s= default; bh=bpTI0i5aE0gZ87ZhyOIuQEOSvFA=; b=ezczfgVwm2HfT1HqwT4I XDazc+Y/kAw/CTAmiTOZUQMRKnwHBwuMyYrbtpyKVpcO87Blvv4esrhAafl8hK2K 1edL4+2t2jLVXaOfHViSMIWq0MaTjBcX7S5V+osgrvwXzfEo1k530KUOqFsrUDVW mxjSndbFZWv92QovOa6MFvc= Received: (qmail 20984 invoked by alias); 3 Sep 2019 08:38:29 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 20970 invoked by uid 89); 3 Sep 2019 08:38:29 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-25.1 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, KAM_SHORT, SPF_HELO_PASS, SPF_PASS autolearn=ham version=3.3.1 spammy= X-HELO: huawei.com Received: from szxga07-in.huawei.com (HELO huawei.com) (45.249.212.35) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 03 Sep 2019 08:38:27 +0000 Received: from DGGEMS405-HUB.china.huawei.com (unknown [172.30.72.59]) by Forcepoint Email with ESMTP id 0511BF3A78E7FC71727C; Tue, 3 Sep 2019 16:38:23 +0800 (CST) Received: from localhost.localdomain (10.67.212.132) by DGGEMS405-HUB.china.huawei.com (10.3.19.205) with Microsoft SMTP Server id 14.3.439.0; Tue, 3 Sep 2019 16:38:12 +0800 From: Shaokun Zhang To: CC: , , , , Shaokun Zhang Subject: [PATCH v2] [AARCH64] Add support for new control bits CTR_EL0.DIC and CTR_EL0.IDC Date: Tue, 3 Sep 2019 16:35:45 +0800 Message-ID: <1567499745-50548-1-git-send-email-zhangshaokun@hisilicon.com> MIME-Version: 1.0 X-IsSubscribed: yes The DCache clean & ICache invalidation requirements for instructions to be data coherence are discoverable through new fields in CTR_EL0. Let's support the two bits if they are enabled, the CPU core will not execute the unnecessary DCache clean or Icache Invalidation instructions. 2019-09-03 Shaokun Zhang * config/aarch64/sync-cache.c: Support CTR_EL0.IDC and CTR_EL0.DIC in __aarch64_sync_cache_range function. --- libgcc/config/aarch64/sync-cache.c | 57 ++++++++++++++++++++++++-------------- 1 file changed, 36 insertions(+), 21 deletions(-) diff --git a/libgcc/config/aarch64/sync-cache.c b/libgcc/config/aarch64/sync-cache.c index 791f5e42ff44..ea3da4be02b3 100644 --- a/libgcc/config/aarch64/sync-cache.c +++ b/libgcc/config/aarch64/sync-cache.c @@ -23,6 +23,9 @@ a copy of the GCC Runtime Library Exception along with this program; see the files COPYING3 and COPYING.RUNTIME respectively. If not, see . */ +#define CTR_IDC_SHIFT 28 +#define CTR_DIC_SHIFT 29 + void __aarch64_sync_cache_range (const void *, const void *); void @@ -41,32 +44,44 @@ __aarch64_sync_cache_range (const void *base, const void *end) icache_lsize = 4 << (cache_info & 0xF); dcache_lsize = 4 << ((cache_info >> 16) & 0xF); - /* Loop over the address range, clearing one cache line at once. - Data cache must be flushed to unification first to make sure the - instruction cache fetches the updated data. 'end' is exclusive, - as per the GNU definition of __clear_cache. */ + /* If CTR_EL0.IDC is enabled, Data cache clean to the Point of Unification is + not required for instruction to data coherence. */ + + if (((cache_info >> CTR_IDC_SHIFT) & 0x1) == 0x0) { + /* Loop over the address range, clearing one cache line at once. + Data cache must be flushed to unification first to make sure the + instruction cache fetches the updated data. 'end' is exclusive, + as per the GNU definition of __clear_cache. */ - /* Make the start address of the loop cache aligned. */ - address = (const char*) ((__UINTPTR_TYPE__) base - & ~ (__UINTPTR_TYPE__) (dcache_lsize - 1)); + /* Make the start address of the loop cache aligned. */ + address = (const char*) ((__UINTPTR_TYPE__) base + & ~ (__UINTPTR_TYPE__) (dcache_lsize - 1)); - for (; address < (const char *) end; address += dcache_lsize) - asm volatile ("dc\tcvau, %0" - : - : "r" (address) - : "memory"); + for (; address < (const char *) end; address += dcache_lsize) + asm volatile ("dc\tcvau, %0" + : + : "r" (address) + : "memory"); + } asm volatile ("dsb\tish" : : : "memory"); - /* Make the start address of the loop cache aligned. */ - address = (const char*) ((__UINTPTR_TYPE__) base - & ~ (__UINTPTR_TYPE__) (icache_lsize - 1)); + /* If CTR_EL0.DIC is enabled, Instruction cache cleaning to the Point of + Unification is not required for instruction to data coherence. */ + + if (((cache_info >> CTR_DIC_SHIFT) & 0x1) == 0x0) { + /* Make the start address of the loop cache aligned. */ + address = (const char*) ((__UINTPTR_TYPE__) base + & ~ (__UINTPTR_TYPE__) (icache_lsize - 1)); + + for (; address < (const char *) end; address += icache_lsize) + asm volatile ("ic\tivau, %0" + : + : "r" (address) + : "memory"); - for (; address < (const char *) end; address += icache_lsize) - asm volatile ("ic\tivau, %0" - : - : "r" (address) - : "memory"); + asm volatile ("dsb\tish" : : : "memory"); + } - asm volatile ("dsb\tish; isb" : : : "memory"); + asm volatile("isb" : : : "memory"); }