From patchwork Mon Sep 2 12:16:32 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Kyrill Tkachov X-Patchwork-Id: 1156612 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-508161-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=foss.arm.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="IvU/YrK9"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 46MTbV4Y8cz9s7T for ; Mon, 2 Sep 2019 22:16:52 +1000 (AEST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:to:cc :from:subject:message-id:date:mime-version:content-type; q=dns; s=default; b=mWYiLI69Y9KBHG5e0B78tFdjOHAKOjBwjqFB4ezxzNX/UP5Z65 TGqBVQizRGQBXVAiQmRvd+ZVoXNmlv6qPY28PHXY9uMqFjiL6j76cnmPInDNtGtB ZiBbGooRDF02MXF0T/f1+3YUiXAF24r+hNavl5+odX29S8By+fWL0zjFM= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:to:cc :from:subject:message-id:date:mime-version:content-type; s= default; bh=k/MPAUe1hJYxUNQqukTKIReJDFI=; b=IvU/YrK9j7D/KmCn5iH4 ge6aJz6BAmeUq7QjniJzCf0WpAN2VVC0EYGIUzHuVY+wrrPnz0yFc5UT1fBAdWYW t/Tik/nSFrnBuH4y9pG6Vnj/md5x6xSwDx8qPgAGsndBiuuJ9f/YitrzvokiQKod 4Tlx0lTuBinISdhHOg9R8A4= Received: (qmail 118901 invoked by alias); 2 Sep 2019 12:16:44 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 118890 invoked by uid 89); 2 Sep 2019 12:16:42 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-17.5 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, KAM_LOTSOFHASH autolearn=ham version=3.3.1 spammy=operate, tkachov, kyrill, sk:kyrylo X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.110.172) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 02 Sep 2019 12:16:41 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 5A832337; Mon, 2 Sep 2019 05:16:39 -0700 (PDT) Received: from [10.2.206.47] (e120808-lin.cambridge.arm.com [10.2.206.47]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id BC7323F246; Mon, 2 Sep 2019 05:16:38 -0700 (PDT) To: "gcc-patches@gcc.gnu.org" Cc: James Greenhalgh , Marcus Shawcroft , Richard Earnshaw From: Kyrill Tkachov Subject: [PATCH][AArch64] Add support for __jcvt intrinsic Message-ID: <9f35b469-1d5e-cd5e-6167-d00e271adc39@foss.arm.com> Date: Mon, 2 Sep 2019 13:16:32 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.7.1 MIME-Version: 1.0 Hi all, This patch implements the __jcvt ACLE intrinsic [1] that maps down to the FJCVTZS [2] instruction from Armv8.3-a. No fancy mode iterators or nothing. Just a single builtin, UNSPEC and define_insn and the associate plumbing. This patch also defines __ARM_FEATURE_JCVT to indicate when the intrinsic is available. Bootstrapped and tested on aarch64-none-linux-gnu. Ok for trunk? Thanks, Kyrill [1] https://developer.arm.com/docs/101028/latest/data-processing-intrinsics [2] https://developer.arm.com/docs/ddi0596/latest/simd-and-floating-point-instructions-alphabetic-order/fjcvtzs-floating-point-javascript-convert-to-signed-fixed-point-rounding-toward-zero 2019-09-02  Kyrylo Tkachov      * config/aarch64/aarch64.md (UNSPEC_FJCVTZS): Define.     (aarch64_fjcvtzs): New define_insn.     * config/aarch64/aarch64.h (TARGET_JSCVT): Define.     * config/aarch64/aarch64-builtins.c (aarch64_builtins):     Add AARCH64_JSCVT.     (aarch64_init_builtins): Initialize __builtin_aarch64_jcvtzs.     (aarch64_expand_builtin): Handle AARCH64_JSCVT.     * config/aarch64/aarch64-c.c (aarch64_update_cpp_builtins): Define     __ARM_FEATURE_JCVT where appropriate.     * config/aarch64/arm_acle.h (__jcvt): Define. 2019-09-02  Kyrylo Tkachov      * gcc.target/aarch64/acle/jcvt_1.c: New test. diff --git a/gcc/config/aarch64/aarch64-builtins.c b/gcc/config/aarch64/aarch64-builtins.c index a20a2ae1acc1ea8951d899431b57be3bd8c9ad3e..9424916d2466aa9f014ce7c0a13667ccc8eeb9ed 100644 --- a/gcc/config/aarch64/aarch64-builtins.c +++ b/gcc/config/aarch64/aarch64-builtins.c @@ -438,6 +438,8 @@ enum aarch64_builtins /* Special cased Armv8.3-A Complex FMA by Lane quad Builtins. */ AARCH64_SIMD_FCMLA_LANEQ_BUILTIN_BASE, AARCH64_SIMD_FCMLA_LANEQ_BUILTINS + /* Builtin for Arm8.3-a Javascript conversion instruction. */ + AARCH64_JSCVT, /* TME builtins. */ AARCH64_TME_BUILTIN_TSTART, AARCH64_TME_BUILTIN_TCOMMIT, @@ -1150,6 +1152,12 @@ aarch64_init_builtins (void) aarch64_init_builtin_rsqrt (); aarch64_init_rng_builtins (); + tree ftype_jcvt + = build_function_type_list (intSI_type_node, double_type_node, NULL); + aarch64_builtin_decls[AARCH64_JSCVT] + = add_builtin_function ("__builtin_aarch64_jcvtzs", ftype_jcvt, + AARCH64_JSCVT, BUILT_IN_MD, NULL, NULL_TREE); + /* Initialize pointer authentication builtins which are backed by instructions in NOP encoding space. @@ -1739,6 +1747,16 @@ aarch64_expand_builtin (tree exp, return target; + case AARCH64_JSCVT: + arg0 = CALL_EXPR_ARG (exp, 0); + op0 = force_reg (DFmode, expand_normal (arg0)); + if (!target) + target = gen_reg_rtx (SImode); + else + target = force_reg (SImode, target); + emit_insn (GEN_FCN (CODE_FOR_aarch64_fjcvtzs) (target, op0)); + return target; + case AARCH64_SIMD_BUILTIN_FCMLA_LANEQ0_V2SF: case AARCH64_SIMD_BUILTIN_FCMLA_LANEQ90_V2SF: case AARCH64_SIMD_BUILTIN_FCMLA_LANEQ180_V2SF: diff --git a/gcc/config/aarch64/aarch64-c.c b/gcc/config/aarch64/aarch64-c.c index c05efeda820f4428eace6e57020eed1b288032e9..137aa18af4620d4cefce1dfe5d92e4df67a278ba 100644 --- a/gcc/config/aarch64/aarch64-c.c +++ b/gcc/config/aarch64/aarch64-c.c @@ -110,6 +110,7 @@ aarch64_update_cpp_builtins (cpp_reader *pfile) aarch64_def_or_undef (TARGET_CRC32, "__ARM_FEATURE_CRC32", pfile); aarch64_def_or_undef (TARGET_DOTPROD, "__ARM_FEATURE_DOTPROD", pfile); aarch64_def_or_undef (TARGET_COMPLEX, "__ARM_FEATURE_COMPLEX", pfile); + aarch64_def_or_undef (TARGET_JSCVT, "__ARM_FEATURE_JCVT", pfile); cpp_undef (pfile, "__AARCH64_CMODEL_TINY__"); cpp_undef (pfile, "__AARCH64_CMODEL_SMALL__"); diff --git a/gcc/config/aarch64/aarch64.h b/gcc/config/aarch64/aarch64.h index 67279b44198be1ea0e950c80504e948d3af504f9..de270e3bf818ea0a2096abc3529abf129d822e88 100644 --- a/gcc/config/aarch64/aarch64.h +++ b/gcc/config/aarch64/aarch64.h @@ -289,6 +289,9 @@ extern unsigned aarch64_architecture_version; /* ARMv8.3-A features. */ #define TARGET_ARMV8_3 (AARCH64_ISA_V8_3) +/* Javascript conversion instruction from Armv8.3-a. */ +#define TARGET_JSCVT (TARGET_FLOAT && AARCH64_ISA_V8_3) + /* Armv8.3-a Complex number extension to AdvSIMD extensions. */ #define TARGET_COMPLEX (TARGET_SIMD && TARGET_ARMV8_3) diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md index d933916e519feac38b79e6d42ff4f0a340de67c6..13e09e0a40aae9993b7a2f8f6c6e10a929994677 100644 --- a/gcc/config/aarch64/aarch64.md +++ b/gcc/config/aarch64/aarch64.md @@ -141,6 +141,7 @@ UNSPEC_CRC32X UNSPEC_FCVTZS UNSPEC_FCVTZU + UNSPEC_FJCVTZS UNSPEC_FRINT32Z UNSPEC_FRINT32X UNSPEC_FRINT64Z @@ -6925,6 +6926,15 @@ [(set_attr "length" "0")] ) +(define_insn "aarch64_fjcvtzs" + [(set (match_operand:SI 0 "register_operand" "=r") + (unspec:SI [(match_operand:DF 1 "register_operand" "w")] + UNSPEC_FJCVTZS))] + "TARGET_JSCVT" + "fjcvtzs\\t%w0, %d1" + [(set_attr "type" "f_cvtf2i")] +) + ;; Pointer authentication patterns are always provided. In architecture ;; revisions prior to ARMv8.3-A these HINT instructions operate as NOPs. ;; This lets the user write portable software which authenticates pointers diff --git a/gcc/config/aarch64/arm_acle.h b/gcc/config/aarch64/arm_acle.h index 0347d1d36a39d65ff264e2fbda45c4daad33a2c9..aa8f649e32da27bb514fd9cd969587244f1f5cb1 100644 --- a/gcc/config/aarch64/arm_acle.h +++ b/gcc/config/aarch64/arm_acle.h @@ -130,6 +130,16 @@ __ttest (void) #pragma GCC pop_options #endif +#pragma GCC push_options +#pragma GCC target ("arch=armv8.3-a") +__extension__ static __inline int32_t __attribute__ ((__always_inline__)) +__jcvt (double __a) +{ + return __builtin_aarch64_jcvtzs (__a); +} + +#pragma GCC pop_options + #pragma GCC push_options #pragma GCC target ("arch=armv8.5-a") __extension__ static __inline float __attribute__ ((__always_inline__)) diff --git a/gcc/testsuite/gcc.target/aarch64/acle/jcvt_1.c b/gcc/testsuite/gcc.target/aarch64/acle/jcvt_1.c new file mode 100644 index 0000000000000000000000000000000000000000..0c900b1b57c7f1416ed1e0355a5722228262ea99 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/acle/jcvt_1.c @@ -0,0 +1,15 @@ +/* Test the __jcvt ACLE intrinsic. */ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=armv8.3-a" } */ + +#include + +#ifdef __ARM_FEATURE_JCVT +int32_t +test_jcvt (double a) +{ + return __jcvt (a); +} +#endif + +/* { dg-final { scan-assembler-times "fjcvtzs\tw\[0-9\]+, d\[0-9\]+\n" 1 } } */