From patchwork Thu Nov 9 08:54:42 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Wu X-Patchwork-Id: 836227 X-Patchwork-Delegate: philipp.tomsich@theobroma-systems.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3yXcVr1bxmz9t5Q for ; Thu, 9 Nov 2017 19:57:24 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id CD446C21E54; Thu, 9 Nov 2017 08:56:19 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.0 required=5.0 tests=ALL_TRUSTED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 8D0E6C21DDF; Thu, 9 Nov 2017 08:56:10 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 5842EC21DA3; Thu, 9 Nov 2017 08:56:05 +0000 (UTC) Received: from localhost by lists.denx.de with SpamAssassin (version 3.4.0); Thu, 09 Nov 2017 08:56:05 +0000 From: David Wu To: philipp.tomsich@theobroma-systems.com, sjg@chromium.org Date: Thu, 9 Nov 2017 16:54:42 +0800 Message-Id: <1510217699-78401-2-git-send-email-david.wu@rock-chips.com> MIME-Version: 1.0 Cc: huangtao@rock-chips.com, andy.yan@rock-chips.com, David Wu , u-boot@lists.denx.de Subject: [U-Boot] [PATCH v2 01/18] rockchip: clk: Add mac clock set for rk3399 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Spam detection software, running on the system "lists.denx.de", has identified this incoming email as possible spam. The original message has been attached to this so you can view it or label similar future email. If you have any questions, see @@CONTACT_ADDRESS@@ for details. Content preview: Assuming mac_clk is fed by an external clock, set clk_rmii_src clock select control register from IO for rgmii interface. Signed-off-by: David Wu Acked-by: Philipp Tomsich Reviewed-by: Philipp Tomsich --- [...] Content analysis details: (5.7 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- 0.6 RCVD_IN_SORBS_WEB RBL: SORBS: sender is an abusable web server [58.22.7.114 listed in dnsbl.sorbs.net] 2.7 RCVD_IN_PSBL RBL: Received via a relay in PSBL [211.157.147.130 listed in psbl.surriel.com] 2.4 RCVD_IN_MSPIKE_L5 RBL: Very bad reputation (-5) [211.157.147.130 listed in bl.mailspike.net] 0.0 RCVD_IN_MSPIKE_BL Mailspike blacklisted Assuming mac_clk is fed by an external clock, set clk_rmii_src clock select control register from IO for rgmii interface. Signed-off-by: David Wu Acked-by: Philipp Tomsich Reviewed-by: Philipp Tomsich --- Changes in v2: None drivers/clk/rockchip/clk_rk3399.c | 21 +++++++++++++++++++-- 1 file changed, 19 insertions(+), 2 deletions(-) diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c index 6f85a38..93aa4ff 100644 --- a/drivers/clk/rockchip/clk_rk3399.c +++ b/drivers/clk/rockchip/clk_rk3399.c @@ -143,6 +143,14 @@ enum { ACLK_PERIHP_DIV_CON_SHIFT = 0, ACLK_PERIHP_DIV_CON_MASK = 0x1f, + /* CLKSEL_CON19 */ + MAC_DIV_CON_SHIFT = 8, + MAC_DIV_CON_MASK = GENMASK(10, 8), + RMII_EXTCLK_SHIFT = 4, + RMII_EXTCLK_MASK = BIT(4), + RMII_EXTCLK_SELECT_INT_DIV_CLK = 0, + RMII_EXTCLK_SELECT_EXT_CLK = BIT(4), + /* CLKSEL_CON21 */ ACLK_EMMC_PLL_SEL_SHIFT = 7, ACLK_EMMC_PLL_SEL_MASK = 0x1 << ACLK_EMMC_PLL_SEL_SHIFT, @@ -785,6 +793,16 @@ static ulong rk3399_ddr_set_clk(struct rk3399_cru *cru, return set_rate; } +static int rockchip_mac_set_clk(struct rk3399_cru *cru, + int periph, uint freq) +{ + /* Assuming mac_clk is fed by an external clock */ + rk_clrsetreg(&cru->clksel_con[19], RMII_EXTCLK_MASK, + RMII_EXTCLK_SELECT_EXT_CLK); + + return 0; +} + static ulong rk3399_saradc_get_clk(struct rk3399_cru *cru) { u32 div, val; @@ -869,8 +887,7 @@ static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate) ret = rk3399_mmc_set_clk(priv->cru, clk->id, rate); break; case SCLK_MAC: - /* nothing to do, as this is an external clock */ - ret = rate; + ret = rockchip_mac_set_clk(priv->cru, clk->id, rate); break; case SCLK_I2C1: case SCLK_I2C2: From patchwork Thu Nov 9 08:54:43 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Wu X-Patchwork-Id: 836229 X-Patchwork-Delegate: philipp.tomsich@theobroma-systems.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3yXcY310M7z9t5Q for ; Thu, 9 Nov 2017 19:59:19 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id BE277C21F32; Thu, 9 Nov 2017 08:56:53 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-1.0 required=5.0 tests=ALL_TRUSTED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 9366DC21E40; Thu, 9 Nov 2017 08:56:50 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id C7E52C21E40; Thu, 9 Nov 2017 08:56:14 +0000 (UTC) Received: from localhost by lists.denx.de with SpamAssassin (version 3.4.0); Thu, 09 Nov 2017 08:56:14 +0000 From: David Wu To: philipp.tomsich@theobroma-systems.com, sjg@chromium.org Date: Thu, 9 Nov 2017 16:54:43 +0800 Message-Id: <1510217699-78401-3-git-send-email-david.wu@rock-chips.com> MIME-Version: 1.0 Cc: huangtao@rock-chips.com, andy.yan@rock-chips.com, David Wu , u-boot@lists.denx.de Subject: [U-Boot] [PATCH v2 02/18] rockchip: dts: rk3399-evb: Change the tx/rx delay value for transmission quality X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Spam detection software, running on the system "lists.denx.de", has identified this incoming email as possible spam. The original message has been attached to this so you can view it or label similar future email. If you have any questions, see @@CONTACT_ADDRESS@@ for details. Content preview: Give the mac controller the correct tx-delay and rx-delay value for the rgmii mode transmission. If they are not matched, there would be Ethernet packets lost, the net feature may not work. Signed-off-by: David Wu Acked-by: Philipp Tomsich Reviewed-by: Philipp Tomsich --- [...] Content analysis details: (5.7 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- 2.7 RCVD_IN_PSBL RBL: Received via a relay in PSBL [211.157.147.130 listed in psbl.surriel.com] 0.6 RCVD_IN_SORBS_WEB RBL: SORBS: sender is an abusable web server [58.22.7.114 listed in dnsbl.sorbs.net] 2.4 RCVD_IN_MSPIKE_L5 RBL: Very bad reputation (-5) [211.157.147.130 listed in bl.mailspike.net] 0.0 RCVD_IN_MSPIKE_BL Mailspike blacklisted Give the mac controller the correct tx-delay and rx-delay value for the rgmii mode transmission. If they are not matched, there would be Ethernet packets lost, the net feature may not work. Signed-off-by: David Wu Acked-by: Philipp Tomsich Reviewed-by: Philipp Tomsich --- Changes in v2: None arch/arm/dts/rk3399-evb.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/dts/rk3399-evb.dts b/arch/arm/dts/rk3399-evb.dts index 0e5d8d7..ed5ef88 100644 --- a/arch/arm/dts/rk3399-evb.dts +++ b/arch/arm/dts/rk3399-evb.dts @@ -276,7 +276,7 @@ assigned-clock-parents = <&clkin_gmac>; pinctrl-names = "default"; pinctrl-0 = <&rgmii_pins>; - tx_delay = <0x10>; - rx_delay = <0x10>; + tx_delay = <0x28>; + rx_delay = <0x11>; status = "okay"; }; From patchwork Thu Nov 9 08:54:44 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Wu X-Patchwork-Id: 836228 X-Patchwork-Delegate: philipp.tomsich@theobroma-systems.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3yXcWF4QQLz9t5Q for ; Thu, 9 Nov 2017 19:57:45 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 4EC5FC21DE6; Thu, 9 Nov 2017 08:57:12 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: ** X-Spam-Status: No, score=3.0 required=5.0 tests=RCVD_IN_MSPIKE_BL, RCVD_IN_MSPIKE_L5,RCVD_IN_SORBS_WEB autolearn=no autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id CCA18C21E14; Thu, 9 Nov 2017 08:56:56 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id A4967C21D84; Thu, 9 Nov 2017 08:56:17 +0000 (UTC) Received: from lucky1.263xmail.com (lucky1.263xmail.com [211.157.147.135]) by lists.denx.de (Postfix) with ESMTPS id BA26DC21E35 for ; Thu, 9 Nov 2017 08:56:13 +0000 (UTC) Received: from david.wu?rock-chips.com (unknown [192.168.167.225]) by lucky1.263xmail.com (Postfix) with ESMTP id 0DEFE63CA; Thu, 9 Nov 2017 16:56:04 +0800 (CST) X-263anti-spam: KSV:0; X-MAIL-GRAY: 1 X-MAIL-DELIVERY: 0 X-KSVirus-check: 0 X-ABS-CHECKED: 4 Received: from localhost.localdomain (localhost [127.0.0.1]) by smtp.263.net (Postfix) with ESMTPA id 6972A3CA; Thu, 9 Nov 2017 16:56:02 +0800 (CST) X-RL-SENDER: david.wu@rock-chips.com X-FST-TO: philipp.tomsich@theobroma-systems.com X-SENDER-IP: 58.22.7.114 X-LOGIN-NAME: david.wu@rock-chips.com X-UNIQUE-TAG: <0b484c4ebc6614338e4bf21b83205268> X-ATTACHMENT-NUM: 0 X-SENDER: wdc@rock-chips.com X-DNS-TYPE: 0 Received: from unknown (unknown [58.22.7.114]) by smtp.263.net (Postfix) whith SMTP id 16675VQSJZL; Thu, 09 Nov 2017 16:56:03 +0800 (CST) From: David Wu To: philipp.tomsich@theobroma-systems.com, sjg@chromium.org Date: Thu, 9 Nov 2017 16:54:44 +0800 Message-Id: <1510217699-78401-4-git-send-email-david.wu@rock-chips.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1510217699-78401-1-git-send-email-david.wu@rock-chips.com> References: <1510217699-78401-1-git-send-email-david.wu@rock-chips.com> Cc: huangtao@rock-chips.com, andy.yan@rock-chips.com, David Wu , u-boot@lists.denx.de Subject: [U-Boot] [PATCH v2 03/18] rockchip: configs: Enable CONFIG_NET_RANDOM_ETHADDR for rk3288-evb X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" If the Ethernet address is not set, the network can't work, enable the random address config for default use. Signed-off-by: David Wu Acked-by: Philipp Tomsich Reviewed-by: Philipp Tomsich --- Changes in v2: None configs/evb-rk3288_defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/configs/evb-rk3288_defconfig b/configs/evb-rk3288_defconfig index e944f97..6c67509 100644 --- a/configs/evb-rk3288_defconfig +++ b/configs/evb-rk3288_defconfig @@ -32,6 +32,7 @@ CONFIG_SPL_PARTITION_UUIDS=y CONFIG_SPL_OF_CONTROL=y CONFIG_OF_SPL_REMOVE_PROPS="pinctrl-0 pinctrl-names clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_ENV_IS_IN_MMC=y +CONFIG_NET_RANDOM_ETHADDR=y CONFIG_REGMAP=y CONFIG_SPL_REGMAP=y CONFIG_SYSCON=y From patchwork Thu Nov 9 08:54:45 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Wu X-Patchwork-Id: 836230 X-Patchwork-Delegate: philipp.tomsich@theobroma-systems.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3yXcYY40lKz9t4c for ; Thu, 9 Nov 2017 19:59:45 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 30CE2C21F5F; Thu, 9 Nov 2017 08:57:32 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: ** X-Spam-Status: No, score=3.0 required=5.0 tests=RCVD_IN_MSPIKE_BL, RCVD_IN_MSPIKE_L5,RCVD_IN_SORBS_WEB autolearn=no autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 5C1D0C21E5B; Thu, 9 Nov 2017 08:57:31 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 51ABBC21E0C; Thu, 9 Nov 2017 08:56:15 +0000 (UTC) Received: from lucky1.263xmail.com (lucky1.263xmail.com [211.157.147.131]) by lists.denx.de (Postfix) with ESMTPS id EAF22C21D8C for ; Thu, 9 Nov 2017 08:56:11 +0000 (UTC) Received: from david.wu?rock-chips.com (unknown [192.168.167.225]) by lucky1.263xmail.com (Postfix) with ESMTP id 652BF96AC5; Thu, 9 Nov 2017 16:56:06 +0800 (CST) X-263anti-spam: KSV:0; X-MAIL-GRAY: 1 X-MAIL-DELIVERY: 0 X-KSVirus-check: 0 X-ABS-CHECKED: 4 Received: from localhost.localdomain (localhost [127.0.0.1]) by smtp.263.net (Postfix) with ESMTPA id DC8CA308; Thu, 9 Nov 2017 16:56:04 +0800 (CST) X-RL-SENDER: david.wu@rock-chips.com X-FST-TO: philipp.tomsich@theobroma-systems.com X-SENDER-IP: 58.22.7.114 X-LOGIN-NAME: david.wu@rock-chips.com X-UNIQUE-TAG: <7531dbd662bb6b8dc9bf93375148ccb8> X-ATTACHMENT-NUM: 0 X-SENDER: wdc@rock-chips.com X-DNS-TYPE: 0 Received: from unknown (unknown [58.22.7.114]) by smtp.263.net (Postfix) whith SMTP id 166751UNQAT; Thu, 09 Nov 2017 16:56:07 +0800 (CST) From: David Wu To: philipp.tomsich@theobroma-systems.com, sjg@chromium.org Date: Thu, 9 Nov 2017 16:54:45 +0800 Message-Id: <1510217699-78401-5-git-send-email-david.wu@rock-chips.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1510217699-78401-1-git-send-email-david.wu@rock-chips.com> References: <1510217699-78401-1-git-send-email-david.wu@rock-chips.com> Cc: huangtao@rock-chips.com, andy.yan@rock-chips.com, David Wu , u-boot@lists.denx.de Subject: [U-Boot] [PATCH v2 04/18] rockchip: grf_rv1108.h: Fix the grf offsets X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The last 4 grf registers offset of rv1108 are wrong, fix them for correct usage. Signed-off-by: David Wu Acked-by: Philipp Tomsich Reviewed-by: Simon Glass --- Changes in v2: - New patch arch/arm/include/asm/arch-rockchip/grf_rv1108.h | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/arm/include/asm/arch-rockchip/grf_rv1108.h b/arch/arm/include/asm/arch-rockchip/grf_rv1108.h index c816a5b..428cf6a 100644 --- a/arch/arm/include/asm/arch-rockchip/grf_rv1108.h +++ b/arch/arm/include/asm/arch-rockchip/grf_rv1108.h @@ -100,13 +100,17 @@ struct rv1108_grf { u32 reserved14[2]; u32 dma_con0; u32 dma_con1; - u32 reserved15[539]; + u32 reserved15[59]; u32 uoc_status; + u32 reserved16[2]; u32 host_status; + u32 reserved17[59]; u32 gmac_con0; + u32 reserved18[191]; u32 chip_id; }; -check_member(rv1108_grf, chip_id, 0xf90); + +check_member(rv1108_grf, chip_id, 0x0c00); /* GRF_GPIO1B_IOMUX */ enum { From patchwork Thu Nov 9 09:01:12 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Wu X-Patchwork-Id: 836231 X-Patchwork-Delegate: philipp.tomsich@theobroma-systems.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3yXccQ5ZVBz9s71 for ; Thu, 9 Nov 2017 20:02:14 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 7AE0CC21F29; Thu, 9 Nov 2017 09:02:13 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.2 required=5.0 tests=ALL_TRUSTED, UPPERCASE_50_75 autolearn=no autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id C2971C21E41; Thu, 9 Nov 2017 09:02:06 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 5B087C21DCA; Thu, 9 Nov 2017 09:02:05 +0000 (UTC) Received: from localhost by lists.denx.de with SpamAssassin (version 3.4.0); Thu, 09 Nov 2017 09:02:05 +0000 From: David Wu To: philipp.tomsich@theobroma-systems.com, sjg@chromium.org Date: Thu, 9 Nov 2017 17:01:12 +0800 Message-Id: <1510218072-78641-1-git-send-email-david.wu@rock-chips.com> MIME-Version: 1.0 Cc: huangtao@rock-chips.com, joe.hershberger@ni.com, u-boot@lists.denx.de, David Wu , andy.yan@rock-chips.com Subject: [U-Boot] [PATCH v2 05/18] rockchip: pinctrl: rv1108: Move the iomux definitions into pinctrl-driver X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Spam detection software, running on the system "lists.denx.de", has identified this incoming email as possible spam. The original message has been attached to this so you can view it or label similar future email. If you have any questions, see @@CONTACT_ADDRESS@@ for details. Content preview: If we include both the rk3288_grf.h and rv1108_grf.h, it will cause the conflicts of redefinition. Clean the iomux definitions at grf_rv1108.h, and move them into pinctrl-driver. Signed-off-by: David Wu --- [...] Content analysis details: (6.5 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- 2.7 RCVD_IN_PSBL RBL: Received via a relay in PSBL [211.157.147.130 listed in psbl.surriel.com] 0.6 RCVD_IN_SORBS_WEB RBL: SORBS: sender is an abusable web server [58.22.7.114 listed in dnsbl.sorbs.net] 2.4 RCVD_IN_MSPIKE_L5 RBL: Very bad reputation (-5) [211.157.147.130 listed in bl.mailspike.net] 0.8 UPPERCASE_50_75 message body is 50-75% uppercase 0.0 RCVD_IN_MSPIKE_BL Mailspike blacklisted If we include both the rk3288_grf.h and rv1108_grf.h, it will cause the conflicts of redefinition. Clean the iomux definitions at grf_rv1108.h, and move them into pinctrl-driver. Signed-off-by: David Wu Acked-by: Philipp Tomsich Reviewed-by: Philipp Tomsich --- Changes in v2: - New patch arch/arm/include/asm/arch-rockchip/grf_rv1108.h | 399 ------------------------ board/rockchip/evb_rv1108/evb_rv1108.c | 15 + drivers/pinctrl/rockchip/pinctrl_rv1108.c | 399 ++++++++++++++++++++++++ 3 files changed, 414 insertions(+), 399 deletions(-) diff --git a/arch/arm/include/asm/arch-rockchip/grf_rv1108.h b/arch/arm/include/asm/arch-rockchip/grf_rv1108.h index 428cf6a..76e742b 100644 --- a/arch/arm/include/asm/arch-rockchip/grf_rv1108.h +++ b/arch/arm/include/asm/arch-rockchip/grf_rv1108.h @@ -111,403 +111,4 @@ struct rv1108_grf { }; check_member(rv1108_grf, chip_id, 0x0c00); - -/* GRF_GPIO1B_IOMUX */ -enum { - GPIO1B7_SHIFT = 14, - GPIO1B7_MASK = 3 << GPIO1B7_SHIFT, - GPIO1B7_GPIO = 0, - GPIO1B7_LCDC_D12, - GPIO1B7_I2S_SDIO2_M0, - GPIO1B7_GMAC_RXDV, - - GPIO1B6_SHIFT = 12, - GPIO1B6_MASK = 3 << GPIO1B6_SHIFT, - GPIO1B6_GPIO = 0, - GPIO1B6_LCDC_D13, - GPIO1B6_I2S_LRCLKTX_M0, - GPIO1B6_GMAC_RXD1, - - GPIO1B5_SHIFT = 10, - GPIO1B5_MASK = 3 << GPIO1B5_SHIFT, - GPIO1B5_GPIO = 0, - GPIO1B5_LCDC_D14, - GPIO1B5_I2S_SDIO1_M0, - GPIO1B5_GMAC_RXD0, - - GPIO1B4_SHIFT = 8, - GPIO1B4_MASK = 3 << GPIO1B4_SHIFT, - GPIO1B4_GPIO = 0, - GPIO1B4_LCDC_D15, - GPIO1B4_I2S_MCLK_M0, - GPIO1B4_GMAC_TXEN, - - GPIO1B3_SHIFT = 6, - GPIO1B3_MASK = 3 << GPIO1B3_SHIFT, - GPIO1B3_GPIO = 0, - GPIO1B3_LCDC_D16, - GPIO1B3_I2S_SCLK_M0, - GPIO1B3_GMAC_TXD1, - - GPIO1B2_SHIFT = 4, - GPIO1B2_MASK = 3 << GPIO1B2_SHIFT, - GPIO1B2_GPIO = 0, - GPIO1B2_LCDC_D17, - GPIO1B2_I2S_SDIO_M0, - GPIO1B2_GMAC_TXD0, - - GPIO1B1_SHIFT = 2, - GPIO1B1_MASK = 3 << GPIO1B1_SHIFT, - GPIO1B1_GPIO = 0, - GPIO1B1_LCDC_D9, - GPIO1B1_PWM7, - - GPIO1B0_SHIFT = 0, - GPIO1B0_MASK = 3, - GPIO1B0_GPIO = 0, - GPIO1B0_LCDC_D8, - GPIO1B0_PWM6, -}; - -/* GRF_GPIO1C_IOMUX */ -enum { - GPIO1C7_SHIFT = 14, - GPIO1C7_MASK = 3 << GPIO1C7_SHIFT, - GPIO1C7_GPIO = 0, - GPIO1C7_CIF_D5, - GPIO1C7_I2S_SDIO2_M1, - - GPIO1C6_SHIFT = 12, - GPIO1C6_MASK = 3 << GPIO1C6_SHIFT, - GPIO1C6_GPIO = 0, - GPIO1C6_CIF_D4, - GPIO1C6_I2S_LRCLKTX_M1, - - GPIO1C5_SHIFT = 10, - GPIO1C5_MASK = 3 << GPIO1C5_SHIFT, - GPIO1C5_GPIO = 0, - GPIO1C5_LCDC_CLK, - GPIO1C5_GMAC_CLK, - - GPIO1C4_SHIFT = 8, - GPIO1C4_MASK = 3 << GPIO1C4_SHIFT, - GPIO1C4_GPIO = 0, - GPIO1C4_LCDC_HSYNC, - GPIO1C4_GMAC_MDC, - - GPIO1C3_SHIFT = 6, - GPIO1C3_MASK = 3 << GPIO1C3_SHIFT, - GPIO1C3_GPIO = 0, - GPIO1C3_LCDC_VSYNC, - GPIO1C3_GMAC_MDIO, - - GPIO1C2_SHIFT = 4, - GPIO1C2_MASK = 3 << GPIO1C2_SHIFT, - GPIO1C2_GPIO = 0, - GPIO1C2_LCDC_EN, - GPIO1C2_I2S_SDIO3_M0, - GPIO1C2_GMAC_RXER, - - GPIO1C1_SHIFT = 2, - GPIO1C1_MASK = 3 << GPIO1C1_SHIFT, - GPIO1C1_GPIO = 0, - GPIO1C1_LCDC_D10, - GPIO1C1_I2S_SDI_M0, - GPIO1C1_PWM4, - - GPIO1C0_SHIFT = 0, - GPIO1C0_MASK = 3, - GPIO1C0_GPIO = 0, - GPIO1C0_LCDC_D11, - GPIO1C0_I2S_LRCLKRX_M0, -}; - -/* GRF_GPIO1D_OIMUX */ -enum { - GPIO1D7_SHIFT = 14, - GPIO1D7_MASK = 3 << GPIO1D7_SHIFT, - GPIO1D7_GPIO = 0, - GPIO1D7_HDMI_CEC, - GPIO1D7_DSP_RTCK, - - GPIO1D6_SHIFT = 12, - GPIO1D6_MASK = 1 << GPIO1D6_SHIFT, - GPIO1D6_GPIO = 0, - GPIO1D6_HDMI_HPD_M0, - - GPIO1D5_SHIFT = 10, - GPIO1D5_MASK = 3 << GPIO1D5_SHIFT, - GPIO1D5_GPIO = 0, - GPIO1D5_UART2_RTSN, - GPIO1D5_HDMI_SDA_M0, - - GPIO1D4_SHIFT = 8, - GPIO1D4_MASK = 3 << GPIO1D4_SHIFT, - GPIO1D4_GPIO = 0, - GPIO1D4_UART2_CTSN, - GPIO1D4_HDMI_SCL_M0, - - GPIO1D3_SHIFT = 6, - GPIO1D3_MASK = 3 << GPIO1D3_SHIFT, - GPIO1D3_GPIO = 0, - GPIO1D3_UART0_SOUT, - GPIO1D3_SPI_TXD_M0, - - GPIO1D2_SHIFT = 4, - GPIO1D2_MASK = 3 << GPIO1D2_SHIFT, - GPIO1D2_GPIO = 0, - GPIO1D2_UART0_SIN, - GPIO1D2_SPI_RXD_M0, - GPIO1D2_DSP_TDI, - - GPIO1D1_SHIFT = 2, - GPIO1D1_MASK = 3 << GPIO1D1_SHIFT, - GPIO1D1_GPIO = 0, - GPIO1D1_UART0_RTSN, - GPIO1D1_SPI_CSN0_M0, - GPIO1D1_DSP_TMS, - - GPIO1D0_SHIFT = 0, - GPIO1D0_MASK = 3, - GPIO1D0_GPIO = 0, - GPIO1D0_UART0_CTSN, - GPIO1D0_SPI_CLK_M0, - GPIO1D0_DSP_TCK, -}; - -/* GRF_GPIO2A_IOMUX */ -enum { - GPIO2A7_SHIFT = 14, - GPIO2A7_MASK = 3 << GPIO2A7_SHIFT, - GPIO2A7_GPIO = 0, - GPIO2A7_FLASH_D7, - GPIO2A7_EMMC_D7, - - GPIO2A6_SHIFT = 12, - GPIO2A6_MASK = 3 << GPIO2A6_SHIFT, - GPIO2A6_GPIO = 0, - GPIO2A6_FLASH_D6, - GPIO2A6_EMMC_D6, - - GPIO2A5_SHIFT = 10, - GPIO2A5_MASK = 3 << GPIO2A5_SHIFT, - GPIO2A5_GPIO = 0, - GPIO2A5_FLASH_D5, - GPIO2A5_EMMC_D5, - - GPIO2A4_SHIFT = 8, - GPIO2A4_MASK = 3 << GPIO2A4_SHIFT, - GPIO2A4_GPIO = 0, - GPIO2A4_FLASH_D4, - GPIO2A4_EMMC_D4, - - GPIO2A3_SHIFT = 6, - GPIO2A3_MASK = 3 << GPIO2A3_SHIFT, - GPIO2A3_GPIO = 0, - GPIO2A3_FLASH_D3, - GPIO2A3_EMMC_D3, - GPIO2A3_SFC_HOLD_IO3, - - GPIO2A2_SHIFT = 4, - GPIO2A2_MASK = 3 << GPIO2A2_SHIFT, - GPIO2A2_GPIO = 0, - GPIO2A2_FLASH_D2, - GPIO2A2_EMMC_D2, - GPIO2A2_SFC_WP_IO2, - - GPIO2A1_SHIFT = 2, - GPIO2A1_MASK = 3 << GPIO2A1_SHIFT, - GPIO2A1_GPIO = 0, - GPIO2A1_FLASH_D1, - GPIO2A1_EMMC_D1, - GPIO2A1_SFC_SO_IO1, - - GPIO2A0_SHIFT = 0, - GPIO2A0_MASK = 3 << GPIO2A0_SHIFT, - GPIO2A0_GPIO = 0, - GPIO2A0_FLASH_D0, - GPIO2A0_EMMC_D0, - GPIO2A0_SFC_SI_IO0, -}; - -/* GRF_GPIO2D_IOMUX */ -enum { - GPIO2B7_SHIFT = 14, - GPIO2B7_MASK = 3 << GPIO2B7_SHIFT, - GPIO2B7_GPIO = 0, - GPIO2B7_FLASH_CS1, - GPIO2B7_SFC_CLK, - - GPIO2B6_SHIFT = 12, - GPIO2B6_MASK = 1 << GPIO2B6_SHIFT, - GPIO2B6_GPIO = 0, - GPIO2B6_EMMC_CLKO, - - GPIO2B5_SHIFT = 10, - GPIO2B5_MASK = 1 << GPIO2B5_SHIFT, - GPIO2B5_GPIO = 0, - GPIO2B5_FLASH_CS0, - - GPIO2B4_SHIFT = 8, - GPIO2B4_MASK = 3 << GPIO2B4_SHIFT, - GPIO2B4_GPIO = 0, - GPIO2B4_FLASH_RDY, - GPIO2B4_EMMC_CMD, - GPIO2B4_SFC_CSN0, - - GPIO2B3_SHIFT = 6, - GPIO2B3_MASK = 1 << GPIO2B3_SHIFT, - GPIO2B3_GPIO = 0, - GPIO2B3_FLASH_RDN, - - GPIO2B2_SHIFT = 4, - GPIO2B2_MASK = 1 << GPIO2B2_SHIFT, - GPIO2B2_GPIO = 0, - GPIO2B2_FLASH_WRN, - - GPIO2B1_SHIFT = 2, - GPIO2B1_MASK = 1 << GPIO2B1_SHIFT, - GPIO2B1_GPIO = 0, - GPIO2B1_FLASH_CLE, - - GPIO2B0_SHIFT = 0, - GPIO2B0_MASK = 1 << GPIO2B0_SHIFT, - GPIO2B0_GPIO = 0, - GPIO2B0_FLASH_ALE, -}; - -/* GRF_GPIO2D_IOMUX */ -enum { - GPIO2D7_SHIFT = 14, - GPIO2D7_MASK = 1 << GPIO2D7_SHIFT, - GPIO2D7_GPIO = 0, - GPIO2D7_SDIO_D0, - - GPIO2D6_SHIFT = 12, - GPIO2D6_MASK = 1 << GPIO2D6_SHIFT, - GPIO2D6_GPIO = 0, - GPIO2D6_SDIO_CMD, - - GPIO2D5_SHIFT = 10, - GPIO2D5_MASK = 1 << GPIO2D5_SHIFT, - GPIO2D5_GPIO = 0, - GPIO2D5_SDIO_CLKO, - - GPIO2D4_SHIFT = 8, - GPIO2D4_MASK = 1 << GPIO2D4_SHIFT, - GPIO2D4_GPIO = 0, - GPIO2D4_I2C1_SCL, - - GPIO2D3_SHIFT = 6, - GPIO2D3_MASK = 1 << GPIO2D3_SHIFT, - GPIO2D3_GPIO = 0, - GPIO2D3_I2C1_SDA, - - GPIO2D2_SHIFT = 4, - GPIO2D2_MASK = 3 << GPIO2D2_SHIFT, - GPIO2D2_GPIO = 0, - GPIO2D2_UART2_SOUT_M0, - GPIO2D2_JTAG_TCK, - - GPIO2D1_SHIFT = 2, - GPIO2D1_MASK = 3 << GPIO2D1_SHIFT, - GPIO2D1_GPIO = 0, - GPIO2D1_UART2_SIN_M0, - GPIO2D1_JTAG_TMS, - GPIO2D1_DSP_TMS, - - GPIO2D0_SHIFT = 0, - GPIO2D0_MASK = 3, - GPIO2D0_GPIO = 0, - GPIO2D0_UART0_CTSN, - GPIO2D0_SPI_CLK_M0, - GPIO2D0_DSP_TCK, -}; - -/* GRF_GPIO3A_IOMUX */ -enum { - GPIO3A7_SHIFT = 14, - GPIO3A7_MASK = 1 << GPIO3A7_SHIFT, - GPIO3A7_GPIO = 0, - - GPIO3A6_SHIFT = 12, - GPIO3A6_MASK = 1 << GPIO3A6_SHIFT, - GPIO3A6_GPIO = 0, - GPIO3A6_UART1_SOUT, - - GPIO3A5_SHIFT = 10, - GPIO3A5_MASK = 1 << GPIO3A5_SHIFT, - GPIO3A5_GPIO = 0, - GPIO3A5_UART1_SIN, - - GPIO3A4_SHIFT = 8, - GPIO3A4_MASK = 1 << GPIO3A4_SHIFT, - GPIO3A4_GPIO = 0, - GPIO3A4_UART1_CTSN, - - GPIO3A3_SHIFT = 6, - GPIO3A3_MASK = 1 << GPIO3A3_SHIFT, - GPIO3A3_GPIO = 0, - GPIO3A3_UART1_RTSN, - - GPIO3A2_SHIFT = 4, - GPIO3A2_MASK = 1 << GPIO3A2_SHIFT, - GPIO3A2_GPIO = 0, - GPIO3A2_SDIO_D3, - - GPIO3A1_SHIFT = 2, - GPIO3A1_MASK = 1 << GPIO3A1_SHIFT, - GPIO3A1_GPIO = 0, - GPIO3A1_SDIO_D2, - - GPIO3A0_SHIFT = 0, - GPIO3A0_MASK = 1, - GPIO3A0_GPIO = 0, - GPIO3A0_SDIO_D1, -}; - -/* GRF_GPIO3C_IOMUX */ -enum { - GPIO3C7_SHIFT = 14, - GPIO3C7_MASK = 1 << GPIO3C7_SHIFT, - GPIO3C7_GPIO = 0, - GPIO3C7_CIF_CLKI, - - GPIO3C6_SHIFT = 12, - GPIO3C6_MASK = 1 << GPIO3C6_SHIFT, - GPIO3C6_GPIO = 0, - GPIO3C6_CIF_VSYNC, - - GPIO3C5_SHIFT = 10, - GPIO3C5_MASK = 1 << GPIO3C5_SHIFT, - GPIO3C5_GPIO = 0, - GPIO3C5_SDMMC_CMD, - - GPIO3C4_SHIFT = 8, - GPIO3C4_MASK = 1 << GPIO3C4_SHIFT, - GPIO3C4_GPIO = 0, - GPIO3C4_SDMMC_CLKO, - - GPIO3C3_SHIFT = 6, - GPIO3C3_MASK = 3 << GPIO3C3_SHIFT, - GPIO3C3_GPIO = 0, - GPIO3C3_SDMMC_D0, - GPIO3C3_UART2_SOUT_M1, - - GPIO3C2_SHIFT = 4, - GPIO3C2_MASK = 3 << GPIO3C2_SHIFT, - GPIO3C2_GPIO = 0, - GPIO3C2_SDMMC_D1, - GPIO3C2_UART2_SIN_M1, - - GPIOC1_SHIFT = 2, - GPIOC1_MASK = 1 << GPIOC1_SHIFT, - GPIOC1_GPIO = 0, - GPIOC1_SDMMC_D2, - - GPIOC0_SHIFT = 0, - GPIOC0_MASK = 1, - GPIO3C0_GPIO = 0, - GPIO3C0_SDMMC_D3, -}; #endif diff --git a/board/rockchip/evb_rv1108/evb_rv1108.c b/board/rockchip/evb_rv1108/evb_rv1108.c index fe37eac..fb41e8f 100644 --- a/board/rockchip/evb_rv1108/evb_rv1108.c +++ b/board/rockchip/evb_rv1108/evb_rv1108.c @@ -16,6 +16,21 @@ int mach_cpu_init(void) { int node; struct rv1108_grf *grf; + enum { + GPIO3C3_SHIFT = 6, + GPIO3C3_MASK = 3 << GPIO3C3_SHIFT, + + GPIO3C2_SHIFT = 4, + GPIO3C2_MASK = 3 << GPIO3C2_SHIFT, + + GPIO2D2_SHIFT = 4, + GPIO2D2_MASK = 3 << GPIO2D2_SHIFT, + GPIO2D2_UART2_SOUT_M0, + + GPIO2D1_SHIFT = 2, + GPIO2D1_MASK = 3 << GPIO2D1_SHIFT, + GPIO2D1_UART2_SIN_M0, + }; node = fdt_node_offset_by_compatible(gd->fdt_blob, -1, "rockchip,rv1108-grf"); grf = (struct rv1108_grf *)fdtdec_get_addr(gd->fdt_blob, node, "reg"); diff --git a/drivers/pinctrl/rockchip/pinctrl_rv1108.c b/drivers/pinctrl/rockchip/pinctrl_rv1108.c index cda94f4..035f01a 100644 --- a/drivers/pinctrl/rockchip/pinctrl_rv1108.c +++ b/drivers/pinctrl/rockchip/pinctrl_rv1108.c @@ -20,6 +20,405 @@ struct rv1108_pinctrl_priv { struct rv1108_grf *grf; }; +/* GRF_GPIO1B_IOMUX */ +enum { + GPIO1B7_SHIFT = 14, + GPIO1B7_MASK = 3 << GPIO1B7_SHIFT, + GPIO1B7_GPIO = 0, + GPIO1B7_LCDC_D12, + GPIO1B7_I2S_SDIO2_M0, + GPIO1B7_GMAC_RXDV, + + GPIO1B6_SHIFT = 12, + GPIO1B6_MASK = 3 << GPIO1B6_SHIFT, + GPIO1B6_GPIO = 0, + GPIO1B6_LCDC_D13, + GPIO1B6_I2S_LRCLKTX_M0, + GPIO1B6_GMAC_RXD1, + + GPIO1B5_SHIFT = 10, + GPIO1B5_MASK = 3 << GPIO1B5_SHIFT, + GPIO1B5_GPIO = 0, + GPIO1B5_LCDC_D14, + GPIO1B5_I2S_SDIO1_M0, + GPIO1B5_GMAC_RXD0, + + GPIO1B4_SHIFT = 8, + GPIO1B4_MASK = 3 << GPIO1B4_SHIFT, + GPIO1B4_GPIO = 0, + GPIO1B4_LCDC_D15, + GPIO1B4_I2S_MCLK_M0, + GPIO1B4_GMAC_TXEN, + + GPIO1B3_SHIFT = 6, + GPIO1B3_MASK = 3 << GPIO1B3_SHIFT, + GPIO1B3_GPIO = 0, + GPIO1B3_LCDC_D16, + GPIO1B3_I2S_SCLK_M0, + GPIO1B3_GMAC_TXD1, + + GPIO1B2_SHIFT = 4, + GPIO1B2_MASK = 3 << GPIO1B2_SHIFT, + GPIO1B2_GPIO = 0, + GPIO1B2_LCDC_D17, + GPIO1B2_I2S_SDIO_M0, + GPIO1B2_GMAC_TXD0, + + GPIO1B1_SHIFT = 2, + GPIO1B1_MASK = 3 << GPIO1B1_SHIFT, + GPIO1B1_GPIO = 0, + GPIO1B1_LCDC_D9, + GPIO1B1_PWM7, + + GPIO1B0_SHIFT = 0, + GPIO1B0_MASK = 3, + GPIO1B0_GPIO = 0, + GPIO1B0_LCDC_D8, + GPIO1B0_PWM6, +}; + +/* GRF_GPIO1C_IOMUX */ +enum { + GPIO1C7_SHIFT = 14, + GPIO1C7_MASK = 3 << GPIO1C7_SHIFT, + GPIO1C7_GPIO = 0, + GPIO1C7_CIF_D5, + GPIO1C7_I2S_SDIO2_M1, + + GPIO1C6_SHIFT = 12, + GPIO1C6_MASK = 3 << GPIO1C6_SHIFT, + GPIO1C6_GPIO = 0, + GPIO1C6_CIF_D4, + GPIO1C6_I2S_LRCLKTX_M1, + + GPIO1C5_SHIFT = 10, + GPIO1C5_MASK = 3 << GPIO1C5_SHIFT, + GPIO1C5_GPIO = 0, + GPIO1C5_LCDC_CLK, + GPIO1C5_GMAC_CLK, + + GPIO1C4_SHIFT = 8, + GPIO1C4_MASK = 3 << GPIO1C4_SHIFT, + GPIO1C4_GPIO = 0, + GPIO1C4_LCDC_HSYNC, + GPIO1C4_GMAC_MDC, + + GPIO1C3_SHIFT = 6, + GPIO1C3_MASK = 3 << GPIO1C3_SHIFT, + GPIO1C3_GPIO = 0, + GPIO1C3_LCDC_VSYNC, + GPIO1C3_GMAC_MDIO, + + GPIO1C2_SHIFT = 4, + GPIO1C2_MASK = 3 << GPIO1C2_SHIFT, + GPIO1C2_GPIO = 0, + GPIO1C2_LCDC_EN, + GPIO1C2_I2S_SDIO3_M0, + GPIO1C2_GMAC_RXER, + + GPIO1C1_SHIFT = 2, + GPIO1C1_MASK = 3 << GPIO1C1_SHIFT, + GPIO1C1_GPIO = 0, + GPIO1C1_LCDC_D10, + GPIO1C1_I2S_SDI_M0, + GPIO1C1_PWM4, + + GPIO1C0_SHIFT = 0, + GPIO1C0_MASK = 3, + GPIO1C0_GPIO = 0, + GPIO1C0_LCDC_D11, + GPIO1C0_I2S_LRCLKRX_M0, +}; + +/* GRF_GPIO1D_OIMUX */ +enum { + GPIO1D7_SHIFT = 14, + GPIO1D7_MASK = 3 << GPIO1D7_SHIFT, + GPIO1D7_GPIO = 0, + GPIO1D7_HDMI_CEC, + GPIO1D7_DSP_RTCK, + + GPIO1D6_SHIFT = 12, + GPIO1D6_MASK = 1 << GPIO1D6_SHIFT, + GPIO1D6_GPIO = 0, + GPIO1D6_HDMI_HPD_M0, + + GPIO1D5_SHIFT = 10, + GPIO1D5_MASK = 3 << GPIO1D5_SHIFT, + GPIO1D5_GPIO = 0, + GPIO1D5_UART2_RTSN, + GPIO1D5_HDMI_SDA_M0, + + GPIO1D4_SHIFT = 8, + GPIO1D4_MASK = 3 << GPIO1D4_SHIFT, + GPIO1D4_GPIO = 0, + GPIO1D4_UART2_CTSN, + GPIO1D4_HDMI_SCL_M0, + + GPIO1D3_SHIFT = 6, + GPIO1D3_MASK = 3 << GPIO1D3_SHIFT, + GPIO1D3_GPIO = 0, + GPIO1D3_UART0_SOUT, + GPIO1D3_SPI_TXD_M0, + + GPIO1D2_SHIFT = 4, + GPIO1D2_MASK = 3 << GPIO1D2_SHIFT, + GPIO1D2_GPIO = 0, + GPIO1D2_UART0_SIN, + GPIO1D2_SPI_RXD_M0, + GPIO1D2_DSP_TDI, + + GPIO1D1_SHIFT = 2, + GPIO1D1_MASK = 3 << GPIO1D1_SHIFT, + GPIO1D1_GPIO = 0, + GPIO1D1_UART0_RTSN, + GPIO1D1_SPI_CSN0_M0, + GPIO1D1_DSP_TMS, + + GPIO1D0_SHIFT = 0, + GPIO1D0_MASK = 3, + GPIO1D0_GPIO = 0, + GPIO1D0_UART0_CTSN, + GPIO1D0_SPI_CLK_M0, + GPIO1D0_DSP_TCK, +}; + +/* GRF_GPIO2A_IOMUX */ +enum { + GPIO2A7_SHIFT = 14, + GPIO2A7_MASK = 3 << GPIO2A7_SHIFT, + GPIO2A7_GPIO = 0, + GPIO2A7_FLASH_D7, + GPIO2A7_EMMC_D7, + + GPIO2A6_SHIFT = 12, + GPIO2A6_MASK = 3 << GPIO2A6_SHIFT, + GPIO2A6_GPIO = 0, + GPIO2A6_FLASH_D6, + GPIO2A6_EMMC_D6, + + GPIO2A5_SHIFT = 10, + GPIO2A5_MASK = 3 << GPIO2A5_SHIFT, + GPIO2A5_GPIO = 0, + GPIO2A5_FLASH_D5, + GPIO2A5_EMMC_D5, + + GPIO2A4_SHIFT = 8, + GPIO2A4_MASK = 3 << GPIO2A4_SHIFT, + GPIO2A4_GPIO = 0, + GPIO2A4_FLASH_D4, + GPIO2A4_EMMC_D4, + + GPIO2A3_SHIFT = 6, + GPIO2A3_MASK = 3 << GPIO2A3_SHIFT, + GPIO2A3_GPIO = 0, + GPIO2A3_FLASH_D3, + GPIO2A3_EMMC_D3, + GPIO2A3_SFC_HOLD_IO3, + + GPIO2A2_SHIFT = 4, + GPIO2A2_MASK = 3 << GPIO2A2_SHIFT, + GPIO2A2_GPIO = 0, + GPIO2A2_FLASH_D2, + GPIO2A2_EMMC_D2, + GPIO2A2_SFC_WP_IO2, + + GPIO2A1_SHIFT = 2, + GPIO2A1_MASK = 3 << GPIO2A1_SHIFT, + GPIO2A1_GPIO = 0, + GPIO2A1_FLASH_D1, + GPIO2A1_EMMC_D1, + GPIO2A1_SFC_SO_IO1, + + GPIO2A0_SHIFT = 0, + GPIO2A0_MASK = 3 << GPIO2A0_SHIFT, + GPIO2A0_GPIO = 0, + GPIO2A0_FLASH_D0, + GPIO2A0_EMMC_D0, + GPIO2A0_SFC_SI_IO0, +}; + +/* GRF_GPIO2D_IOMUX */ +enum { + GPIO2B7_SHIFT = 14, + GPIO2B7_MASK = 3 << GPIO2B7_SHIFT, + GPIO2B7_GPIO = 0, + GPIO2B7_FLASH_CS1, + GPIO2B7_SFC_CLK, + + GPIO2B6_SHIFT = 12, + GPIO2B6_MASK = 1 << GPIO2B6_SHIFT, + GPIO2B6_GPIO = 0, + GPIO2B6_EMMC_CLKO, + + GPIO2B5_SHIFT = 10, + GPIO2B5_MASK = 1 << GPIO2B5_SHIFT, + GPIO2B5_GPIO = 0, + GPIO2B5_FLASH_CS0, + + GPIO2B4_SHIFT = 8, + GPIO2B4_MASK = 3 << GPIO2B4_SHIFT, + GPIO2B4_GPIO = 0, + GPIO2B4_FLASH_RDY, + GPIO2B4_EMMC_CMD, + GPIO2B4_SFC_CSN0, + + GPIO2B3_SHIFT = 6, + GPIO2B3_MASK = 1 << GPIO2B3_SHIFT, + GPIO2B3_GPIO = 0, + GPIO2B3_FLASH_RDN, + + GPIO2B2_SHIFT = 4, + GPIO2B2_MASK = 1 << GPIO2B2_SHIFT, + GPIO2B2_GPIO = 0, + GPIO2B2_FLASH_WRN, + + GPIO2B1_SHIFT = 2, + GPIO2B1_MASK = 1 << GPIO2B1_SHIFT, + GPIO2B1_GPIO = 0, + GPIO2B1_FLASH_CLE, + + GPIO2B0_SHIFT = 0, + GPIO2B0_MASK = 1 << GPIO2B0_SHIFT, + GPIO2B0_GPIO = 0, + GPIO2B0_FLASH_ALE, +}; + +/* GRF_GPIO2D_IOMUX */ +enum { + GPIO2D7_SHIFT = 14, + GPIO2D7_MASK = 1 << GPIO2D7_SHIFT, + GPIO2D7_GPIO = 0, + GPIO2D7_SDIO_D0, + + GPIO2D6_SHIFT = 12, + GPIO2D6_MASK = 1 << GPIO2D6_SHIFT, + GPIO2D6_GPIO = 0, + GPIO2D6_SDIO_CMD, + + GPIO2D5_SHIFT = 10, + GPIO2D5_MASK = 1 << GPIO2D5_SHIFT, + GPIO2D5_GPIO = 0, + GPIO2D5_SDIO_CLKO, + + GPIO2D4_SHIFT = 8, + GPIO2D4_MASK = 1 << GPIO2D4_SHIFT, + GPIO2D4_GPIO = 0, + GPIO2D4_I2C1_SCL, + + GPIO2D3_SHIFT = 6, + GPIO2D3_MASK = 1 << GPIO2D3_SHIFT, + GPIO2D3_GPIO = 0, + GPIO2D3_I2C1_SDA, + + GPIO2D2_SHIFT = 4, + GPIO2D2_MASK = 3 << GPIO2D2_SHIFT, + GPIO2D2_GPIO = 0, + GPIO2D2_UART2_SOUT_M0, + GPIO2D2_JTAG_TCK, + + GPIO2D1_SHIFT = 2, + GPIO2D1_MASK = 3 << GPIO2D1_SHIFT, + GPIO2D1_GPIO = 0, + GPIO2D1_UART2_SIN_M0, + GPIO2D1_JTAG_TMS, + GPIO2D1_DSP_TMS, + + GPIO2D0_SHIFT = 0, + GPIO2D0_MASK = 3, + GPIO2D0_GPIO = 0, + GPIO2D0_UART0_CTSN, + GPIO2D0_SPI_CLK_M0, + GPIO2D0_DSP_TCK, +}; + +/* GRF_GPIO3A_IOMUX */ +enum { + GPIO3A7_SHIFT = 14, + GPIO3A7_MASK = 1 << GPIO3A7_SHIFT, + GPIO3A7_GPIO = 0, + + GPIO3A6_SHIFT = 12, + GPIO3A6_MASK = 1 << GPIO3A6_SHIFT, + GPIO3A6_GPIO = 0, + GPIO3A6_UART1_SOUT, + + GPIO3A5_SHIFT = 10, + GPIO3A5_MASK = 1 << GPIO3A5_SHIFT, + GPIO3A5_GPIO = 0, + GPIO3A5_UART1_SIN, + + GPIO3A4_SHIFT = 8, + GPIO3A4_MASK = 1 << GPIO3A4_SHIFT, + GPIO3A4_GPIO = 0, + GPIO3A4_UART1_CTSN, + + GPIO3A3_SHIFT = 6, + GPIO3A3_MASK = 1 << GPIO3A3_SHIFT, + GPIO3A3_GPIO = 0, + GPIO3A3_UART1_RTSN, + + GPIO3A2_SHIFT = 4, + GPIO3A2_MASK = 1 << GPIO3A2_SHIFT, + GPIO3A2_GPIO = 0, + GPIO3A2_SDIO_D3, + + GPIO3A1_SHIFT = 2, + GPIO3A1_MASK = 1 << GPIO3A1_SHIFT, + GPIO3A1_GPIO = 0, + GPIO3A1_SDIO_D2, + + GPIO3A0_SHIFT = 0, + GPIO3A0_MASK = 1, + GPIO3A0_GPIO = 0, + GPIO3A0_SDIO_D1, +}; + +/* GRF_GPIO3C_IOMUX */ +enum { + GPIO3C7_SHIFT = 14, + GPIO3C7_MASK = 1 << GPIO3C7_SHIFT, + GPIO3C7_GPIO = 0, + GPIO3C7_CIF_CLKI, + + GPIO3C6_SHIFT = 12, + GPIO3C6_MASK = 1 << GPIO3C6_SHIFT, + GPIO3C6_GPIO = 0, + GPIO3C6_CIF_VSYNC, + + GPIO3C5_SHIFT = 10, + GPIO3C5_MASK = 1 << GPIO3C5_SHIFT, + GPIO3C5_GPIO = 0, + GPIO3C5_SDMMC_CMD, + + GPIO3C4_SHIFT = 8, + GPIO3C4_MASK = 1 << GPIO3C4_SHIFT, + GPIO3C4_GPIO = 0, + GPIO3C4_SDMMC_CLKO, + + GPIO3C3_SHIFT = 6, + GPIO3C3_MASK = 3 << GPIO3C3_SHIFT, + GPIO3C3_GPIO = 0, + GPIO3C3_SDMMC_D0, + GPIO3C3_UART2_SOUT_M1, + + GPIO3C2_SHIFT = 4, + GPIO3C2_MASK = 3 << GPIO3C2_SHIFT, + GPIO3C2_GPIO = 0, + GPIO3C2_SDMMC_D1, + GPIO3C2_UART2_SIN_M1, + + GPIOC1_SHIFT = 2, + GPIOC1_MASK = 1 << GPIOC1_SHIFT, + GPIOC1_GPIO = 0, + GPIOC1_SDMMC_D2, + + GPIOC0_SHIFT = 0, + GPIOC0_MASK = 1, + GPIO3C0_GPIO = 0, + GPIO3C0_SDMMC_D3, +}; + static void pinctrl_rv1108_uart_config(struct rv1108_grf *grf, int uart_id) { switch (uart_id) { From patchwork Thu Nov 9 09:02:29 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Wu X-Patchwork-Id: 836232 X-Patchwork-Delegate: philipp.tomsich@theobroma-systems.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3yXcfK5kqdz9t5Q for ; Thu, 9 Nov 2017 20:03:53 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 31E95C21FCD; Thu, 9 Nov 2017 09:03:24 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: ** X-Spam-Status: No, score=3.0 required=5.0 tests=RCVD_IN_MSPIKE_BL, RCVD_IN_MSPIKE_L5,RCVD_IN_SORBS_WEB autolearn=no autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 6DADFC21F5F; Thu, 9 Nov 2017 09:03:21 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id EFB7FC21F5D; Thu, 9 Nov 2017 09:03:18 +0000 (UTC) Received: from lucky1.263xmail.com (lucky1.263xmail.com [211.157.147.131]) by lists.denx.de (Postfix) with ESMTPS id 57DEBC21F5F for ; Thu, 9 Nov 2017 09:03:18 +0000 (UTC) Received: from david.wu?rock-chips.com (unknown [192.168.167.234]) by lucky1.263xmail.com (Postfix) with ESMTP id 7ABC396F16; Thu, 9 Nov 2017 17:03:14 +0800 (CST) X-263anti-spam: KSV:0; X-MAIL-GRAY: 1 X-MAIL-DELIVERY: 0 X-KSVirus-check: 0 X-ABS-CHECKED: 4 Received: from localhost.localdomain (localhost [127.0.0.1]) by smtp.263.net (Postfix) with ESMTPA id A01643C6; Thu, 9 Nov 2017 17:03:12 +0800 (CST) X-RL-SENDER: david.wu@rock-chips.com X-FST-TO: philipp.tomsich@theobroma-systems.com X-SENDER-IP: 58.22.7.114 X-LOGIN-NAME: david.wu@rock-chips.com X-UNIQUE-TAG: X-ATTACHMENT-NUM: 0 X-SENDER: wdc@rock-chips.com X-DNS-TYPE: 0 Received: from localhost.localdomain (unknown [58.22.7.114]) by smtp.263.net (Postfix) whith ESMTP id 16622ODYWXD; Thu, 09 Nov 2017 17:03:14 +0800 (CST) From: David Wu To: philipp.tomsich@theobroma-systems.com, sjg@chromium.org Date: Thu, 9 Nov 2017 17:02:29 +0800 Message-Id: <1510218149-78706-1-git-send-email-david.wu@rock-chips.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1510217699-78401-1-git-send-email-david.wu@rock-chips.com> References: <1510217699-78401-1-git-send-email-david.wu@rock-chips.com> Cc: huangtao@rock-chips.com, joe.hershberger@ni.com, u-boot@lists.denx.de, David Wu , andy.yan@rock-chips.com Subject: [U-Boot] [PATCH v2 06/18] net: gmac_rockchip: Add support for the RV1108 GMAC X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The rv1108 GMAC only support rmii interface, so need to add the set_rmii() ops. Use the phy current interface to set rmii or rgmii ops. At the same time, need to set the mac clock rate of rmii with 50M, the clock rate of rgmii with 125M. Signed-off-by: David Wu Acked-by: Philipp Tomsich Reviewed-by: Philipp Tomsich --- Changes in v2: - Add check whether the set rgmii/rmii function is a valid function pointer - Use current phy interface to set mac clock rate - Clean the grf offset at gmac_rockchip.c drivers/net/gmac_rockchip.c | 89 +++++++++++++++++++++++++++++++++++++++++---- 1 file changed, 82 insertions(+), 7 deletions(-) diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c index 586ccbf..22e3941 100644 --- a/drivers/net/gmac_rockchip.c +++ b/drivers/net/gmac_rockchip.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include "designware.h" @@ -37,6 +38,7 @@ struct gmac_rockchip_platdata { struct rk_gmac_ops { int (*fix_mac_speed)(struct dw_eth_dev *priv); + void (*set_to_rmii)(struct gmac_rockchip_platdata *pdata); void (*set_to_rgmii)(struct gmac_rockchip_platdata *pdata); }; @@ -142,6 +144,41 @@ static int rk3399_gmac_fix_mac_speed(struct dw_eth_dev *priv) return 0; } +static int rv1108_set_rmii_speed(struct dw_eth_dev *priv) +{ + struct rv1108_grf *grf; + int clk, speed; + enum { + RV1108_GMAC_SPEED_MASK = BIT(2), + RV1108_GMAC_SPEED_10M = 0 << 2, + RV1108_GMAC_SPEED_100M = 1 << 2, + RV1108_GMAC_CLK_SEL_MASK = BIT(7), + RV1108_GMAC_CLK_SEL_2_5M = 0 << 7, + RV1108_GMAC_CLK_SEL_25M = 1 << 7, + }; + + switch (priv->phydev->speed) { + case 10: + clk = RV1108_GMAC_CLK_SEL_2_5M; + speed = RV1108_GMAC_SPEED_10M; + break; + case 100: + clk = RV1108_GMAC_CLK_SEL_25M; + speed = RV1108_GMAC_SPEED_100M; + break; + default: + debug("Unknown phy speed: %d\n", priv->phydev->speed); + return -EINVAL; + } + + grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + rk_clrsetreg(&grf->gmac_con0, + RV1108_GMAC_CLK_SEL_MASK | RV1108_GMAC_SPEED_MASK, + clk | speed); + + return 0; +} + static void rk3288_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) { struct rk3288_grf *grf; @@ -221,11 +258,28 @@ static void rk3399_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata) pdata->tx_delay << RK3399_CLK_TX_DL_CFG_GMAC_SHIFT); } +static void rv1108_gmac_set_to_rmii(struct gmac_rockchip_platdata *pdata) +{ + struct rv1108_grf *grf; + + enum { + RV1108_GMAC_PHY_INTF_SEL_MASK = GENMASK(6, 4), + RV1108_GMAC_PHY_INTF_SEL_RMII = 4 << 4, + }; + + grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + rk_clrsetreg(&grf->gmac_con0, + RV1108_GMAC_PHY_INTF_SEL_MASK, + RV1108_GMAC_PHY_INTF_SEL_RMII); +} + static int gmac_rockchip_probe(struct udevice *dev) { struct gmac_rockchip_platdata *pdata = dev_get_platdata(dev); struct rk_gmac_ops *ops = (struct rk_gmac_ops *)dev_get_driver_data(dev); + struct dw_eth_pdata *dw_pdata = dev_get_platdata(dev); + struct eth_pdata *eth_pdata = &dw_pdata->eth_pdata; struct clk clk; int ret; @@ -233,13 +287,27 @@ static int gmac_rockchip_probe(struct udevice *dev) if (ret) return ret; - /* Since mac_clk is fed by an external clock we can use 0 here */ - ret = clk_set_rate(&clk, 0); - if (ret) - return ret; - - /* Set to RGMII mode */ - ops->set_to_rgmii(pdata); + switch (eth_pdata->phy_interface) { + case PHY_INTERFACE_MODE_RGMII: + ret = clk_set_rate(&clk, 125000000); + if (IS_ERR_VALUE(ret)) + return ret; + /* Set to RGMII mode */ + if (ops->set_to_rgmii) + ops->set_to_rgmii(pdata); + break; + case PHY_INTERFACE_MODE_RMII: + ret = clk_set_rate(&clk, 50000000); + if (IS_ERR_VALUE(ret)) + return ret; + /* Set to RMII mode */ + if (ops->set_to_rmii) + ops->set_to_rmii(pdata); + break; + default: + debug("NO interface defined!\n"); + return -ENXIO; + } return designware_eth_probe(dev); } @@ -289,6 +357,11 @@ const struct rk_gmac_ops rk3399_gmac_ops = { .set_to_rgmii = rk3399_gmac_set_to_rgmii, }; +const struct rk_gmac_ops rv1108_gmac_ops = { + .fix_mac_speed = rv1108_set_rmii_speed, + .set_to_rmii = rv1108_gmac_set_to_rmii, +}; + static const struct udevice_id rockchip_gmac_ids[] = { { .compatible = "rockchip,rk3288-gmac", .data = (ulong)&rk3288_gmac_ops }, @@ -296,6 +369,8 @@ static const struct udevice_id rockchip_gmac_ids[] = { .data = (ulong)&rk3368_gmac_ops }, { .compatible = "rockchip,rk3399-gmac", .data = (ulong)&rk3399_gmac_ops }, + { .compatible = "rockchip,rv1108-gmac", + .data = (ulong)&rv1108_gmac_ops }, { } }; From patchwork Thu Nov 9 09:03:40 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Wu X-Patchwork-Id: 836233 X-Patchwork-Delegate: philipp.tomsich@theobroma-systems.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3yXcgN0J6Vz9s71 for ; Thu, 9 Nov 2017 20:04:47 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 8075CC21F5F; Thu, 9 Nov 2017 09:04:35 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=-0.2 required=5.0 tests=ALL_TRUSTED, UPPERCASE_50_75 autolearn=no autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 47FFAC21F43; Thu, 9 Nov 2017 09:04:31 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 9E063C21F73; Thu, 9 Nov 2017 09:04:29 +0000 (UTC) Received: from localhost by lists.denx.de with SpamAssassin (version 3.4.0); Thu, 09 Nov 2017 09:04:29 +0000 From: David Wu To: philipp.tomsich@theobroma-systems.com, sjg@chromium.org Date: Thu, 9 Nov 2017 17:03:40 +0800 Message-Id: <1510218220-78779-1-git-send-email-david.wu@rock-chips.com> MIME-Version: 1.0 Cc: huangtao@rock-chips.com, joe.hershberger@ni.com, u-boot@lists.denx.de, David Wu , andy.yan@rock-chips.com Subject: [U-Boot] [PATCH v2 07/18] rockchip: pinctrl: rk3328: Move the iomux definitions into pinctrl-driver X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Spam detection software, running on the system "lists.denx.de", has identified this incoming email as possible spam. The original message has been attached to this so you can view it or label similar future email. If you have any questions, see @@CONTACT_ADDRESS@@ for details. Content preview: Clean the iomux definitions at grf_rk3328.h, and move them into pinctrl-driver for resolving the compiling error of redefinition. Signed-off-by: David Wu --- Changes in v2: - New patch [...] Content analysis details: (6.5 points, 5.0 required) pts rule name description ---- ---------------------- -------------------------------------------------- 0.6 RCVD_IN_SORBS_WEB RBL: SORBS: sender is an abusable web server [58.22.7.114 listed in dnsbl.sorbs.net] 2.7 RCVD_IN_PSBL RBL: Received via a relay in PSBL [211.157.147.134 listed in psbl.surriel.com] 2.4 RCVD_IN_MSPIKE_L5 RBL: Very bad reputation (-5) [211.157.147.134 listed in bl.mailspike.net] 0.8 UPPERCASE_50_75 message body is 50-75% uppercase 0.0 RCVD_IN_MSPIKE_BL Mailspike blacklisted Clean the iomux definitions at grf_rk3328.h, and move them into pinctrl-driver for resolving the compiling error of redefinition. Signed-off-by: David Wu Acked-by: Philipp Tomsich Reviewed-by: Philipp Tomsich --- Changes in v2: - New patch arch/arm/include/asm/arch-rockchip/grf_rk3328.h | 113 ------------------- drivers/pinctrl/rockchip/pinctrl_rk3328.c | 144 ++++++++++++++++++++++++ 2 files changed, 144 insertions(+), 113 deletions(-) diff --git a/arch/arm/include/asm/arch-rockchip/grf_rk3328.h b/arch/arm/include/asm/arch-rockchip/grf_rk3328.h index f0a0781..0c37f2a 100644 --- a/arch/arm/include/asm/arch-rockchip/grf_rk3328.h +++ b/arch/arm/include/asm/arch-rockchip/grf_rk3328.h @@ -131,118 +131,5 @@ struct rk3328_sgrf_regs { }; check_member(rk3328_sgrf_regs, hdcp_key_access_mask, 0x2a0); -enum { - /* GPIO0A_IOMUX */ - GPIO0A5_SEL_SHIFT = 10, - GPIO0A5_SEL_MASK = 3 << GPIO0A5_SEL_SHIFT, - GPIO0A5_I2C3_SCL = 2, - - GPIO0A6_SEL_SHIFT = 12, - GPIO0A6_SEL_MASK = 3 << GPIO0A6_SEL_SHIFT, - GPIO0A6_I2C3_SDA = 2, - - GPIO0A7_SEL_SHIFT = 14, - GPIO0A7_SEL_MASK = 3 << GPIO0A7_SEL_SHIFT, - GPIO0A7_EMMC_DATA0 = 2, - - /* GPIO0D_IOMUX*/ - GPIO0D6_SEL_SHIFT = 12, - GPIO0D6_SEL_MASK = 3 << GPIO0D6_SEL_SHIFT, - GPIO0D6_GPIO = 0, - GPIO0D6_SDMMC0_PWRENM1 = 3, - - /* GPIO1A_IOMUX */ - GPIO1A0_SEL_SHIFT = 0, - GPIO1A0_SEL_MASK = 0x3fff << GPIO1A0_SEL_SHIFT, - GPIO1A0_CARD_DATA_CLK_CMD_DETN = 0x1555, - - /* GPIO2A_IOMUX */ - GPIO2A0_SEL_SHIFT = 0, - GPIO2A0_SEL_MASK = 3 << GPIO2A0_SEL_SHIFT, - GPIO2A0_UART2_TX_M1 = 1, - - GPIO2A1_SEL_SHIFT = 2, - GPIO2A1_SEL_MASK = 3 << GPIO2A1_SEL_SHIFT, - GPIO2A1_UART2_RX_M1 = 1, - - GPIO2A2_SEL_SHIFT = 4, - GPIO2A2_SEL_MASK = 3 << GPIO2A2_SEL_SHIFT, - GPIO2A2_PWM_IR = 1, - - GPIO2A4_SEL_SHIFT = 8, - GPIO2A4_SEL_MASK = 3 << GPIO2A4_SEL_SHIFT, - GPIO2A4_PWM_0 = 1, - GPIO2A4_I2C1_SDA, - - GPIO2A5_SEL_SHIFT = 10, - GPIO2A5_SEL_MASK = 3 << GPIO2A5_SEL_SHIFT, - GPIO2A5_PWM_1 = 1, - GPIO2A5_I2C1_SCL, - - GPIO2A6_SEL_SHIFT = 12, - GPIO2A6_SEL_MASK = 3 << GPIO2A6_SEL_SHIFT, - GPIO2A6_PWM_2 = 1, - - GPIO2A7_SEL_SHIFT = 14, - GPIO2A7_SEL_MASK = 3 << GPIO2A7_SEL_SHIFT, - GPIO2A7_GPIO = 0, - GPIO2A7_SDMMC0_PWRENM0, - - /* GPIO2BL_IOMUX */ - GPIO2BL0_SEL_SHIFT = 0, - GPIO2BL0_SEL_MASK = 0x3f << GPIO2BL0_SEL_SHIFT, - GPIO2BL0_SPI_CLK_TX_RX_M0 = 0x15, - - GPIO2BL3_SEL_SHIFT = 6, - GPIO2BL3_SEL_MASK = 3 << GPIO2BL3_SEL_SHIFT, - GPIO2BL3_SPI_CSN0_M0 = 1, - - GPIO2BL4_SEL_SHIFT = 8, - GPIO2BL4_SEL_MASK = 3 << GPIO2BL4_SEL_SHIFT, - GPIO2BL4_SPI_CSN1_M0 = 1, - - GPIO2BL5_SEL_SHIFT = 10, - GPIO2BL5_SEL_MASK = 3 << GPIO2BL5_SEL_SHIFT, - GPIO2BL5_I2C2_SDA = 1, - - GPIO2BL6_SEL_SHIFT = 12, - GPIO2BL6_SEL_MASK = 3 << GPIO2BL6_SEL_SHIFT, - GPIO2BL6_I2C2_SCL = 1, - - /* GPIO2D_IOMUX */ - GPIO2D0_SEL_SHIFT = 0, - GPIO2D0_SEL_MASK = 3 << GPIO2D0_SEL_SHIFT, - GPIO2D0_I2C0_SCL = 1, - - GPIO2D1_SEL_SHIFT = 2, - GPIO2D1_SEL_MASK = 3 << GPIO2D1_SEL_SHIFT, - GPIO2D1_I2C0_SDA = 1, - - GPIO2D4_SEL_SHIFT = 8, - GPIO2D4_SEL_MASK = 0xff << GPIO2D4_SEL_SHIFT, - GPIO2D4_EMMC_DATA1234 = 0xaa, - - /* GPIO3C_IOMUX */ - GPIO3C0_SEL_SHIFT = 0, - GPIO3C0_SEL_MASK = 0x3fff << GPIO3C0_SEL_SHIFT, - GPIO3C0_EMMC_DATA567_PWR_CLK_RSTN_CMD = 0x2aaa, - - /* COM_IOMUX */ - IOMUX_SEL_UART2_SHIFT = 0, - IOMUX_SEL_UART2_MASK = 3 << IOMUX_SEL_UART2_SHIFT, - IOMUX_SEL_UART2_M0 = 0, - IOMUX_SEL_UART2_M1, - - IOMUX_SEL_SPI_SHIFT = 4, - IOMUX_SEL_SPI_MASK = 3 << IOMUX_SEL_SPI_SHIFT, - IOMUX_SEL_SPI_M0 = 0, - IOMUX_SEL_SPI_M1, - IOMUX_SEL_SPI_M2, - - IOMUX_SEL_SDMMC_SHIFT = 7, - IOMUX_SEL_SDMMC_MASK = 1 << IOMUX_SEL_SDMMC_SHIFT, - IOMUX_SEL_SDMMC_M0 = 0, - IOMUX_SEL_SDMMC_M1, -}; #endif /* __SOC_ROCKCHIP_RK3328_GRF_H__ */ diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3328.c b/drivers/pinctrl/rockchip/pinctrl_rk3328.c index c74163e..0042025 100644 --- a/drivers/pinctrl/rockchip/pinctrl_rk3328.c +++ b/drivers/pinctrl/rockchip/pinctrl_rk3328.c @@ -17,6 +17,150 @@ DECLARE_GLOBAL_DATA_PTR; +enum { + /* GPIO0A_IOMUX */ + GPIO0A5_SEL_SHIFT = 10, + GPIO0A5_SEL_MASK = 3 << GPIO0A5_SEL_SHIFT, + GPIO0A5_I2C3_SCL = 2, + + GPIO0A6_SEL_SHIFT = 12, + GPIO0A6_SEL_MASK = 3 << GPIO0A6_SEL_SHIFT, + GPIO0A6_I2C3_SDA = 2, + + GPIO0A7_SEL_SHIFT = 14, + GPIO0A7_SEL_MASK = 3 << GPIO0A7_SEL_SHIFT, + GPIO0A7_EMMC_DATA0 = 2, + + /* GPIO0B_IOMUX*/ + GPIO0B0_SEL_SHIFT = 0, + GPIO0B0_SEL_MASK = GENMASK(1, 0), + GPIO0B0_GAMC_CLKTXM0 = 1, + + GPIO0B4_SEL_SHIFT = 8, + GPIO0B4_SEL_MASK = GENMASK(9, 8), + GPIO0B4_GAMC_TXENM0 = 1, + + /* GPIO0C_IOMUX*/ + GPIO0C0_SEL_SHIFT = 0, + GPIO0C0_SEL_MASK = GENMASK(1, 0), + GPIO0C0_GAMC_TXD1M0 = 1, + + GPIO0C1_SEL_SHIFT = 2, + GPIO0C1_SEL_MASK = GENMASK(3, 2), + GPIO0C1_GAMC_TXD0M0 = 1, + + GPIO0C6_SEL_SHIFT = 12, + GPIO0C6_SEL_MASK = GENMASK(13, 12), + GPIO0C6_GAMC_TXD2M0 = 1, + + GPIO0C7_SEL_SHIFT = 14, + GPIO0C7_SEL_MASK = GENMASK(15, 14), + GPIO0C7_GAMC_TXD3M0 = 1, + + /* GPIO0D_IOMUX*/ + GPIO0D0_SEL_SHIFT = 0, + GPIO0D0_SEL_MASK = GENMASK(1, 0), + GPIO0D0_GMAC_CLKM0 = 1, + + GPIO0D6_SEL_SHIFT = 12, + GPIO0D6_SEL_MASK = 3 << GPIO0D6_SEL_SHIFT, + GPIO0D6_GPIO = 0, + GPIO0D6_SDMMC0_PWRENM1 = 3, + + /* GPIO1A_IOMUX */ + GPIO1A0_SEL_SHIFT = 0, + GPIO1A0_SEL_MASK = 0x3fff << GPIO1A0_SEL_SHIFT, + GPIO1A0_CARD_DATA_CLK_CMD_DETN = 0x1555, + + /* GPIO2A_IOMUX */ + GPIO2A0_SEL_SHIFT = 0, + GPIO2A0_SEL_MASK = 3 << GPIO2A0_SEL_SHIFT, + GPIO2A0_UART2_TX_M1 = 1, + + GPIO2A1_SEL_SHIFT = 2, + GPIO2A1_SEL_MASK = 3 << GPIO2A1_SEL_SHIFT, + GPIO2A1_UART2_RX_M1 = 1, + + GPIO2A2_SEL_SHIFT = 4, + GPIO2A2_SEL_MASK = 3 << GPIO2A2_SEL_SHIFT, + GPIO2A2_PWM_IR = 1, + + GPIO2A4_SEL_SHIFT = 8, + GPIO2A4_SEL_MASK = 3 << GPIO2A4_SEL_SHIFT, + GPIO2A4_PWM_0 = 1, + GPIO2A4_I2C1_SDA, + + GPIO2A5_SEL_SHIFT = 10, + GPIO2A5_SEL_MASK = 3 << GPIO2A5_SEL_SHIFT, + GPIO2A5_PWM_1 = 1, + GPIO2A5_I2C1_SCL, + + GPIO2A6_SEL_SHIFT = 12, + GPIO2A6_SEL_MASK = 3 << GPIO2A6_SEL_SHIFT, + GPIO2A6_PWM_2 = 1, + + GPIO2A7_SEL_SHIFT = 14, + GPIO2A7_SEL_MASK = 3 << GPIO2A7_SEL_SHIFT, + GPIO2A7_GPIO = 0, + GPIO2A7_SDMMC0_PWRENM0, + + /* GPIO2BL_IOMUX */ + GPIO2BL0_SEL_SHIFT = 0, + GPIO2BL0_SEL_MASK = 0x3f << GPIO2BL0_SEL_SHIFT, + GPIO2BL0_SPI_CLK_TX_RX_M0 = 0x15, + + GPIO2BL3_SEL_SHIFT = 6, + GPIO2BL3_SEL_MASK = 3 << GPIO2BL3_SEL_SHIFT, + GPIO2BL3_SPI_CSN0_M0 = 1, + + GPIO2BL4_SEL_SHIFT = 8, + GPIO2BL4_SEL_MASK = 3 << GPIO2BL4_SEL_SHIFT, + GPIO2BL4_SPI_CSN1_M0 = 1, + + GPIO2BL5_SEL_SHIFT = 10, + GPIO2BL5_SEL_MASK = 3 << GPIO2BL5_SEL_SHIFT, + GPIO2BL5_I2C2_SDA = 1, + + GPIO2BL6_SEL_SHIFT = 12, + GPIO2BL6_SEL_MASK = 3 << GPIO2BL6_SEL_SHIFT, + GPIO2BL6_I2C2_SCL = 1, + + /* GPIO2D_IOMUX */ + GPIO2D0_SEL_SHIFT = 0, + GPIO2D0_SEL_MASK = 3 << GPIO2D0_SEL_SHIFT, + GPIO2D0_I2C0_SCL = 1, + + GPIO2D1_SEL_SHIFT = 2, + GPIO2D1_SEL_MASK = 3 << GPIO2D1_SEL_SHIFT, + GPIO2D1_I2C0_SDA = 1, + + GPIO2D4_SEL_SHIFT = 8, + GPIO2D4_SEL_MASK = 0xff << GPIO2D4_SEL_SHIFT, + GPIO2D4_EMMC_DATA1234 = 0xaa, + + /* GPIO3C_IOMUX */ + GPIO3C0_SEL_SHIFT = 0, + GPIO3C0_SEL_MASK = 0x3fff << GPIO3C0_SEL_SHIFT, + GPIO3C0_EMMC_DATA567_PWR_CLK_RSTN_CMD = 0x2aaa, + + /* COM_IOMUX */ + IOMUX_SEL_UART2_SHIFT = 0, + IOMUX_SEL_UART2_MASK = 3 << IOMUX_SEL_UART2_SHIFT, + IOMUX_SEL_UART2_M0 = 0, + IOMUX_SEL_UART2_M1, + + IOMUX_SEL_SPI_SHIFT = 4, + IOMUX_SEL_SPI_MASK = 3 << IOMUX_SEL_SPI_SHIFT, + IOMUX_SEL_SPI_M0 = 0, + IOMUX_SEL_SPI_M1, + IOMUX_SEL_SPI_M2, + + IOMUX_SEL_SDMMC_SHIFT = 7, + IOMUX_SEL_SDMMC_MASK = 1 << IOMUX_SEL_SDMMC_SHIFT, + IOMUX_SEL_SDMMC_M0 = 0, + IOMUX_SEL_SDMMC_M1, +}; + struct rk3328_pinctrl_priv { struct rk3328_grf_regs *grf; }; From patchwork Thu Nov 9 09:04:39 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Wu X-Patchwork-Id: 836234 X-Patchwork-Delegate: philipp.tomsich@theobroma-systems.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3yXchK3W8rz9s71 for ; Thu, 9 Nov 2017 20:05:37 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 24D54C21F7C; Thu, 9 Nov 2017 09:05:26 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: *** X-Spam-Status: No, score=3.8 required=5.0 tests=RCVD_IN_MSPIKE_BL, RCVD_IN_MSPIKE_L5,RCVD_IN_SORBS_WEB,UPPERCASE_50_75 autolearn=no autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id A2206C21FC1; Thu, 9 Nov 2017 09:05:23 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 6D643C21FBA; Thu, 9 Nov 2017 09:05:22 +0000 (UTC) Received: from lucky1.263xmail.com (lucky1.263xmail.com [211.157.147.131]) by lists.denx.de (Postfix) with ESMTPS id 869F7C21FF0 for ; Thu, 9 Nov 2017 09:05:21 +0000 (UTC) Received: from david.wu?rock-chips.com (unknown [192.168.167.78]) by lucky1.263xmail.com (Postfix) with ESMTP id 9431C96FC9; Thu, 9 Nov 2017 17:05:17 +0800 (CST) X-263anti-spam: KSV:0; X-MAIL-GRAY: 1 X-MAIL-DELIVERY: 0 X-KSVirus-check: 0 X-ABS-CHECKED: 4 Received: from localhost.localdomain (localhost [127.0.0.1]) by smtp.263.net (Postfix) with ESMTPA id EAEAC3DE; Thu, 9 Nov 2017 17:05:16 +0800 (CST) X-RL-SENDER: david.wu@rock-chips.com X-FST-TO: philipp.tomsich@theobroma-systems.com X-SENDER-IP: 58.22.7.114 X-LOGIN-NAME: david.wu@rock-chips.com X-UNIQUE-TAG: X-ATTACHMENT-NUM: 0 X-SENDER: wdc@rock-chips.com X-DNS-TYPE: 0 Received: from localhost.localdomain (unknown [58.22.7.114]) by smtp.263.net (Postfix) whith ESMTP id 20407LVXGWB; Thu, 09 Nov 2017 17:05:18 +0800 (CST) From: David Wu To: philipp.tomsich@theobroma-systems.com, sjg@chromium.org Date: Thu, 9 Nov 2017 17:04:39 +0800 Message-Id: <1510218279-78848-1-git-send-email-david.wu@rock-chips.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1510217699-78401-1-git-send-email-david.wu@rock-chips.com> References: <1510217699-78401-1-git-send-email-david.wu@rock-chips.com> Cc: huangtao@rock-chips.com, joe.hershberger@ni.com, u-boot@lists.denx.de, David Wu , andy.yan@rock-chips.com Subject: [U-Boot] [PATCH v2 08/18] rockchip: pinctrl: Add rk3328 gmac pinctrl support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Need to set gmac m1 pins iomux, gmac m0 tx pins, select bit2 and bit10 at com iomux register. After that, set rgmii m1 tx pins to 12ma drive-strength, and clean others to 2ma. Signed-off-by: David Wu Acked-by: Philipp Tomsich Reviewed-by: Philipp Tomsich --- Changes in v2: - New patch drivers/pinctrl/rockchip/pinctrl_rk3328.c | 236 ++++++++++++++++++++++++++++++ 1 file changed, 236 insertions(+) diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3328.c b/drivers/pinctrl/rockchip/pinctrl_rk3328.c index 0042025..c155027 100644 --- a/drivers/pinctrl/rockchip/pinctrl_rk3328.c +++ b/drivers/pinctrl/rockchip/pinctrl_rk3328.c @@ -72,6 +72,69 @@ enum { GPIO1A0_SEL_MASK = 0x3fff << GPIO1A0_SEL_SHIFT, GPIO1A0_CARD_DATA_CLK_CMD_DETN = 0x1555, + /* GPIO1B_IOMUX */ + GPIO1B0_SEL_SHIFT = 0, + GPIO1B0_SEL_MASK = GENMASK(1, 0), + GPIO1B0_GMAC_TXD1M1 = 2, + + GPIO1B1_SEL_SHIFT = 2, + GPIO1B1_SEL_MASK = GENMASK(3, 2), + GPIO1B1_GMAC_TXD0M1 = 2, + + GPIO1B2_SEL_SHIFT = 4, + GPIO1B2_SEL_MASK = GENMASK(5, 4), + GPIO1B2_GMAC_RXD1M1 = 2, + + GPIO1B3_SEL_SHIFT = 6, + GPIO1B3_SEL_MASK = GENMASK(7, 6), + GPIO1B3_GMAC_RXD0M1 = 2, + + GPIO1B4_SEL_SHIFT = 8, + GPIO1B4_SEL_MASK = GENMASK(9, 8), + GPIO1B4_GMAC_TXCLKM1 = 2, + + GPIO1B5_SEL_SHIFT = 10, + GPIO1B5_SEL_MASK = GENMASK(11, 10), + GPIO1B5_GMAC_RXCLKM1 = 2, + + GPIO1B6_SEL_SHIFT = 12, + GPIO1B6_SEL_MASK = GENMASK(13, 12), + GPIO1B6_GMAC_RXD3M1 = 2, + + GPIO1B7_SEL_SHIFT = 14, + GPIO1B7_SEL_MASK = GENMASK(15, 14), + GPIO1B7_GMAC_RXD2M1 = 2, + + /* GPIO1C_IOMUX */ + GPIO1C0_SEL_SHIFT = 0, + GPIO1C0_SEL_MASK = GENMASK(1, 0), + GPIO1C0_GMAC_TXD3M1 = 2, + + GPIO1C1_SEL_SHIFT = 2, + GPIO1C1_SEL_MASK = GENMASK(3, 2), + GPIO1C1_GMAC_TXD2M1 = 2, + + GPIO1C3_SEL_SHIFT = 6, + GPIO1C3_SEL_MASK = GENMASK(7, 6), + GPIO1C3_GMAC_MDIOM1 = 2, + + GPIO1C5_SEL_SHIFT = 10, + GPIO1C5_SEL_MASK = GENMASK(11, 10), + GPIO1C5_GMAC_CLKM1 = 2, + + GPIO1C6_SEL_SHIFT = 12, + GPIO1C6_SEL_MASK = GENMASK(13, 12), + GPIO1C6_GMAC_RXDVM1 = 2, + + GPIO1C7_SEL_SHIFT = 14, + GPIO1C7_SEL_MASK = GENMASK(15, 14), + GPIO1C7_GMAC_MDCM1 = 2, + + /* GPIO1D_IOMUX */ + GPIO1D1_SEL_SHIFT = 2, + GPIO1D1_SEL_MASK = GENMASK(3, 2), + GPIO1D1_GMAC_TXENM1 = 2, + /* GPIO2A_IOMUX */ GPIO2A0_SEL_SHIFT = 0, GPIO2A0_SEL_MASK = 3 << GPIO2A0_SEL_SHIFT, @@ -149,6 +212,11 @@ enum { IOMUX_SEL_UART2_M0 = 0, IOMUX_SEL_UART2_M1, + IOMUX_SEL_GMAC_SHIFT = 2, + IOMUX_SEL_GMAC_MASK = BIT(2), + IOMUX_SEL_GMAC_M0 = 0, + IOMUX_SEL_GMAC_M1, + IOMUX_SEL_SPI_SHIFT = 4, IOMUX_SEL_SPI_MASK = 3 << IOMUX_SEL_SPI_SHIFT, IOMUX_SEL_SPI_M0 = 0, @@ -159,6 +227,47 @@ enum { IOMUX_SEL_SDMMC_MASK = 1 << IOMUX_SEL_SDMMC_SHIFT, IOMUX_SEL_SDMMC_M0 = 0, IOMUX_SEL_SDMMC_M1, + + IOMUX_SEL_GMACM1_OPTIMIZATION_SHIFT = 10, + IOMUX_SEL_GMACM1_OPTIMIZATION_MASK = BIT(10), + IOMUX_SEL_GMACM1_OPTIMIZATION_BEFORE = 0, + IOMUX_SEL_GMACM1_OPTIMIZATION_AFTER, + + /* GRF_GPIO1B_E */ + GRF_GPIO1B0_E_SHIFT = 0, + GRF_GPIO1B0_E_MASK = GENMASK(1, 0), + GRF_GPIO1B1_E_SHIFT = 2, + GRF_GPIO1B1_E_MASK = GENMASK(3, 2), + GRF_GPIO1B2_E_SHIFT = 4, + GRF_GPIO1B2_E_MASK = GENMASK(5, 4), + GRF_GPIO1B3_E_SHIFT = 6, + GRF_GPIO1B3_E_MASK = GENMASK(7, 6), + GRF_GPIO1B4_E_SHIFT = 8, + GRF_GPIO1B4_E_MASK = GENMASK(9, 8), + GRF_GPIO1B5_E_SHIFT = 10, + GRF_GPIO1B5_E_MASK = GENMASK(11, 10), + GRF_GPIO1B6_E_SHIFT = 12, + GRF_GPIO1B6_E_MASK = GENMASK(13, 12), + GRF_GPIO1B7_E_SHIFT = 14, + GRF_GPIO1B7_E_MASK = GENMASK(15, 14), + + /* GRF_GPIO1C_E */ + GRF_GPIO1C0_E_SHIFT = 0, + GRF_GPIO1C0_E_MASK = GENMASK(1, 0), + GRF_GPIO1C1_E_SHIFT = 2, + GRF_GPIO1C1_E_MASK = GENMASK(3, 2), + GRF_GPIO1C3_E_SHIFT = 6, + GRF_GPIO1C3_E_MASK = GENMASK(7, 6), + GRF_GPIO1C5_E_SHIFT = 10, + GRF_GPIO1C5_E_MASK = GENMASK(11, 10), + GRF_GPIO1C6_E_SHIFT = 12, + GRF_GPIO1C6_E_MASK = GENMASK(13, 12), + GRF_GPIO1C7_E_SHIFT = 14, + GRF_GPIO1C7_E_MASK = GENMASK(15, 14), + + /* GRF_GPIO1D_E */ + GRF_GPIO1D1_E_SHIFT = 2, + GRF_GPIO1D1_E_MASK = GENMASK(3, 2), }; struct rk3328_pinctrl_priv { @@ -344,6 +453,124 @@ static void pinctrl_rk3328_sdmmc_config(struct rk3328_grf_regs *grf, } } +#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP) +static void pinctrl_rk3328_gmac_config(struct rk3328_grf_regs *grf, int gmac_id) +{ + switch (gmac_id) { + case PERIPH_ID_GMAC: + /* set rgmii m1 pins mux */ + rk_clrsetreg(&grf->gpio1b_iomux, + GPIO1B0_SEL_MASK | + GPIO1B1_SEL_MASK | + GPIO1B2_SEL_MASK | + GPIO1B3_SEL_MASK | + GPIO1B4_SEL_MASK | + GPIO1B5_SEL_MASK | + GPIO1B6_SEL_MASK | + GPIO1B7_SEL_MASK, + GPIO1B0_GMAC_TXD1M1 << GPIO1B0_SEL_SHIFT | + GPIO1B1_GMAC_TXD0M1 << GPIO1B1_SEL_SHIFT | + GPIO1B2_GMAC_RXD1M1 << GPIO1B2_SEL_SHIFT | + GPIO1B3_GMAC_RXD0M1 << GPIO1B3_SEL_SHIFT | + GPIO1B4_GMAC_TXCLKM1 << GPIO1B4_SEL_SHIFT | + GPIO1B5_GMAC_RXCLKM1 << GPIO1B5_SEL_SHIFT | + GPIO1B6_GMAC_RXD3M1 << GPIO1B6_SEL_SHIFT | + GPIO1B7_GMAC_RXD2M1 << GPIO1B7_SEL_SHIFT); + + rk_clrsetreg(&grf->gpio1c_iomux, + GPIO1C0_SEL_MASK | + GPIO1C1_SEL_MASK | + GPIO1C3_SEL_MASK | + GPIO1C5_SEL_MASK | + GPIO1C6_SEL_MASK | + GPIO1C7_SEL_MASK, + GPIO1C0_GMAC_TXD3M1 << GPIO1C0_SEL_SHIFT | + GPIO1C1_GMAC_TXD2M1 << GPIO1C1_SEL_SHIFT | + GPIO1C3_GMAC_MDIOM1 << GPIO1C3_SEL_SHIFT | + GPIO1C5_GMAC_CLKM1 << GPIO1C5_SEL_SHIFT | + GPIO1C6_GMAC_RXDVM1 << GPIO1C6_SEL_SHIFT | + GPIO1C7_GMAC_MDCM1 << GPIO1C7_SEL_SHIFT); + + rk_clrsetreg(&grf->gpio1d_iomux, + GPIO1D1_SEL_MASK, + GPIO1D1_GMAC_TXENM1 << GPIO1D1_SEL_SHIFT); + + /* set rgmii m0 tx pins mux */ + rk_clrsetreg(&grf->gpio0b_iomux, + GPIO0B0_SEL_MASK | + GPIO0B4_SEL_MASK, + GPIO0B0_GAMC_CLKTXM0 << GPIO0B0_SEL_SHIFT | + GPIO0B4_GAMC_TXENM0 << GPIO0B4_SEL_SHIFT); + + rk_clrsetreg(&grf->gpio0c_iomux, + GPIO0C0_SEL_MASK | + GPIO0C1_SEL_MASK | + GPIO0C6_SEL_MASK | + GPIO0C7_SEL_MASK, + GPIO0C0_GAMC_TXD1M0 << GPIO0C0_SEL_SHIFT | + GPIO0C1_GAMC_TXD0M0 << GPIO0C1_SEL_SHIFT | + GPIO0C6_GAMC_TXD2M0 << GPIO0C6_SEL_SHIFT | + GPIO0C7_GAMC_TXD3M0 << GPIO0C7_SEL_SHIFT); + + rk_clrsetreg(&grf->gpio0d_iomux, + GPIO0D0_SEL_MASK, + GPIO0D0_GMAC_CLKM0 << GPIO0D0_SEL_SHIFT); + + /* set com mux */ + rk_clrsetreg(&grf->com_iomux, + IOMUX_SEL_GMAC_MASK | + IOMUX_SEL_GMACM1_OPTIMIZATION_MASK, + IOMUX_SEL_GMAC_M1 << IOMUX_SEL_GMAC_SHIFT | + IOMUX_SEL_GMACM1_OPTIMIZATION_AFTER << + IOMUX_SEL_GMACM1_OPTIMIZATION_SHIFT); + + /* + * set rgmii m1 tx pins to 12ma drive-strength, + * and clean others to 2ma. + */ + rk_clrsetreg(&grf->gpio1b_e, + GRF_GPIO1B0_E_MASK | + GRF_GPIO1B1_E_MASK | + GRF_GPIO1B2_E_MASK | + GRF_GPIO1B3_E_MASK | + GRF_GPIO1B4_E_MASK | + GRF_GPIO1B5_E_MASK | + GRF_GPIO1B6_E_MASK | + GRF_GPIO1B7_E_MASK, + 0x3 << GRF_GPIO1B0_E_SHIFT | + 0x3 << GRF_GPIO1B1_E_SHIFT | + 0x0 << GRF_GPIO1B2_E_SHIFT | + 0x0 << GRF_GPIO1B3_E_SHIFT | + 0x3 << GRF_GPIO1B4_E_SHIFT | + 0x0 << GRF_GPIO1B5_E_SHIFT | + 0x0 << GRF_GPIO1B6_E_SHIFT | + 0x0 << GRF_GPIO1B7_E_SHIFT); + + rk_clrsetreg(&grf->gpio1c_e, + GRF_GPIO1C0_E_MASK | + GRF_GPIO1C1_E_MASK | + GRF_GPIO1C3_E_MASK | + GRF_GPIO1C5_E_MASK | + GRF_GPIO1C6_E_MASK | + GRF_GPIO1C7_E_MASK, + 0x3 << GRF_GPIO1C0_E_SHIFT | + 0x3 << GRF_GPIO1C1_E_SHIFT | + 0x0 << GRF_GPIO1C3_E_SHIFT | + 0x0 << GRF_GPIO1C5_E_SHIFT | + 0x0 << GRF_GPIO1C6_E_SHIFT | + 0x0 << GRF_GPIO1C7_E_SHIFT); + + rk_clrsetreg(&grf->gpio1d_e, + GRF_GPIO1D1_E_MASK, + 0x3 << GRF_GPIO1D1_E_SHIFT); + break; + default: + debug("gmac id = %d iomux error!\n", gmac_id); + break; + } +} +#endif + static int rk3328_pinctrl_request(struct udevice *dev, int func, int flags) { struct rk3328_pinctrl_priv *priv = dev_get_priv(dev); @@ -380,6 +607,11 @@ static int rk3328_pinctrl_request(struct udevice *dev, int func, int flags) case PERIPH_ID_SDMMC1: pinctrl_rk3328_sdmmc_config(priv->grf, func); break; +#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP) + case PERIPH_ID_GMAC: + pinctrl_rk3328_gmac_config(priv->grf, func); + break; +#endif default: return -EINVAL; } @@ -414,6 +646,10 @@ static int rk3328_pinctrl_get_periph_id(struct udevice *dev, return PERIPH_ID_SDCARD; case 14: return PERIPH_ID_EMMC; +#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP) + case 24: + return PERIPH_ID_GMAC; +#endif } return -ENOENT; From patchwork Thu Nov 9 09:19:18 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Wu X-Patchwork-Id: 836242 X-Patchwork-Delegate: philipp.tomsich@theobroma-systems.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3yXd1r1SvRz9t5c for ; Thu, 9 Nov 2017 20:20:48 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id C38CEC2204B; Thu, 9 Nov 2017 09:20:25 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: ** X-Spam-Status: No, score=3.0 required=5.0 tests=RCVD_IN_MSPIKE_BL, RCVD_IN_MSPIKE_L5,RCVD_IN_SORBS_WEB autolearn=no autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 8344CC21F91; Thu, 9 Nov 2017 09:20:22 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id B132DC2204A; Thu, 9 Nov 2017 09:20:12 +0000 (UTC) Received: from lucky1.263xmail.com (lucky1.263xmail.com [211.157.147.131]) by lists.denx.de (Postfix) with ESMTPS id 759C2C22015 for ; Thu, 9 Nov 2017 09:20:11 +0000 (UTC) Received: from david.wu?rock-chips.com (unknown [192.168.167.158]) by lucky1.263xmail.com (Postfix) with ESMTP id 8525A96D12; Thu, 9 Nov 2017 17:20:07 +0800 (CST) X-263anti-spam: KSV:0; X-MAIL-GRAY: 1 X-MAIL-DELIVERY: 0 X-KSVirus-check: 0 X-ABS-CHECKED: 4 Received: from localhost.localdomain (localhost [127.0.0.1]) by smtp.263.net (Postfix) with ESMTPA id 07E523DD; Thu, 9 Nov 2017 17:19:57 +0800 (CST) X-RL-SENDER: david.wu@rock-chips.com X-FST-TO: philipp.tomsich@theobroma-systems.com X-SENDER-IP: 58.22.7.114 X-LOGIN-NAME: david.wu@rock-chips.com X-UNIQUE-TAG: X-ATTACHMENT-NUM: 0 X-SENDER: wdc@rock-chips.com X-DNS-TYPE: 0 Received: from localhost.localdomain (unknown [58.22.7.114]) by smtp.263.net (Postfix) whith ESMTP id 13528WJXC7O; Thu, 09 Nov 2017 17:19:59 +0800 (CST) From: David Wu To: philipp.tomsich@theobroma-systems.com, sjg@chromium.org Date: Thu, 9 Nov 2017 17:19:18 +0800 Message-Id: <1510219158-79015-1-git-send-email-david.wu@rock-chips.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1510217699-78401-1-git-send-email-david.wu@rock-chips.com> References: <1510217699-78401-1-git-send-email-david.wu@rock-chips.com> Cc: huangtao@rock-chips.com, joe.hershberger@ni.com, u-boot@lists.denx.de, David Wu , andy.yan@rock-chips.com Subject: [U-Boot] [PATCH v2 09/18] clk: rockchip: Add rk3328 gamc clock support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" The rk3328 soc has two gmac controllers, one is gmac2io, the other is gmac2phy. We use the gmac2io rgmii interface for 1000M phy here. Signed-off-by: David Wu Acked-by: Philipp Tomsich Reviewed-by: Philipp Tomsich --- Changes in v2: - New patch drivers/clk/rockchip/clk_rk3328.c | 20 ++++++++++++++++++++ include/dt-bindings/clock/rk3328-cru.h | 6 +++--- 2 files changed, 23 insertions(+), 3 deletions(-) diff --git a/drivers/clk/rockchip/clk_rk3328.c b/drivers/clk/rockchip/clk_rk3328.c index 540d910..0940474 100644 --- a/drivers/clk/rockchip/clk_rk3328.c +++ b/drivers/clk/rockchip/clk_rk3328.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -393,6 +394,22 @@ static ulong rk3328_i2c_set_clk(struct rk3328_cru *cru, ulong clk_id, uint hz) return DIV_TO_RATE(GPLL_HZ, src_clk_div); } +static int rockchip_mac_set_clk(struct rk3328_cru *cru, + int periph, uint freq) +{ + struct rk3328_grf_regs *grf; + + grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + /* Assuming mac_clk is fed by an external clock */ + rk_clrsetreg(&grf->soc_con[4], BIT(14), + BIT(14)); + + rk_clrsetreg(&grf->mac_con[1], BIT(10), + BIT(10)); + + return 0; +} + static ulong rk3328_mmc_get_clk(struct rk3328_cru *cru, uint clk_id) { u32 div, con, con_id; @@ -558,6 +575,9 @@ static ulong rk3328_clk_set_rate(struct clk *clk, ulong rate) case SCLK_I2C3: ret = rk3328_i2c_set_clk(priv->cru, clk->id, rate); break; + case SCLK_MAC2IO: + ret = rockchip_mac_set_clk(priv->cru, clk->id, rate); + break; case SCLK_PWM: ret = rk3328_pwm_set_clk(priv->cru, rate); break; diff --git a/include/dt-bindings/clock/rk3328-cru.h b/include/dt-bindings/clock/rk3328-cru.h index 6d8bf13..cdc0b33 100644 --- a/include/dt-bindings/clock/rk3328-cru.h +++ b/include/dt-bindings/clock/rk3328-cru.h @@ -86,6 +86,9 @@ #define SCLK_USB3OTG_SUSPEND 97 #define SCLK_REF_USB3OTG_SRC 98 #define SCLK_MAC2IO_SRC 99 +#define SCLK_MAC2IO 100 +#define SCLK_MAC2PHY 101 +#define SCLK_MAC2IO_EXT 102 /* dclk gates */ #define DCLK_LCDC 180 @@ -199,9 +202,6 @@ #define CLK_NR_CLKS (HCLK_HDCP + 1) -#define SCLK_MAC2IO 0 -#define SCLK_MAC2PHY 1 - #define CLKGRF_NR_CLKS (SCLK_MAC2PHY + 1) /* soft-reset indices */ From patchwork Thu Nov 9 09:21:53 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Wu X-Patchwork-Id: 836245 X-Patchwork-Delegate: philipp.tomsich@theobroma-systems.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3yXd4947ZPz9t5c for ; Thu, 9 Nov 2017 20:22:49 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 1E865C220C7; Thu, 9 Nov 2017 09:22:40 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: ** X-Spam-Status: No, score=3.0 required=5.0 tests=RCVD_IN_MSPIKE_BL, RCVD_IN_MSPIKE_L5,RCVD_IN_SORBS_WEB autolearn=no autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id E3FA8C22037; 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Thu, 09 Nov 2017 17:22:32 +0800 (CST) From: David Wu To: philipp.tomsich@theobroma-systems.com, sjg@chromium.org Date: Thu, 9 Nov 2017 17:21:53 +0800 Message-Id: <1510219313-79143-1-git-send-email-david.wu@rock-chips.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1510217699-78401-1-git-send-email-david.wu@rock-chips.com> References: <1510217699-78401-1-git-send-email-david.wu@rock-chips.com> Cc: huangtao@rock-chips.com, joe.hershberger@ni.com, u-boot@lists.denx.de, David Wu , andy.yan@rock-chips.com Subject: [U-Boot] [PATCH v2 11/18] rockchip: configs: Enable GMAC configs for evb-rk3328 X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Enable GMAC configs for evb-rk3328 Signed-off-by: David Wu Acked-by: Philipp Tomsich Reviewed-by: Philipp Tomsich --- Changes in v2: - New patch configs/evb-rk3328_defconfig | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/configs/evb-rk3328_defconfig b/configs/evb-rk3328_defconfig index 3b8b104..3d8c04d 100644 --- a/configs/evb-rk3328_defconfig +++ b/configs/evb-rk3328_defconfig @@ -17,6 +17,7 @@ CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_TIME=y CONFIG_ENV_IS_IN_MMC=y +CONFIG_NET_RANDOM_ETHADDR=y CONFIG_REGMAP=y CONFIG_SYSCON=y CONFIG_CLK=y @@ -24,6 +25,10 @@ CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y CONFIG_MMC_DW=y CONFIG_MMC_DW_ROCKCHIP=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_GMAC_ROCKCHIP=y +CONFIG_PHY=y CONFIG_PINCTRL=y CONFIG_PINCTRL_ROCKCHIP_RK3328=y CONFIG_DM_PMIC=y From patchwork Thu Nov 9 09:24:04 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Wu X-Patchwork-Id: 836247 X-Patchwork-Delegate: philipp.tomsich@theobroma-systems.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3yXd6b3tY5z9t5c for ; Thu, 9 Nov 2017 20:24:55 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 1F6F3C2213D; Thu, 9 Nov 2017 09:24:49 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: ** X-Spam-Status: No, score=3.0 required=5.0 tests=RCVD_IN_MSPIKE_BL, RCVD_IN_MSPIKE_L5,RCVD_IN_SORBS_WEB autolearn=no autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 0000FC220B7; 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Thu, 09 Nov 2017 17:24:43 +0800 (CST) From: David Wu To: philipp.tomsich@theobroma-systems.com, sjg@chromium.org Date: Thu, 9 Nov 2017 17:24:04 +0800 Message-Id: <1510219444-79270-1-git-send-email-david.wu@rock-chips.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1510217699-78401-1-git-send-email-david.wu@rock-chips.com> References: <1510217699-78401-1-git-send-email-david.wu@rock-chips.com> Cc: huangtao@rock-chips.com, joe.hershberger@ni.com, u-boot@lists.denx.de, David Wu , andy.yan@rock-chips.com Subject: [U-Boot] [PATCH v2 13/18] rockchip: dts: rk3328-evb: Enable gmac2io for rk3328-evb X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Add rk3328-evb gmac support. Signed-off-by: David Wu Acked-by: Philipp Tomsich Reviewed-by: Philipp Tomsich --- Changes in v2: - New patch arch/arm/dts/rk3328-evb.dts | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm/dts/rk3328-evb.dts b/arch/arm/dts/rk3328-evb.dts index 3dd9d81..336c2d5 100644 --- a/arch/arm/dts/rk3328-evb.dts +++ b/arch/arm/dts/rk3328-evb.dts @@ -15,6 +15,13 @@ stdout-path = &uart2; }; + gmac_clkin: external-gmac-clock { + compatible = "fixed-clock"; + clock-frequency = <125000000>; + clock-output-names = "gmac_clkin"; + #clock-cells = <0>; + }; + vcc3v3_sdmmc: sdmmc-pwren { compatible = "regulator-fixed"; regulator-name = "vcc3v3"; @@ -40,6 +47,13 @@ regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; }; + + vcc_phy: vcc-phy-regulator { + compatible = "regulator-fixed"; + regulator-name = "vcc_phy"; + regulator-always-on; + regulator-boot-on; + }; }; &saradc { @@ -74,6 +88,22 @@ status = "okay"; }; +&gmac2io { + phy-supply = <&vcc_phy>; + phy-mode = "rgmii"; + clock_in_out = "input"; + snps,reset-gpio = <&gpio1 RK_PC2 GPIO_ACTIVE_LOW>; + snps,reset-active-low; + snps,reset-delays-us = <0 10000 50000>; + assigned-clocks = <&cru SCLK_MAC2IO>, <&cru SCLK_MAC2IO_EXT>; + assigned-clock-parents = <&gmac_clkin>, <&gmac_clkin>; + pinctrl-names = "default"; + pinctrl-0 = <&rgmiim1_pins>; + tx_delay = <0x26>; + rx_delay = <0x11>; + status = "okay"; +}; + &usb_host0_ehci { status = "okay"; }; From patchwork Thu Nov 9 09:26:12 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Wu X-Patchwork-Id: 836250 X-Patchwork-Delegate: philipp.tomsich@theobroma-systems.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3yXdBp5LwRz9t5c for ; Thu, 9 Nov 2017 20:28:34 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id 5643FC22071; Thu, 9 Nov 2017 09:28:06 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: ** X-Spam-Status: No, score=3.0 required=5.0 tests=RCVD_IN_MSPIKE_BL, RCVD_IN_MSPIKE_L5,RCVD_IN_SORBS_WEB autolearn=no autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id CBEE7C22161; Thu, 9 Nov 2017 09:28:03 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 8B174C221A6; Thu, 9 Nov 2017 09:27:05 +0000 (UTC) Received: from lucky1.263xmail.com (lucky1.263xmail.com [211.157.147.135]) by lists.denx.de (Postfix) with ESMTPS id B4537C22164 for ; Thu, 9 Nov 2017 09:26:57 +0000 (UTC) Received: from david.wu?rock-chips.com (unknown [192.168.167.130]) by lucky1.263xmail.com (Postfix) with ESMTP id ED50E6C2E; Thu, 9 Nov 2017 17:26:53 +0800 (CST) X-263anti-spam: KSV:0; X-MAIL-GRAY: 1 X-MAIL-DELIVERY: 0 X-KSVirus-check: 0 X-ABS-CHECKED: 4 Received: from localhost.localdomain (localhost [127.0.0.1]) by smtp.263.net (Postfix) with ESMTPA id C9FA83B5; Thu, 9 Nov 2017 17:26:51 +0800 (CST) X-RL-SENDER: david.wu@rock-chips.com X-FST-TO: philipp.tomsich@theobroma-systems.com X-SENDER-IP: 58.22.7.114 X-LOGIN-NAME: david.wu@rock-chips.com X-UNIQUE-TAG: <67258df6239d163e9872606df0de0e9e> X-ATTACHMENT-NUM: 0 X-SENDER: wdc@rock-chips.com X-DNS-TYPE: 0 Received: from localhost.localdomain (unknown [58.22.7.114]) by smtp.263.net (Postfix) whith ESMTP id 7795ZE0BR4; Thu, 09 Nov 2017 17:26:53 +0800 (CST) From: David Wu To: philipp.tomsich@theobroma-systems.com, sjg@chromium.org Date: Thu, 9 Nov 2017 17:26:12 +0800 Message-Id: <1510219572-79393-1-git-send-email-david.wu@rock-chips.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1510217699-78401-1-git-send-email-david.wu@rock-chips.com> References: <1510217699-78401-1-git-send-email-david.wu@rock-chips.com> Cc: huangtao@rock-chips.com, joe.hershberger@ni.com, u-boot@lists.denx.de, David Wu , andy.yan@rock-chips.com Subject: [U-Boot] [PATCH v2 15/18] rockchip: pinctrl: Add rk322x gmac pinctrl support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Set gmac pins iomux and rgmii tx pins to 12ma drive-strength, clean others to 2ma. Signed-off-by: David Wu Acked-by: Philipp Tomsich Reviewed-by: Philipp Tomsich --- Changes in v2: - New patch drivers/pinctrl/rockchip/pinctrl_rk322x.c | 138 ++++++++++++++++++++++++++++++ 1 file changed, 138 insertions(+) diff --git a/drivers/pinctrl/rockchip/pinctrl_rk322x.c b/drivers/pinctrl/rockchip/pinctrl_rk322x.c index 28d9996..956e02f 100644 --- a/drivers/pinctrl/rockchip/pinctrl_rk322x.c +++ b/drivers/pinctrl/rockchip/pinctrl_rk322x.c @@ -470,6 +470,48 @@ enum { CON_IOMUX_PWM0SEL_MASK = 1 << CON_IOMUX_PWM0SEL_SHIFT, }; +/* GRF_GPIO2B_E */ +enum { + GRF_GPIO2B0_E_SHIFT = 0, + GRF_GPIO2B0_E_MASK = GENMASK(1, 0), + GRF_GPIO2B1_E_SHIFT = 2, + GRF_GPIO2B1_E_MASK = GENMASK(3, 2), + GRF_GPIO2B3_E_SHIFT = 6, + GRF_GPIO2B3_E_MASK = GENMASK(7, 6), + GRF_GPIO2B4_E_SHIFT = 8, + GRF_GPIO2B4_E_MASK = GENMASK(9, 8), + GRF_GPIO2B5_E_SHIFT = 10, + GRF_GPIO2B5_E_MASK = GENMASK(11, 10), + GRF_GPIO2B6_E_SHIFT = 12, + GRF_GPIO2B6_E_MASK = GENMASK(13, 12), +}; + +/* GRF_GPIO2C_E */ +enum { + GRF_GPIO2C0_E_SHIFT = 0, + GRF_GPIO2C0_E_MASK = GENMASK(1, 0), + GRF_GPIO2C1_E_SHIFT = 2, + GRF_GPIO2C1_E_MASK = GENMASK(3, 2), + GRF_GPIO2C2_E_SHIFT = 4, + GRF_GPIO2C2_E_MASK = GENMASK(5, 4), + GRF_GPIO2C3_E_SHIFT = 6, + GRF_GPIO2C3_E_MASK = GENMASK(7, 6), + GRF_GPIO2C4_E_SHIFT = 8, + GRF_GPIO2C4_E_MASK = GENMASK(9, 8), + GRF_GPIO2C5_E_SHIFT = 10, + GRF_GPIO2C5_E_MASK = GENMASK(11, 10), + GRF_GPIO2C6_E_SHIFT = 12, + GRF_GPIO2C6_E_MASK = GENMASK(13, 12), + GRF_GPIO2C7_E_SHIFT = 14, + GRF_GPIO2C7_E_MASK = GENMASK(15, 14), +}; + +/* GRF_GPIO2D_E */ +enum { + GRF_GPIO2D1_E_SHIFT = 2, + GRF_GPIO2D1_E_MASK = GENMASK(3, 2), +}; + struct rk322x_pinctrl_priv { struct rk322x_grf *grf; }; @@ -633,6 +675,95 @@ static void pinctrl_rk322x_sdmmc_config(struct rk322x_grf *grf, int mmc_id) } } +#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP) +static void pinctrl_rk322x_gmac_config(struct rk322x_grf *grf, int gmac_id) +{ + switch (gmac_id) { + case PERIPH_ID_GMAC: + /* set rgmii pins mux */ + rk_clrsetreg(&grf->gpio2b_iomux, + GPIO2B0_MASK | + GPIO2B1_MASK | + GPIO2B3_MASK | + GPIO2B4_MASK | + GPIO2B5_MASK | + GPIO2B6_MASK, + GPIO2B0_GMAC_RXDV << GPIO2B0_SHIFT | + GPIO2B1_GMAC_TXCLK << GPIO2B1_SHIFT | + GPIO2B3_GMAC_RXCLK << GPIO2B3_SHIFT | + GPIO2B4_GMAC_MDIO << GPIO2B4_SHIFT | + GPIO2B5_GMAC_TXEN << GPIO2B5_SHIFT | + GPIO2B6_GMAC_CLK << GPIO2B6_SHIFT); + + rk_clrsetreg(&grf->gpio2c_iomux, + GPIO2C0_MASK | + GPIO2C1_MASK | + GPIO2C2_MASK | + GPIO2C3_MASK | + GPIO2C4_MASK | + GPIO2C5_MASK | + GPIO2C6_MASK | + GPIO2C7_MASK, + GPIO2C0_GMAC_RXD1 << GPIO2C0_SHIFT | + GPIO2C1_GMAC_RXD0 << GPIO2C1_SHIFT | + GPIO2C2_GMAC_TXD1 << GPIO2C2_SHIFT | + GPIO2C3_GMAC_TXD0 << GPIO2C3_SHIFT | + GPIO2C4_GMAC_RXD3 << GPIO2C4_SHIFT | + GPIO2C5_GMAC_RXD2 << GPIO2C5_SHIFT | + GPIO2C6_GMAC_TXD2 << GPIO2C6_SHIFT | + GPIO2C7_GMAC_TXD3 << GPIO2C7_SHIFT); + + rk_clrsetreg(&grf->gpio2d_iomux, + GPIO2D1_MASK, + GPIO2D1_GMAC_MDC << GPIO2D1_SHIFT); + + /* + * set rgmii tx pins to 12ma drive-strength, + * clean others with 2ma. + */ + rk_clrsetreg(&grf->gpio2_e[1], + GRF_GPIO2B0_E_MASK | + GRF_GPIO2B1_E_MASK | + GRF_GPIO2B3_E_MASK | + GRF_GPIO2B4_E_MASK | + GRF_GPIO2B5_E_MASK | + GRF_GPIO2B6_E_MASK, + 0x0 << GRF_GPIO2B0_E_SHIFT | + 0x3 << GRF_GPIO2B1_E_SHIFT | + 0x0 << GRF_GPIO2B3_E_SHIFT | + 0x0 << GRF_GPIO2B4_E_SHIFT | + 0x3 << GRF_GPIO2B5_E_SHIFT | + 0x0 << GRF_GPIO2B6_E_SHIFT); + + rk_clrsetreg(&grf->gpio2_e[2], + GRF_GPIO2C0_E_MASK | + GRF_GPIO2C1_E_MASK | + GRF_GPIO2C2_E_MASK | + GRF_GPIO2C3_E_MASK | + GRF_GPIO2C4_E_MASK | + GRF_GPIO2C5_E_MASK | + GRF_GPIO2C6_E_MASK | + GRF_GPIO2C7_E_MASK, + 0x0 << GRF_GPIO2C0_E_SHIFT | + 0x0 << GRF_GPIO2C1_E_SHIFT | + 0x3 << GRF_GPIO2C2_E_SHIFT | + 0x3 << GRF_GPIO2C3_E_SHIFT | + 0x0 << GRF_GPIO2C4_E_SHIFT | + 0x0 << GRF_GPIO2C5_E_SHIFT | + 0x3 << GRF_GPIO2C6_E_SHIFT | + 0x3 << GRF_GPIO2C7_E_SHIFT); + + rk_clrsetreg(&grf->gpio2_e[3], + GRF_GPIO2D1_E_MASK, + 0x0 << GRF_GPIO2D1_E_SHIFT); + break; + default: + debug("gmac id = %d iomux error!\n", gmac_id); + break; + } +} +#endif + static int rk322x_pinctrl_request(struct udevice *dev, int func, int flags) { struct rk322x_pinctrl_priv *priv = dev_get_priv(dev); @@ -662,6 +793,9 @@ static int rk322x_pinctrl_request(struct udevice *dev, int func, int flags) case PERIPH_ID_SDMMC1: pinctrl_rk322x_sdmmc_config(priv->grf, func); break; + case PERIPH_ID_GMAC: + pinctrl_rk322x_gmac_config(priv->grf, func); + break; default: return -EINVAL; } @@ -701,6 +835,10 @@ static int rk322x_pinctrl_get_periph_id(struct udevice *dev, return PERIPH_ID_UART1; case 57: return PERIPH_ID_UART2; +#if CONFIG_IS_ENABLED(GMAC_ROCKCHIP) + case 24: + return PERIPH_ID_GMAC; +#endif } return -ENOENT; } From patchwork Thu Nov 9 09:27:12 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: David Wu X-Patchwork-Id: 836251 X-Patchwork-Delegate: philipp.tomsich@theobroma-systems.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 3yXdDs3Fwtz9t5n for ; Thu, 9 Nov 2017 20:30:21 +1100 (AEDT) Received: by lists.denx.de (Postfix, from userid 105) id C75D6C22192; Thu, 9 Nov 2017 09:29:07 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: ** X-Spam-Status: No, score=3.0 required=5.0 tests=RCVD_IN_MSPIKE_BL, RCVD_IN_MSPIKE_L5,RCVD_IN_SORBS_WEB autolearn=no autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id 9AED4C22182; Thu, 9 Nov 2017 09:28:17 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id A7796C2217D; Thu, 9 Nov 2017 09:28:00 +0000 (UTC) Received: from lucky1.263xmail.com (lucky1.263xmail.com [211.157.147.131]) by lists.denx.de (Postfix) with ESMTPS id 0B0D4C22113 for ; Thu, 9 Nov 2017 09:28:00 +0000 (UTC) Received: from david.wu?rock-chips.com (unknown [192.168.167.97]) by lucky1.263xmail.com (Postfix) with ESMTP id EE7F797008; Thu, 9 Nov 2017 17:27:54 +0800 (CST) X-263anti-spam: KSV:0; X-MAIL-GRAY: 1 X-MAIL-DELIVERY: 0 X-KSVirus-check: 0 X-ABS-CHECKED: 4 Received: from localhost.localdomain (localhost [127.0.0.1]) by smtp.263.net (Postfix) with ESMTPA id D1CD93DE; Thu, 9 Nov 2017 17:27:51 +0800 (CST) X-RL-SENDER: david.wu@rock-chips.com X-FST-TO: philipp.tomsich@theobroma-systems.com X-SENDER-IP: 58.22.7.114 X-LOGIN-NAME: david.wu@rock-chips.com X-UNIQUE-TAG: <135e82ded58614967f7e13aaa87a7c25> X-ATTACHMENT-NUM: 0 X-SENDER: wdc@rock-chips.com X-DNS-TYPE: 0 Received: from localhost.localdomain (unknown [58.22.7.114]) by smtp.263.net (Postfix) whith ESMTP id 4842G56G1T; Thu, 09 Nov 2017 17:27:53 +0800 (CST) From: David Wu To: philipp.tomsich@theobroma-systems.com, sjg@chromium.org Date: Thu, 9 Nov 2017 17:27:12 +0800 Message-Id: <1510219632-79453-1-git-send-email-david.wu@rock-chips.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1510217699-78401-1-git-send-email-david.wu@rock-chips.com> References: <1510217699-78401-1-git-send-email-david.wu@rock-chips.com> Cc: huangtao@rock-chips.com, joe.hershberger@ni.com, u-boot@lists.denx.de, David Wu , andy.yan@rock-chips.com Subject: [U-Boot] [PATCH v2 16/18] clk: rockchip: Add rk322x gamc clock support X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Assuming mac_clk is fed by an external clock, set clk_rmii_src clock select control register from IO for rgmii interface. Signed-off-by: David Wu Acked-by: Philipp Tomsich Reviewed-by: Philipp Tomsich --- Changes in v2: - New patch drivers/clk/rockchip/clk_rk322x.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/clk/rockchip/clk_rk322x.c b/drivers/clk/rockchip/clk_rk322x.c index e87267d..5fd27cd 100644 --- a/drivers/clk/rockchip/clk_rk322x.c +++ b/drivers/clk/rockchip/clk_rk322x.c @@ -239,6 +239,16 @@ static ulong rockchip_mmc_get_clk(struct rk322x_cru *cru, uint clk_general_rate, return DIV_TO_RATE(src_rate, div) / 2; } +static int rk322x_mac_set_clk(struct rk322x_cru *cru, + int periph, uint freq) +{ + /* Assuming mac_clk is fed by an external clock */ + rk_clrsetreg(&cru->cru_clksel_con[5], BIT(5), + BIT(5)); + + return 0; +} + static ulong rockchip_mmc_set_clk(struct rk322x_cru *cru, uint clk_general_rate, int periph, uint freq) { @@ -352,6 +362,9 @@ static ulong rk322x_clk_set_rate(struct clk *clk, ulong rate) case CLK_DDR: new_rate = rk322x_ddr_set_clk(priv->cru, rate); break; + case SCLK_MAC: + new_rate = rk322x_mac_set_clk(priv->cru, clk->id, rate); + break; default: return -ENOENT; }