From patchwork Fri Aug 23 15:21:09 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 1152268 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=wdc.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=wdc.com header.i=@wdc.com header.b="LWhzaOb/"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 46FQG44kzbz9sDQ for ; Sat, 24 Aug 2019 01:25:48 +1000 (AEST) Received: from localhost ([::1]:57992 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i1BRh-0001cE-E5 for incoming@patchwork.ozlabs.org; Fri, 23 Aug 2019 11:25:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59771) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i1BQr-0001bj-Es for qemu-devel@nongnu.org; Fri, 23 Aug 2019 11:24:54 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1i1BQq-00004u-0r for qemu-devel@nongnu.org; Fri, 23 Aug 2019 11:24:52 -0400 Received: from esa3.hgst.iphmx.com ([216.71.153.141]:38176) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1i1BQp-0008VZ-KE; Fri, 23 Aug 2019 11:24:51 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1566573891; x=1598109891; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=dNPHnBonHYmj24fakuU63K2w0RapOswOQO6wbRLxGds=; b=LWhzaOb/2uJdA5W3U9VCxeV+szHwhduyvwc0gkRkjMZmsWuRSr0y6M6T XaYmxX70432N+J7SVCVOQvOdgTrNB6maC/bvukXE784fPB6gohVm1y56N Kj5ggCfPcXwp8DUp+M5meIjZv29dok6zDKxaXIgnxNiizIqwhSZdpNwNf bAlbaBZXLqmKFFCDNWqChMUnFoIuMHuaiIeTWRTkIRFCrtvVZ/YTVKFSc 5nxGDZvvbeXVQeLrMUFy9wYZbj8dCVaC7WiuGDjnVFEvCuaISUUSuMjWr ps7CWxaEvL72j7tsqXu8l+8JYBq52MTst5Wt5CVZOvt9bc+aP/QnvGV8f A==; IronPort-SDR: ZWxp4ADug0MKqwU3hTcGLZ0lWp4M9GyEmhOgLXEPObRmUKCw2wXaidrF3cIzDfaqnp+An5W0L2 LKP/IbzEA9hNVL3uz2izUzogeBCtnQJxnyhf9Q53RHQjKH9Quu+mxpRzjS3mqWTcxqSKfNm61e 0DUcXAc32wWzunM8P5LXvJn/mDNogL9l1jozq62pxzMM8/nXPicFnZW2XJvkAtzeo1iYd2gLJe Nl249gtDRtsS14pYX1qIFrOOkN9PM7F6Q1NB1fubYkCnMbZku9wEPEBdrCBJGLBRMzn+6OfdJK hk0= X-IronPort-AV: E=Sophos;i="5.64,421,1559491200"; d="scan'208";a="121112422" Received: from uls-op-cesaip02.wdc.com (HELO uls-op-cesaep02.wdc.com) ([199.255.45.15]) by ob1.hgst.iphmx.com with ESMTP; 23 Aug 2019 23:24:49 +0800 IronPort-SDR: molqb5i362KXk2lCrBNIGGyW2LmKx+dLKSYHvySIflLfVPhng1ENWbJcxjc2vdd+KwqJG7Z6L/ I4JTHM/MmciFGJdy2Z/ELIZVyRK7FCYAQcWB5A34eXMC/sZg2msZImWoC/Pz26z6j84i0ZrcMW fPVXhuUa8Hnnxh9y6367u1D3RXEF/LD5to4kxeoUmKYVvNYzbBjK/53sFHwLoPmYrRoVTfEh2F G6xHYeTgd8eRhq1i/gwoBxSbAGBMPdRRMv/vyR+iqvsSOsvRcDJTIVSRBzbmVS4LmvNu5SCiGr UjNNsppLEoNyI0QpzFeis4jM Received: from uls-op-cesaip02.wdc.com ([10.248.3.37]) by uls-op-cesaep02.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Aug 2019 08:22:06 -0700 IronPort-SDR: qwiURRZn8R6rwP3yyifFkFWs31Dq7fcZ7zXXd0CS1fWtCnqkTH2LClm1tjgDmzZzKEFayEJtET HA2KNHykTj6Mq0yM9G1KsLPWTMZ8/a4MBFqBLDUJVN9fPPpsSpcQzrEKoKjMaXQTxOJNi/crLM ko8FdMXigcYEzF7fhRUlc0hCwRKsn7FlHma6Dqly2iCkdrRV1ZfRGn+JmLIcPZhR/dEhfEfOVS HrR/Hi4oS1gNWY7Cjt1GHtHEny/wYfaXuiYOyEJZ0qaBLYQpL935Dxp3x4p4KglXNgp1bfA5Fv mX8= WDCIronportException: Internal Received: from risc6-mainframe.sdcorp.global.sandisk.com (HELO risc6-mainframe.int.fusionio.com) ([10.196.157.58]) by uls-op-cesaip02.wdc.com with ESMTP; 23 Aug 2019 08:24:49 -0700 From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Date: Fri, 23 Aug 2019 08:21:09 -0700 Message-Id: <6532e1a327feada5bbd0631ed6ea72ec32528936.1566573576.git.alistair.francis@wdc.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: References: MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: FreeBSD 9.x X-Received-From: 216.71.153.141 Subject: [Qemu-devel] [PATCH v4 1/7] target/riscv: Don't set write permissions on dirty PTEs X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, palmer@sifive.com, alistair.francis@wdc.com, bmeng.cn@gmail.com Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Setting write permission on dirty PTEs results in userspace inside a Hypervisor guest (VU) becoming corrupted. This appears to be because it ends up with write permission in the second stage translation in cases where we aren't doing a store. Signed-off-by: Alistair Francis Reviewed-by: Bin Meng --- target/riscv/cpu_helper.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index e32b6126af..f027be7f16 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -340,10 +340,8 @@ restart: if ((pte & PTE_X)) { *prot |= PAGE_EXEC; } - /* add write permission on stores or if the page is already dirty, - so that we TLB miss on later writes to update the dirty bit */ - if ((pte & PTE_W) && - (access_type == MMU_DATA_STORE || (pte & PTE_D))) { + /* add write permission on stores */ + if ((pte & PTE_W) && (access_type == MMU_DATA_STORE)) { *prot |= PAGE_WRITE; } return TRANSLATE_SUCCESS; From patchwork Fri Aug 23 15:21:12 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 1152272 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=wdc.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=wdc.com header.i=@wdc.com header.b="mz89vmlI"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 46FQL50mgHz9s7T for ; Sat, 24 Aug 2019 01:29:17 +1000 (AEST) Received: from localhost ([::1]:58108 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i1BV4-0005UU-Gn for incoming@patchwork.ozlabs.org; Fri, 23 Aug 2019 11:29:14 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59782) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1i1BQr-0001bk-Pv for qemu-devel@nongnu.org; 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IronPort-SDR: nPCuerFax3eWZFHT5xS7sCfbCf4jNXmZDzQupxQG7ixRWY6LaIIgL+zhsQ82yNe1Eoq8WEx5Fi /E24+92TEepUUEkYJr9w0j5dYMOe0WqDnz0/YTSYNrvI/Ynx5SeAW/PNU2uZMOBsLwTVG7mb5H axouIOFwYb8ZmnocYSDRwi0ger1qe8ri7IokPRBAV+2OeN5qqcI36r90/6uH3OXKRMLFccrk/b 48Fogdave0PrUOPaAOSTEpdh1lBexDTQ78i5t8e9Pndyd/WSuUqH98b5R2lU2mWRC4wQJrD5JW Nwg= X-IronPort-AV: E=Sophos;i="5.64,421,1559491200"; d="scan'208";a="121112423" Received: from uls-op-cesaip02.wdc.com (HELO uls-op-cesaep02.wdc.com) ([199.255.45.15]) by ob1.hgst.iphmx.com with ESMTP; 23 Aug 2019 23:24:52 +0800 IronPort-SDR: hGaNfzoZVxWkNRv5DVXn6psL7cSLJPxSA4eeVmp5lthWS05xhEeNiaQf3b0X45dKrHyb2/AN6z lIj1KlznQUxm51vlT1iaPsJjRd4h5FftJMoLyvIqMArz8odysr9jYgjKC0Abs1SS5XTYId6ykR NVZ4HSIv+U8wjozD4ruKWerWBrAWQAhATA+GXhVCAMXNPOjkjb8cRXxVCaEJ77OBZRICiEagMA w+OmUNTEcHjDpPf6ryhuXUHowt5zl4KmVnQR4DM9QnwfGfeKu59fO1Evo3K8jmqlUpRkfxyBKj ACbidL7steMTmtgwUiuzFCWz Received: from uls-op-cesaip02.wdc.com ([10.248.3.37]) by uls-op-cesaep02.wdc.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Aug 2019 08:22:09 -0700 IronPort-SDR: qy5CXmtGjA6wMmjZ7kVjnApH0FmPBaQCnD2uBgudTehQL8lpwToVCNVYbMPxmittanRubcNuul z74SK/6NnETwIwt/UnMavH7v/OqzMxPV1po0rc9eY3RXksEd6uhvp3Ari5ijI5VOli46PvwScX FQY9nHftWbM5AwXJar/kMdRLdYjroKQ/95EZOkM7nwdL8jb3xpeEWZ/u/FFNqZE0tMr0TfDLDD 1TwO6btDcp093TtZkKwB1UgkHdOZOcNg8K8n93rRmMkmtoj7uah7fxgJ1cL8I0OMMuJa9q7AWa yRs= WDCIronportException: Internal Received: from risc6-mainframe.sdcorp.global.sandisk.com (HELO risc6-mainframe.int.fusionio.com) ([10.196.157.58]) by uls-op-cesaip02.wdc.com with ESMTP; 23 Aug 2019 08:24:52 -0700 From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Date: Fri, 23 Aug 2019 08:21:12 -0700 Message-Id: X-Mailer: git-send-email 2.22.0 In-Reply-To: References: MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: FreeBSD 9.x X-Received-From: 216.71.153.141 Subject: [Qemu-devel] [PATCH v4 2/7] riscv: plic: Remove unused interrupt functions X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, palmer@sifive.com, alistair.francis@wdc.com, bmeng.cn@gmail.com Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Alistair Francis Reviewed-by: Jonathan Behrens Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Chih-Min Chao Reviewed-by: Bin Meng --- hw/riscv/sifive_plic.c | 12 ------------ include/hw/riscv/sifive_plic.h | 3 --- 2 files changed, 15 deletions(-) diff --git a/hw/riscv/sifive_plic.c b/hw/riscv/sifive_plic.c index 64a1a10380..98e4304b66 100644 --- a/hw/riscv/sifive_plic.c +++ b/hw/riscv/sifive_plic.c @@ -162,18 +162,6 @@ static void sifive_plic_update(SiFivePLICState *plic) } } -void sifive_plic_raise_irq(SiFivePLICState *plic, uint32_t irq) -{ - sifive_plic_set_pending(plic, irq, true); - sifive_plic_update(plic); -} - -void sifive_plic_lower_irq(SiFivePLICState *plic, uint32_t irq) -{ - sifive_plic_set_pending(plic, irq, false); - sifive_plic_update(plic); -} - static uint32_t sifive_plic_claim(SiFivePLICState *plic, uint32_t addrid) { int i, j; diff --git a/include/hw/riscv/sifive_plic.h b/include/hw/riscv/sifive_plic.h index b0edba2884..4421e81249 100644 --- a/include/hw/riscv/sifive_plic.h +++ b/include/hw/riscv/sifive_plic.h @@ -69,9 +69,6 @@ typedef struct SiFivePLICState { uint32_t aperture_size; } SiFivePLICState; -void sifive_plic_raise_irq(SiFivePLICState *plic, uint32_t irq); -void sifive_plic_lower_irq(SiFivePLICState *plic, uint32_t irq); - DeviceState *sifive_plic_create(hwaddr addr, char *hart_config, uint32_t num_sources, uint32_t num_priorities, uint32_t priority_base, uint32_t pending_base, From patchwork Fri Aug 23 15:21:14 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 1152274 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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23 Aug 2019 08:22:12 -0700 IronPort-SDR: 6C7Q1t4ltlnGsc7UZfA1ZJf+9LENhRBr6fZhqwRZUC6LxVEFXFNc7CE/H4MwsavpPHpK/raeTq zsY9y/yozsr6qW+4MwGZE14W+uYtgJvUfGlPcrLBkNOb3QKlGxG8oR8qmKqaWcM44QSOA4fgIG JkiuFtB9INOMVvX3WfVIeSbRxSx4jRt4YHppIYm0LNtH1SjsAmg7pwdFHPqzUJamlsGQuQZr+e gNhG2MUWAPglslWs1jOt8/6yDqW0m8LVOMW+Z3O7K7Gld379tojCaoO5+nKTytJrZZAqViK6C7 dMc= WDCIronportException: Internal Received: from risc6-mainframe.sdcorp.global.sandisk.com (HELO risc6-mainframe.int.fusionio.com) ([10.196.157.58]) by uls-op-cesaip02.wdc.com with ESMTP; 23 Aug 2019 08:24:55 -0700 From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Date: Fri, 23 Aug 2019 08:21:14 -0700 Message-Id: <5cc26abb98a9534720f09674b4b9caafb8f2cf0a.1566573576.git.alistair.francis@wdc.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: References: MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: FreeBSD 9.x X-Received-From: 216.71.153.141 Subject: [Qemu-devel] [PATCH v4 3/7] target/riscv: Create function to test if FP is enabled X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, palmer@sifive.com, alistair.francis@wdc.com, bmeng.cn@gmail.com Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Let's create a function that tests if floating point support is enabled. We can then protect all floating point operations based on if they are enabled. This patch so far doesn't change anything, it's just preparing for the Hypervisor support for floating point operations. Signed-off-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Christophe de Dinechin Reviewed-by: Chih-Min Chao Reviewed-by: Bin Meng --- target/riscv/cpu.h | 6 +++++- target/riscv/cpu_helper.c | 10 ++++++++++ target/riscv/csr.c | 20 +++++++++++--------- 3 files changed, 26 insertions(+), 10 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 240b31e2eb..eb7b5b0af3 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -255,6 +255,7 @@ void riscv_cpu_do_interrupt(CPUState *cpu); int riscv_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request); +bool riscv_cpu_fp_enabled(CPURISCVState *env); int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch); hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, @@ -298,7 +299,10 @@ static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, #ifdef CONFIG_USER_ONLY *flags = TB_FLAGS_MSTATUS_FS; #else - *flags = cpu_mmu_index(env, 0) | (env->mstatus & MSTATUS_FS); + *flags = cpu_mmu_index(env, 0); + if (riscv_cpu_fp_enabled(env)) { + *flags |= env->mstatus & MSTATUS_FS; + } #endif } diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index f027be7f16..225e407cff 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -71,6 +71,16 @@ bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request) #if !defined(CONFIG_USER_ONLY) +/* Return true is floating point support is currently enabled */ +bool riscv_cpu_fp_enabled(CPURISCVState *env) +{ + if (env->mstatus & MSTATUS_FS) { + return true; + } + + return false; +} + int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts) { CPURISCVState *env = &cpu->env; diff --git a/target/riscv/csr.c b/target/riscv/csr.c index e0d4586760..2789215b5e 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -46,7 +46,7 @@ void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops) static int fs(CPURISCVState *env, int csrno) { #if !defined(CONFIG_USER_ONLY) - if (!env->debugger && !(env->mstatus & MSTATUS_FS)) { + if (!env->debugger && !riscv_cpu_fp_enabled(env)) { return -1; } #endif @@ -108,7 +108,7 @@ static int pmp(CPURISCVState *env, int csrno) static int read_fflags(CPURISCVState *env, int csrno, target_ulong *val) { #if !defined(CONFIG_USER_ONLY) - if (!env->debugger && !(env->mstatus & MSTATUS_FS)) { + if (!env->debugger && !riscv_cpu_fp_enabled(env)) { return -1; } #endif @@ -119,7 +119,7 @@ static int read_fflags(CPURISCVState *env, int csrno, target_ulong *val) static int write_fflags(CPURISCVState *env, int csrno, target_ulong val) { #if !defined(CONFIG_USER_ONLY) - if (!env->debugger && !(env->mstatus & MSTATUS_FS)) { + if (!env->debugger && !riscv_cpu_fp_enabled(env)) { return -1; } env->mstatus |= MSTATUS_FS; @@ -131,7 +131,7 @@ static int write_fflags(CPURISCVState *env, int csrno, target_ulong val) static int read_frm(CPURISCVState *env, int csrno, target_ulong *val) { #if !defined(CONFIG_USER_ONLY) - if (!env->debugger && !(env->mstatus & MSTATUS_FS)) { + if (!env->debugger && !riscv_cpu_fp_enabled(env)) { return -1; } #endif @@ -142,7 +142,7 @@ static int read_frm(CPURISCVState *env, int csrno, target_ulong *val) static int write_frm(CPURISCVState *env, int csrno, target_ulong val) { #if !defined(CONFIG_USER_ONLY) - if (!env->debugger && !(env->mstatus & MSTATUS_FS)) { + if (!env->debugger && !riscv_cpu_fp_enabled(env)) { return -1; } env->mstatus |= MSTATUS_FS; @@ -154,7 +154,7 @@ static int write_frm(CPURISCVState *env, int csrno, target_ulong val) static int read_fcsr(CPURISCVState *env, int csrno, target_ulong *val) { #if !defined(CONFIG_USER_ONLY) - if (!env->debugger && !(env->mstatus & MSTATUS_FS)) { + if (!env->debugger && !riscv_cpu_fp_enabled(env)) { return -1; } #endif @@ -166,7 +166,7 @@ static int read_fcsr(CPURISCVState *env, int csrno, target_ulong *val) static int write_fcsr(CPURISCVState *env, int csrno, target_ulong val) { #if !defined(CONFIG_USER_ONLY) - if (!env->debugger && !(env->mstatus & MSTATUS_FS)) { + if (!env->debugger && !riscv_cpu_fp_enabled(env)) { return -1; } env->mstatus |= MSTATUS_FS; @@ -307,6 +307,7 @@ static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val) { target_ulong mstatus = env->mstatus; target_ulong mask = 0; + int dirty; /* flush tlb on mstatus fields that affect VM */ if (env->priv_ver <= PRIV_VERSION_1_09_1) { @@ -340,8 +341,9 @@ static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val) mstatus = (mstatus & ~mask) | (val & mask); - int dirty = ((mstatus & MSTATUS_FS) == MSTATUS_FS) | - ((mstatus & MSTATUS_XS) == MSTATUS_XS); + dirty = (riscv_cpu_fp_enabled(env) && + ((mstatus & MSTATUS_FS) == MSTATUS_FS)) | + ((mstatus & MSTATUS_XS) == MSTATUS_XS); mstatus = set_field(mstatus, MSTATUS_SD, dirty); env->mstatus = mstatus; From patchwork Fri Aug 23 15:21:17 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 1152270 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=wdc.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=wdc.com header.i=@wdc.com header.b="fzW9C2t7"; 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23 Aug 2019 08:24:57 -0700 From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Date: Fri, 23 Aug 2019 08:21:17 -0700 Message-Id: <10379ff923d36b17dcca0a9ef6c0599b346106be.1566573576.git.alistair.francis@wdc.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: References: MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: FreeBSD 9.x X-Received-From: 216.71.153.141 Subject: [Qemu-devel] [PATCH v4 4/7] target/riscv: Update the Hypervisor CSRs to v0.4 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, palmer@sifive.com, alistair.francis@wdc.com, bmeng.cn@gmail.com Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Update the Hypervisor CSR addresses to match the v0.4 spec. Signed-off-by: Alistair Francis Reviewed-by: Chih-Min Chao Reviewed-by: Bin Meng --- target/riscv/cpu_bits.h | 35 ++++++++++++++++++----------------- 1 file changed, 18 insertions(+), 17 deletions(-) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 11f971ad5d..e99834856c 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -173,6 +173,24 @@ #define CSR_SPTBR 0x180 #define CSR_SATP 0x180 +/* Hpervisor CSRs */ +#define CSR_HSTATUS 0x600 +#define CSR_HEDELEG 0x602 +#define CSR_HIDELEG 0x603 +#define CSR_HCOUNTERNEN 0x606 +#define CSR_HGATP 0x680 + +#if defined(TARGET_RISCV32) +#define HGATP_MODE SATP32_MODE +#define HGATP_VMID SATP32_ASID +#define HGATP_PPN SATP32_PPN +#endif +#if defined(TARGET_RISCV64) +#define HGATP_MODE SATP64_MODE +#define HGATP_VMID SATP64_ASID +#define HGATP_PPN SATP64_PPN +#endif + /* Physical Memory Protection */ #define CSR_PMPCFG0 0x3a0 #define CSR_PMPCFG1 0x3a1 @@ -206,23 +224,6 @@ #define CSR_DPC 0x7b1 #define CSR_DSCRATCH 0x7b2 -/* Hpervisor CSRs */ -#define CSR_HSTATUS 0xa00 -#define CSR_HEDELEG 0xa02 -#define CSR_HIDELEG 0xa03 -#define CSR_HGATP 0xa80 - -#if defined(TARGET_RISCV32) -#define HGATP_MODE SATP32_MODE -#define HGATP_ASID SATP32_ASID -#define HGATP_PPN SATP32_PPN -#endif -#if defined(TARGET_RISCV64) -#define HGATP_MODE SATP64_MODE -#define HGATP_ASID SATP64_ASID -#define HGATP_PPN SATP64_PPN -#endif - /* Performance Counters */ #define CSR_MHPMCOUNTER3 0xb03 #define CSR_MHPMCOUNTER4 0xb04 From patchwork Fri Aug 23 15:21:19 2019 Content-Type: text/plain; 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23 Aug 2019 08:22:17 -0700 IronPort-SDR: qRhFM2xJcFBWr4wozziC5WSspFxFvYNvKOZOHKVn9KQcQRJaLe/ttfGaihiJupp4d7dQg/7HQE xxt9x3jIR5sccJl4Y8+MdyIroB0NSi0hWMfGxwopUb7Kc5qoD2e7rpYy/iqW3Sc7V9G0gnR4ZS g/XBh/MTneNfwLxNvxNN/L3tCiOKJj5JcYCWuzr0/oSBHxvY0D098eMJ5hwBkp6h/VtusamQGt UhArcHOIIIR0OS3bkC9wuT6qzk6ZQ/NQXgwbCQP8ii8gelgtztGC3KSjVaTDkPWXx5FYRRMMNm dWg= WDCIronportException: Internal Received: from risc6-mainframe.sdcorp.global.sandisk.com (HELO risc6-mainframe.int.fusionio.com) ([10.196.157.58]) by uls-op-cesaip02.wdc.com with ESMTP; 23 Aug 2019 08:25:00 -0700 From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Date: Fri, 23 Aug 2019 08:21:19 -0700 Message-Id: <2101ad1b795800a6f7cbf52d47de5cb0e86c568a.1566573576.git.alistair.francis@wdc.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: References: MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: FreeBSD 9.x X-Received-From: 216.71.153.141 Subject: [Qemu-devel] [PATCH v4 5/7] target/riscv: Use both register name and ABI name X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, palmer@sifive.com, alistair.francis@wdc.com, bmeng.cn@gmail.com Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" From: Atish Patra Use both the generic register name and ABI name for the general purpose registers and floating point registers. Signed-off-by: Atish Patra Signed-off-by: Alistair Francis Reviewed-by: Bin Meng --- target/riscv/cpu.c | 19 +++++++++++-------- 1 file changed, 11 insertions(+), 8 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 6d52f97d7c..f13e298a36 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -34,17 +34,20 @@ static const char riscv_exts[26] = "IEMAFDQCLBJTPVNSUHKORWXYZG"; const char * const riscv_int_regnames[] = { - "zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", - "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5", - "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7", - "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6" + "x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1", + "x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3", + "x14/a4", "x15/a5", "x16/a6", "x17/a7", "x18/s2", "x19/s3", "x20/s4", + "x21/s5", "x22/s6", "x23/s7", "x24/s8", "x25/s9", "x26/s10", "x27/s11", + "x28/t3", "x29/t4", "x30/t5", "x31/t6" }; const char * const riscv_fpr_regnames[] = { - "ft0", "ft1", "ft2", "ft3", "ft4", "ft5", "ft6", "ft7", - "fs0", "fs1", "fa0", "fa1", "fa2", "fa3", "fa4", "fa5", - "fa6", "fa7", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7", - "fs8", "fs9", "fs10", "fs11", "ft8", "ft9", "ft10", "ft11" + "f0/ft0", "f1/ft1", "f2/ft2", "f3/ft3", "f4/ft4", "f5/ft5", + "f6/ft6", "f7/ft7", "f8/fs0", "f9/fs1", "f10/fa0", "f11/fa1", + "f12/fa2", "f13/fa3", "f14/fa4", "f15/fa5", "f16/fa6", "f17/fa7", + "f18/fs2", "f19/fs3", "f20/fs4", "f21/fs5", "f22/fs6", "f23/fs7", + "f24/fs8", "f25/fs9", "f26/fs10", "f27/fs11", "f28/ft8", "f29/ft9", + "f30/ft10", "f31/ft11" }; const char * const riscv_excp_names[] = { From patchwork Fri Aug 23 15:21:22 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 1152273 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=wdc.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=wdc.com header.i=@wdc.com header.b="k98NNE0q"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 46FQLl3xDlz9s7T for ; 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23 Aug 2019 08:22:20 -0700 IronPort-SDR: EwS7PAfNKiwm/tvCripTUaMpPp7m7IH/tbJs8WCFr7YIUSYj33fQketA+iXOOR1WzB3n2oVjlg Y+CtacpxEKBJysuC7soZxg2Yg22sttJDXdFx21WQSIDvkR1Nk620W3Tqmp3qmEpuLm/upUVR3l rUqaLgSEH+R/zxYfSrKUMzfV37e3gj1xsxcB/jb6o86/cFN33BqLcEQ7BGZndsc4qucTvw4tyA JXNMpGgekcq5NznnZH5TJTMWe1cng4pAu6GKQ12TneAcsktbDBQc1AeRrWLMc8IyR1FljoPZot CuQ= WDCIronportException: Internal Received: from risc6-mainframe.sdcorp.global.sandisk.com (HELO risc6-mainframe.int.fusionio.com) ([10.196.157.58]) by uls-op-cesaip02.wdc.com with ESMTP; 23 Aug 2019 08:25:03 -0700 From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Date: Fri, 23 Aug 2019 08:21:22 -0700 Message-Id: <0b18d5784d392d315bc0c6df8b7c258022f1f6d5.1566573576.git.alistair.francis@wdc.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: References: MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: FreeBSD 9.x X-Received-From: 216.71.153.141 Subject: [Qemu-devel] [PATCH v4 6/7] target/riscv: Fix mstatus dirty mask X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, palmer@sifive.com, alistair.francis@wdc.com, bmeng.cn@gmail.com Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Signed-off-by: Alistair Francis Reviewed-by: Bin Meng --- target/riscv/csr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 2789215b5e..f767ad24be 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -335,7 +335,7 @@ static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val) * RV32: MPV and MTL are not in mstatus. The current plan is to * add them to mstatush. For now, we just don't support it. */ - mask |= MSTATUS_MPP | MSTATUS_MPV; + mask |= MSTATUS_MTL | MSTATUS_MPV; #endif } From patchwork Fri Aug 23 15:21:25 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alistair Francis X-Patchwork-Id: 1152275 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=nongnu.org (client-ip=209.51.188.17; helo=lists.gnu.org; envelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=wdc.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=wdc.com header.i=@wdc.com header.b="jmIVx291"; dkim-atps=neutral Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 46FQVX3RfXz9sN6 for ; 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23 Aug 2019 08:22:23 -0700 IronPort-SDR: r8mUkXi/N67n/I5pkxTK9YVjoQ7lYovu32DTi9+iFfwyaWBjzyan8ln+u0FzHihDD0mN/V/Hcf I7P70KDOYcuEVGKJN39SNFvIaRAqKNssTgKu+Au9Od5Y+pGviq/4CyiSKwqRpyqyjcYUkUUtUd xGDPlxwZRu/3eDZbxVgFEut12LEkR9pabH/bP9kn/KJ6eb2rcjIUn1+8EShIRYBgSlzjb+C/3E 3IRoH6ld1LQpa+LUwNRhTxsBw2ujixyLyrixjhiiMvO5rqykUNuhBDpKyqL8FYzoVV/DCqI79u yUo= WDCIronportException: Internal Received: from risc6-mainframe.sdcorp.global.sandisk.com (HELO risc6-mainframe.int.fusionio.com) ([10.196.157.58]) by uls-op-cesaip01.wdc.com with ESMTP; 23 Aug 2019 08:25:05 -0700 From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Date: Fri, 23 Aug 2019 08:21:25 -0700 Message-Id: <066a2c520c38b0c175c052d6a3385d5661764833.1566573576.git.alistair.francis@wdc.com> X-Mailer: git-send-email 2.22.0 In-Reply-To: References: MIME-Version: 1.0 X-detected-operating-system: by eggs.gnu.org: FreeBSD 9.x X-Received-From: 216.71.154.42 Subject: [Qemu-devel] [PATCH v4 7/7] target/riscv: Use TB_FLAGS_MSTATUS_FS for floating point X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: alistair23@gmail.com, palmer@sifive.com, alistair.francis@wdc.com, bmeng.cn@gmail.com Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" Use the TB_FLAGS_MSTATUS_FS macro when enabling floating point in the tb flags. Signed-off-by: Alistair Francis Reviewed-by: Palmer Dabbelt --- target/riscv/cpu.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index eb7b5b0af3..0347be453b 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -301,7 +301,7 @@ static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, #else *flags = cpu_mmu_index(env, 0); if (riscv_cpu_fp_enabled(env)) { - *flags |= env->mstatus & MSTATUS_FS; + *flags |= TB_FLAGS_MSTATUS_FS; } #endif }