From patchwork Fri Aug 23 07:45:54 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mihailo Stojanovic X-Patchwork-Id: 1152015 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-507574-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=rt-rk.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="UDTykC2y"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 46FD3m3gHtz9sBp for ; Fri, 23 Aug 2019 17:46:09 +1000 (AEST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id; q=dns; s=default; b=xsYvp5dXBVcL ujn1u1iQaPmRXZRAsGdpa4llfB3zwJ6TuEAf7LuTkEIY4GcxuBw7lUHzNDgBd4jH h0ltfcxO8forktfTZ78Od62pa5Nnw8UFJGRbW1/lcslhrrwBEddVjJO2p1oUptHr yMgsiTfod6Twi0hjmsY8tdFIO3CReEA= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id; s=default; bh=Mq/8N5OKLiDQkJHcu0 8N4plQqjQ=; b=UDTykC2yRuSTJvDJQNhRaK8R4u4hrIGXHSMlfxL8+ojQlBbaJ/ VmQeV04Pr6YkxR52ytvSL3xhC6Zxi2D5jOxi0uSMx/6pR60p82016L9aDELFDNhV FcW2bU+GK+OpCZy9Hr5eYnvOgAXoelq05cGXLjeHcw0Qj/YGqiOQgNziY= Received: (qmail 5271 invoked by alias); 23 Aug 2019 07:46:02 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 5261 invoked by uid 89); 23 Aug 2019 07:46:01 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-20.2 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.1 spammy= X-HELO: mail.rt-rk.com Received: from mx2.rt-rk.com (HELO mail.rt-rk.com) (89.216.37.149) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 23 Aug 2019 07:45:59 +0000 Received: from localhost (localhost [127.0.0.1]) by mail.rt-rk.com (Postfix) with ESMTP id 4A90F1A1FE5; Fri, 23 Aug 2019 09:45:55 +0200 (CEST) Received: from rtrkw790-lin.domain.local (rtrkw790-lin.domain.local [192.168.237.60]) by mail.rt-rk.com (Postfix) with ESMTPSA id 340AB1A1157; Fri, 23 Aug 2019 09:45:55 +0200 (CEST) From: Mihailo Stojanovic To: gcc-patches@gcc.gnu.org Cc: Jeff Law , Mihailo Stojanovic Subject: [PATCH v2] [MIPS] Add machine mode to get_fcsr pattern operand Date: Fri, 23 Aug 2019 09:45:54 +0200 Message-Id: <1566546354-14448-1-git-send-email-mihailo.stojanovic@rt-rk.com> Hi, Missing machine mode for the unspec_volatile operand of get_fcsr patterns causes an ICE in simplify_subreg on n64 ABI. This adds the missing machine modes and a new test. Tested on mips64el-mti-linux-gnu. Ok for trunk and possibly backport? Cheers, Mihailo gcc/ * config/mips/mips.md (mips_get_fcsr, *mips_get_fcsr): Use SI machine mode for unspec_volatile operand. * testsuite/gcc.target/mips/get-fcsr-3.c: New test. --- gcc/config/mips/mips.md | 4 ++-- gcc/testsuite/gcc.target/mips/get-fcsr-3.c | 9 +++++++++ 2 files changed, 11 insertions(+), 2 deletions(-) create mode 100644 gcc/testsuite/gcc.target/mips/get-fcsr-3.c diff --git a/gcc/config/mips/mips.md b/gcc/config/mips/mips.md index e17b1d5..4ad5c62 100644 --- a/gcc/config/mips/mips.md +++ b/gcc/config/mips/mips.md @@ -7588,7 +7588,7 @@ ;; __builtin_mips_get_fcsr: move the FCSR into operand 0. (define_expand "mips_get_fcsr" [(set (match_operand:SI 0 "register_operand") - (unspec_volatile [(const_int 0)] UNSPEC_GET_FCSR))] + (unspec_volatile:SI [(const_int 0)] UNSPEC_GET_FCSR))] "TARGET_HARD_FLOAT_ABI" { if (TARGET_MIPS16) @@ -7600,7 +7600,7 @@ (define_insn "*mips_get_fcsr" [(set (match_operand:SI 0 "register_operand" "=d") - (unspec_volatile [(const_int 0)] UNSPEC_GET_FCSR))] + (unspec_volatile:SI [(const_int 0)] UNSPEC_GET_FCSR))] "TARGET_HARD_FLOAT" "cfc1\t%0,$31") diff --git a/gcc/testsuite/gcc.target/mips/get-fcsr-3.c b/gcc/testsuite/gcc.target/mips/get-fcsr-3.c new file mode 100644 index 0000000..7bb97b6 --- /dev/null +++ b/gcc/testsuite/gcc.target/mips/get-fcsr-3.c @@ -0,0 +1,9 @@ +/* { dg-options "-mabi=64 -mhard-float" } */ + +NOMIPS16 unsigned int +foo (void) +{ + return __builtin_mips_get_fcsr () & 0x1; +} + +/* { dg-final { scan-assembler "cfc1" } } */