From patchwork Thu Aug 22 10:28:42 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Ramuthevar, Vadivel MuruganX" X-Patchwork-Id: 1151462 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.intel.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 46Dgky3JtWz9sP3 for ; Thu, 22 Aug 2019 20:29:43 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732081AbfHVK2s (ORCPT ); Thu, 22 Aug 2019 06:28:48 -0400 Received: from mga11.intel.com ([192.55.52.93]:40925 "EHLO mga11.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732080AbfHVK2s (ORCPT ); Thu, 22 Aug 2019 06:28:48 -0400 X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 22 Aug 2019 03:28:48 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.64,416,1559545200"; d="scan'208";a="330340900" Received: from sgsxdev004.isng.intel.com (HELO localhost) ([10.226.88.13]) by orsmga004.jf.intel.com with ESMTP; 22 Aug 2019 03:28:45 -0700 From: "Ramuthevar,Vadivel MuruganX" To: kishon@ti.com, robh@kernel.org Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, andriy.shevchenko@intel.com, cheol.yong.kim@intel.com, qi-ming.wu@intel.com, peter.harliman.liem@intel.com, Ramuthevar Vadivel Murugan Subject: [PATCH v4 1/2] dt-bindings: phy: intel-emmc-phy: Add YAML schema for LGM eMMC PHY Date: Thu, 22 Aug 2019 18:28:42 +0800 Message-Id: <20190822102843.47964-1-vadivel.muruganx.ramuthevar@linux.intel.com> X-Mailer: git-send-email 2.11.0 Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Ramuthevar Vadivel Murugan Add a YAML schema to use the host controller driver with the eMMC PHY on Intel's Lightning Mountain SoC. Signed-off-by: Ramuthevar Vadivel Murugan Reviewed-by: Rob Herring Reviewed-by: Andy Shevchenko --- changes in v4: - As per Rob's review: validate 5.2 and 5.3 - drop unrelated items. changes in v3: - resolve 'make dt_binding_check' warnings changes in v2: As per Rob Herring review comments, the following updates - change GPL-2.0 -> (GPL-2.0-only OR BSD-2-Clause) - filename is the compatible string plus .yaml - LGM: Lightning Mountain - update maintainer - add intel,syscon under property list - keep one example instead of two --- .../bindings/phy/intel,lgm-emmc-phy.yaml | 50 ++++++++++++++++++++++ 1 file changed, 50 insertions(+) create mode 100644 Documentation/devicetree/bindings/phy/intel,lgm-emmc-phy.yaml diff --git a/Documentation/devicetree/bindings/phy/intel,lgm-emmc-phy.yaml b/Documentation/devicetree/bindings/phy/intel,lgm-emmc-phy.yaml new file mode 100644 index 000000000000..16c27e817665 --- /dev/null +++ b/Documentation/devicetree/bindings/phy/intel,lgm-emmc-phy.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/phy/intel,lgm-emmc-phy.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Intel Lightning Mountain(LGM) eMMC PHY Device Tree Bindings + +maintainers: + - Ramuthevar Vadivel Murugan + +description: Binding for eMMC PHY + +properties: + compatible: + const: intel,lgm-emmc-phy + + intel,syscon: + description: phandle to the emmc through syscon + $ref: '/schemas/types.yaml#/definitions/phandle' + + clocks: + maxItems: 1 + + clock-names: + maxItems: 1 + + "#phy-cells": + const: 0 + +required: + - "#phy-cells" + - compatible + - intel,syscon + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + emmc_phy: emmc_phy { + compatible = "intel,lgm-emmc-phy"; + intel,syscon = <&sysconf>; + clocks = <&emmc>; + clock-names = "emmcclk"; + #phy-cells = <0>; + }; + +...