From patchwork Thu Aug 22 06:58:31 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Sam Shih X-Patchwork-Id: 1151317 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 46Db4v3zTYz9s7T for ; Thu, 22 Aug 2019 16:59:59 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1730790AbfHVG77 (ORCPT ); Thu, 22 Aug 2019 02:59:59 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:47405 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1728605AbfHVG77 (ORCPT ); Thu, 22 Aug 2019 02:59:59 -0400 X-UUID: 85a8d394eb26433cbdb0ee87e0639415-20190822 X-UUID: 85a8d394eb26433cbdb0ee87e0639415-20190822 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0707 with TLS) with ESMTP id 1958893970; Thu, 22 Aug 2019 14:59:52 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs05n1.mediatek.inc (172.21.101.15) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 22 Aug 2019 14:59:49 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Thu, 22 Aug 2019 14:59:45 +0800 From: Sam Shih To: Rob Herring , Mark Rutland , Matthias Brugger , Thierry Reding CC: Ryder Lee , John Crispin , , , , , "Sam Shih" Subject: [PATCH v5 01/13] pwm: mediatek: add a property "num-pwms" Date: Thu, 22 Aug 2019 14:58:31 +0800 Message-ID: <1566457123-20791-2-git-send-email-sam.shih@mediatek.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1566457123-20791-1-git-send-email-sam.shih@mediatek.com> References: <1566457123-20791-1-git-send-email-sam.shih@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: linux-pwm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org From: Ryder Lee This adds a property "num-pwms" to avoid having an endless list of compatibles with no differences for the same driver. Signed-off-by: Ryder Lee Signed-off-by: Sam Shih Reviewed-by: Uwe Kleine-König --- Used: https://patchwork.kernel.org/project/linux-mediatek/list/?series=68207 Changes since v5: Check num-pwms value is no more than MTK_CLK_MAX - 2 (MAIN + TOP) Changes since v4: Follow reviewer's comments: Move the changes of droping the check for of_device_get_match_data returning non-NULL to next patch Change-Id: I5a7aa05f5dec346612bd417f1c4530abc85f77a8 --- drivers/pwm/pwm-mediatek.c | 36 ++++++++++++++++++++++++++++-------- 1 file changed, 28 insertions(+), 8 deletions(-) diff --git a/drivers/pwm/pwm-mediatek.c b/drivers/pwm/pwm-mediatek.c index eb6674ce995f..e214f4f57107 100644 --- a/drivers/pwm/pwm-mediatek.c +++ b/drivers/pwm/pwm-mediatek.c @@ -55,7 +55,7 @@ static const char * const mtk_pwm_clk_name[MTK_CLK_MAX] = { }; struct mtk_pwm_platform_data { - unsigned int num_pwms; + unsigned int fallback_npwms; bool pwm45_fixup; bool has_clks; }; @@ -227,9 +227,10 @@ static const struct pwm_ops mtk_pwm_ops = { static int mtk_pwm_probe(struct platform_device *pdev) { const struct mtk_pwm_platform_data *data; + struct device_node *np = pdev->dev.of_node; struct mtk_pwm_chip *pc; struct resource *res; - unsigned int i; + unsigned int i, npwms; int ret; pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL); @@ -246,7 +247,26 @@ static int mtk_pwm_probe(struct platform_device *pdev) if (IS_ERR(pc->regs)) return PTR_ERR(pc->regs); - for (i = 0; i < data->num_pwms + 2 && pc->soc->has_clks; i++) { + ret = of_property_read_u32(np, "num-pwms", &npwms); + if (ret < 0) { + /* It's deprecated, we should specify num_pwms via DT now. */ + if (pc->soc->fallback_npwms) { + npwms = pc->soc->fallback_npwms; + dev_warn(&pdev->dev, "DT is outdated, please update it\n"); + } else { + dev_err(&pdev->dev, "failed to get number of PWMs\n"); + return ret; + } + } + + /* MAIN + TOP + NPWM < MTK_CLK_MAX */ + if ((npwms + 2) > MTK_CLK_MAX) { + dev_warn(&pdev->dev, "number of PWMs is larger than %d\n", + MTK_CLK_MAX - 2); + npwms = MTK_CLK_MAX - 2; + } + + for (i = 0; i < npwms + 2 && pc->soc->has_clks; i++) { pc->clks[i] = devm_clk_get(&pdev->dev, mtk_pwm_clk_name[i]); if (IS_ERR(pc->clks[i])) { dev_err(&pdev->dev, "clock: %s fail: %ld\n", @@ -260,7 +280,7 @@ static int mtk_pwm_probe(struct platform_device *pdev) pc->chip.dev = &pdev->dev; pc->chip.ops = &mtk_pwm_ops; pc->chip.base = -1; - pc->chip.npwm = data->num_pwms; + pc->chip.npwm = npwms; ret = pwmchip_add(&pc->chip); if (ret < 0) { @@ -279,25 +299,25 @@ static int mtk_pwm_remove(struct platform_device *pdev) } static const struct mtk_pwm_platform_data mt2712_pwm_data = { - .num_pwms = 8, + .fallback_npwms = 8, .pwm45_fixup = false, .has_clks = true, }; static const struct mtk_pwm_platform_data mt7622_pwm_data = { - .num_pwms = 6, + .fallback_npwms = 6, .pwm45_fixup = false, .has_clks = true, }; static const struct mtk_pwm_platform_data mt7623_pwm_data = { - .num_pwms = 5, + .fallback_npwms = 5, .pwm45_fixup = true, .has_clks = true, }; static const struct mtk_pwm_platform_data mt7628_pwm_data = { - .num_pwms = 4, + .fallback_npwms = 4, .pwm45_fixup = true, .has_clks = false, }; From patchwork Thu Aug 22 06:58:32 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Sam Shih X-Patchwork-Id: 1151318 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 46Db5R4Z6gz9sBp for ; Thu, 22 Aug 2019 17:00:27 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731918AbfHVHA0 (ORCPT ); Thu, 22 Aug 2019 03:00:26 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:27207 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1728605AbfHVHA0 (ORCPT ); Thu, 22 Aug 2019 03:00:26 -0400 X-UUID: b702d273852648b3ad3c60f7b35ead3e-20190822 X-UUID: b702d273852648b3ad3c60f7b35ead3e-20190822 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0707 with TLS) with ESMTP id 332468386; Thu, 22 Aug 2019 15:00:19 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs08n1.mediatek.inc (172.21.101.55) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 22 Aug 2019 15:00:17 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Thu, 22 Aug 2019 15:00:13 +0800 From: Sam Shih To: Rob Herring , Mark Rutland , Matthias Brugger , Thierry Reding CC: Ryder Lee , John Crispin , , , , , Sam Shih Subject: [PATCH v5 02/13] pwm: mediatek: droping the check for of_device_get_match_data Date: Thu, 22 Aug 2019 14:58:32 +0800 Message-ID: <1566457123-20791-3-git-send-email-sam.shih@mediatek.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1566457123-20791-1-git-send-email-sam.shih@mediatek.com> References: <1566457123-20791-1-git-send-email-sam.shih@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: linux-pwm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org This patch drop the check for of_device_get_match_data. Due to the only way call driver probe is compatible match. The .data pointer which point to the SoC specify data is directly set by driver, and it should not be NULL in our case. We can safety remove the check for of_device_get_match_data. Signed-off-by: Ryder Lee Signed-off-by: Sam Shih Acked-by: Uwe Kleine-König --- Used: https://patchwork.kernel.org/patch/11096905/ Changes since v4: Follow reviewer's comments: Move the changes of droping the check for of_device_get_match_data returning non-NULL to this patch Change-Id: Ibcba903d5b26159051adfc5ef2e601ee2f78729b --- drivers/pwm/pwm-mediatek.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/drivers/pwm/pwm-mediatek.c b/drivers/pwm/pwm-mediatek.c index e214f4f57107..ebd62629e3fe 100644 --- a/drivers/pwm/pwm-mediatek.c +++ b/drivers/pwm/pwm-mediatek.c @@ -226,7 +226,6 @@ static const struct pwm_ops mtk_pwm_ops = { static int mtk_pwm_probe(struct platform_device *pdev) { - const struct mtk_pwm_platform_data *data; struct device_node *np = pdev->dev.of_node; struct mtk_pwm_chip *pc; struct resource *res; @@ -237,10 +236,7 @@ static int mtk_pwm_probe(struct platform_device *pdev) if (!pc) return -ENOMEM; - data = of_device_get_match_data(&pdev->dev); - if (data == NULL) - return -EINVAL; - pc->soc = data; + pc->soc = of_device_get_match_data(&pdev->dev); res = platform_get_resource(pdev, IORESOURCE_MEM, 0); pc->regs = devm_ioremap_resource(&pdev->dev, res); From patchwork Thu Aug 22 06:58:33 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Shih X-Patchwork-Id: 1151319 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 46Db5n2zszz9s7T for ; Thu, 22 Aug 2019 17:00:45 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731349AbfHVHAp (ORCPT ); Thu, 22 Aug 2019 03:00:45 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:24426 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1728605AbfHVHAp (ORCPT ); Thu, 22 Aug 2019 03:00:45 -0400 X-UUID: 17eb2086c4e3493798a5996dce96b8e8-20190822 X-UUID: 17eb2086c4e3493798a5996dce96b8e8-20190822 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0707 with TLS) with ESMTP id 1696701101; Thu, 22 Aug 2019 15:00:40 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs05n1.mediatek.inc (172.21.101.15) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 22 Aug 2019 15:00:38 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Thu, 22 Aug 2019 15:00:34 +0800 From: Sam Shih To: Rob Herring , Mark Rutland , Matthias Brugger , Thierry Reding CC: Ryder Lee , John Crispin , , , , , Sam Shih Subject: [PATCH v5 03/13] pwm: mediatek: add a property "clock-frequency" Date: Thu, 22 Aug 2019 14:58:33 +0800 Message-ID: <1566457123-20791-4-git-send-email-sam.shih@mediatek.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1566457123-20791-1-git-send-email-sam.shih@mediatek.com> References: <1566457123-20791-1-git-send-email-sam.shih@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: linux-pwm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org This fix mt7628 pwm during configure from userspace. The SoC is legacy MIPS and has no complex clock tree. This patch add property clock-frequency to the SoC specific data and legacy MIPS SoC need to configure it in DT. This property is use for period calculation. We will improve this fix by droping has-clks attribute and using clock-frequency to do the same thing in a new patch. Signed-off-by: Ryder Lee Signed-off-by: Sam Shih --- Changes since v5: 1. Follow reviewer's comments Make the changes of fix mt7628 pwm as a single patch Changes since v4: - Follow reviewers's comments 1. use pc->soc->has_clks to check clocks exist or not. 2. Add error message when probe() unable to get clks - Fixes bug when SoC is old mips which has no complex clock tree. if clocks not exist, use the new property from DT to apply period caculation; otherwise, use clk_get_rate to get clock frequency and apply period caculation. Change-Id: Ibbe6d7a4f80b30f60725bcbeca1d02ce7834d28c --- drivers/pwm/pwm-mediatek.c | 39 ++++++++++++++++++++++++++++++-------- 1 file changed, 31 insertions(+), 8 deletions(-) diff --git a/drivers/pwm/pwm-mediatek.c b/drivers/pwm/pwm-mediatek.c index ebd62629e3fe..1f18bff4800c 100644 --- a/drivers/pwm/pwm-mediatek.c +++ b/drivers/pwm/pwm-mediatek.c @@ -65,11 +65,13 @@ struct mtk_pwm_platform_data { * @chip: linux PWM chip representation * @regs: base address of PWM chip * @clks: list of clocks + * @clk_freq: the fix clock frequency of legacy MIPS SoC */ struct mtk_pwm_chip { struct pwm_chip chip; void __iomem *regs; struct clk *clks[MTK_CLK_MAX]; + unsigned int clk_freq; const struct mtk_pwm_platform_data *soc; }; @@ -141,19 +143,27 @@ static int mtk_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, int duty_ns, int period_ns) { struct mtk_pwm_chip *pc = to_mtk_pwm_chip(chip); - struct clk *clk = pc->clks[MTK_CLK_PWM1 + pwm->hwpwm]; + unsigned int clk_freq; u32 clkdiv = 0, cnt_period, cnt_duty, reg_width = PWMDWIDTH, reg_thres = PWMTHRES; u64 resolution; int ret; + if (pc->soc->has_clks) { + struct clk *clk = pc->clks[MTK_CLK_PWM1 + pwm->hwpwm]; + + clk_freq = clk_get_rate(clk); + } else { + clk_freq = pc->clk_freq; + } + ret = mtk_pwm_clk_enable(chip, pwm); if (ret < 0) return ret; /* Using resolution in picosecond gets accuracy higher */ resolution = (u64)NSEC_PER_SEC * 1000; - do_div(resolution, clk_get_rate(clk)); + do_div(resolution, clk_freq); cnt_period = DIV_ROUND_CLOSEST_ULL((u64)period_ns * 1000, resolution); while (cnt_period > 8191) { @@ -262,13 +272,26 @@ static int mtk_pwm_probe(struct platform_device *pdev) npwms = MTK_CLK_MAX - 2; } - for (i = 0; i < npwms + 2 && pc->soc->has_clks; i++) { - pc->clks[i] = devm_clk_get(&pdev->dev, mtk_pwm_clk_name[i]); - if (IS_ERR(pc->clks[i])) { - dev_err(&pdev->dev, "clock: %s fail: %ld\n", - mtk_pwm_clk_name[i], PTR_ERR(pc->clks[i])); - return PTR_ERR(pc->clks[i]); + if (pc->soc->has_clks) { + for (i = 0; i < npwms + 2 ; i++) { + pc->clks[i] = devm_clk_get(&pdev->dev, + mtk_pwm_clk_name[i]); + if (IS_ERR(pc->clks[i])) { + dev_err(&pdev->dev, "clock: %s fail: %ld\n", + mtk_pwm_clk_name[i], + PTR_ERR(pc->clks[i])); + return PTR_ERR(pc->clks[i]); + } + } + } else { + unsigned int clk_freq; + + ret = of_property_read_u32(np, "clock-frequency", &clk_freq); + if (ret < 0) { + dev_err(&pdev->dev, "failed to get clock_frequency\n"); + return ret; } + pc->clk_freq = clk_freq; } platform_set_drvdata(pdev, pc); From patchwork Thu Aug 22 06:58:34 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Sam Shih X-Patchwork-Id: 1151320 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 46Db6s4XJWz9s7T for ; Thu, 22 Aug 2019 17:01:41 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731946AbfHVHBg (ORCPT ); Thu, 22 Aug 2019 03:01:36 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:6704 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1728605AbfHVHBg (ORCPT ); Thu, 22 Aug 2019 03:01:36 -0400 X-UUID: dae33867942e440da2d639619e7ce4f9-20190822 X-UUID: dae33867942e440da2d639619e7ce4f9-20190822 Received: from mtkmrs01.mediatek.inc [(172.21.131.159)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0707 with TLS) with ESMTP id 594319567; Thu, 22 Aug 2019 15:01:32 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs05n1.mediatek.inc (172.21.101.15) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 22 Aug 2019 15:01:30 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Thu, 22 Aug 2019 15:01:19 +0800 From: Sam Shih To: Rob Herring , Mark Rutland , Matthias Brugger , Thierry Reding CC: Ryder Lee , John Crispin , , , , , Sam Shih Subject: [PATCH v5 04/13] pwm: mediatek: allocate the clks array dynamically Date: Thu, 22 Aug 2019 14:58:34 +0800 Message-ID: <1566457123-20791-5-git-send-email-sam.shih@mediatek.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1566457123-20791-1-git-send-email-sam.shih@mediatek.com> References: <1566457123-20791-1-git-send-email-sam.shih@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: linux-pwm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org Instead of using fixed size of arrays, allocate the memory for them based on the information we get from the DT. Also remove the check for num_pwms, due to dynamically allocate pwm should not cause array index out of bound. Signed-off-by: Ryder Lee Signed-off-by: Sam Shih Reviewed-by: Uwe Kleine-König --- Changes since v5: - Follow reviewers's comments Make the changes of allocate the clks array dynamically as a single patch Changes since v4: - Follow reviewers's comments 1. use pc->soc->has_clks to check clocks exist or not. 2. Add error message when probe() unable to get clks - Fixes bug when SoC is old mips which has no complex clock tree. if clocks not exist, use the new property from DT to apply period caculation; otherwise, use clk_get_rate to get clock frequency and apply period caculation. Change-Id: I42edf07548fd604a5a4f689b45e945809057e3e3 --- drivers/pwm/pwm-mediatek.c | 96 ++++++++++++++++++-------------------- 1 file changed, 46 insertions(+), 50 deletions(-) diff --git a/drivers/pwm/pwm-mediatek.c b/drivers/pwm/pwm-mediatek.c index 1f18bff4800c..8d1fd8163f15 100644 --- a/drivers/pwm/pwm-mediatek.c +++ b/drivers/pwm/pwm-mediatek.c @@ -35,25 +35,6 @@ #define PWM_CLK_DIV_MAX 7 -enum { - MTK_CLK_MAIN = 0, - MTK_CLK_TOP, - MTK_CLK_PWM1, - MTK_CLK_PWM2, - MTK_CLK_PWM3, - MTK_CLK_PWM4, - MTK_CLK_PWM5, - MTK_CLK_PWM6, - MTK_CLK_PWM7, - MTK_CLK_PWM8, - MTK_CLK_MAX, -}; - -static const char * const mtk_pwm_clk_name[MTK_CLK_MAX] = { - "main", "top", "pwm1", "pwm2", "pwm3", "pwm4", "pwm5", "pwm6", "pwm7", - "pwm8" -}; - struct mtk_pwm_platform_data { unsigned int fallback_npwms; bool pwm45_fixup; @@ -64,13 +45,17 @@ struct mtk_pwm_platform_data { * struct mtk_pwm_chip - struct representing PWM chip * @chip: linux PWM chip representation * @regs: base address of PWM chip - * @clks: list of clocks + * @clk_top: the top clock generator + * @clk_main: the clock used by PWM core + * @clk_pwms: the clock used by each PWM channel * @clk_freq: the fix clock frequency of legacy MIPS SoC */ struct mtk_pwm_chip { struct pwm_chip chip; void __iomem *regs; - struct clk *clks[MTK_CLK_MAX]; + struct clk *clk_top; + struct clk *clk_main; + struct clk **clk_pwms; unsigned int clk_freq; const struct mtk_pwm_platform_data *soc; }; @@ -92,24 +77,24 @@ static int mtk_pwm_clk_enable(struct pwm_chip *chip, struct pwm_device *pwm) if (!pc->soc->has_clks) return 0; - ret = clk_prepare_enable(pc->clks[MTK_CLK_TOP]); + ret = clk_prepare_enable(pc->clk_top); if (ret < 0) return ret; - ret = clk_prepare_enable(pc->clks[MTK_CLK_MAIN]); + ret = clk_prepare_enable(pc->clk_main); if (ret < 0) goto disable_clk_top; - ret = clk_prepare_enable(pc->clks[MTK_CLK_PWM1 + pwm->hwpwm]); + ret = clk_prepare_enable(pc->clk_pwms[pwm->hwpwm]); if (ret < 0) goto disable_clk_main; return 0; disable_clk_main: - clk_disable_unprepare(pc->clks[MTK_CLK_MAIN]); + clk_disable_unprepare(pc->clk_main); disable_clk_top: - clk_disable_unprepare(pc->clks[MTK_CLK_TOP]); + clk_disable_unprepare(pc->clk_top); return ret; } @@ -121,9 +106,9 @@ static void mtk_pwm_clk_disable(struct pwm_chip *chip, struct pwm_device *pwm) if (!pc->soc->has_clks) return; - clk_disable_unprepare(pc->clks[MTK_CLK_PWM1 + pwm->hwpwm]); - clk_disable_unprepare(pc->clks[MTK_CLK_MAIN]); - clk_disable_unprepare(pc->clks[MTK_CLK_TOP]); + clk_disable_unprepare(pc->clk_pwms[pwm->hwpwm]); + clk_disable_unprepare(pc->clk_main); + clk_disable_unprepare(pc->clk_top); } static inline u32 mtk_pwm_readl(struct mtk_pwm_chip *chip, unsigned int num, @@ -149,13 +134,10 @@ static int mtk_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, u64 resolution; int ret; - if (pc->soc->has_clks) { - struct clk *clk = pc->clks[MTK_CLK_PWM1 + pwm->hwpwm]; - - clk_freq = clk_get_rate(clk); - } else { + if (pc->soc->has_clks) + clk_freq = clk_get_rate(pc->clk_pwms[pwm->hwpwm]); + else clk_freq = pc->clk_freq; - } ret = mtk_pwm_clk_enable(chip, pwm); if (ret < 0) @@ -239,7 +221,7 @@ static int mtk_pwm_probe(struct platform_device *pdev) struct device_node *np = pdev->dev.of_node; struct mtk_pwm_chip *pc; struct resource *res; - unsigned int i, npwms; + unsigned int npwms; int ret; pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL); @@ -265,22 +247,36 @@ static int mtk_pwm_probe(struct platform_device *pdev) } } - /* MAIN + TOP + NPWM < MTK_CLK_MAX */ - if ((npwms + 2) > MTK_CLK_MAX) { - dev_warn(&pdev->dev, "number of PWMs is larger than %d\n", - MTK_CLK_MAX - 2); - npwms = MTK_CLK_MAX - 2; - } - if (pc->soc->has_clks) { - for (i = 0; i < npwms + 2 ; i++) { - pc->clks[i] = devm_clk_get(&pdev->dev, - mtk_pwm_clk_name[i]); - if (IS_ERR(pc->clks[i])) { + int i; + + pc->clk_pwms = devm_kcalloc(&pdev->dev, npwms, + sizeof(*pc->clk_pwms), GFP_KERNEL); + if (!pc->clk_pwms) + return -ENOMEM; + + pc->clk_top = devm_clk_get(&pdev->dev, "top"); + if (IS_ERR(pc->clk_top)) { + dev_err(&pdev->dev, "clock: top fail: %ld\n", + PTR_ERR(pc->clk_top)); + return PTR_ERR(pc->clk_top); + } + + pc->clk_main = devm_clk_get(&pdev->dev, "main"); + if (IS_ERR(pc->clk_main)) { + dev_err(&pdev->dev, "clock: main fail: %ld\n", + PTR_ERR(pc->clk_main)); + return PTR_ERR(pc->clk_main); + } + for (i = 0; i < npwms; i++) { + char name[8]; + + snprintf(name, sizeof(name), "pwm%d", i + 1); + pc->clk_pwms[i] = devm_clk_get(&pdev->dev, name); + if (IS_ERR(pc->clk_pwms[i])) { dev_err(&pdev->dev, "clock: %s fail: %ld\n", - mtk_pwm_clk_name[i], - PTR_ERR(pc->clks[i])); - return PTR_ERR(pc->clks[i]); + name, PTR_ERR(pc->clk_pwms[i])); + return PTR_ERR(pc->clk_pwms[i]); } } } else { From patchwork Thu Aug 22 06:58:35 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Sam Shih X-Patchwork-Id: 1151321 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 46Db7M4vNjz9s7T for ; Thu, 22 Aug 2019 17:02:07 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728451AbfHVHCH (ORCPT ); Thu, 22 Aug 2019 03:02:07 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:17781 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1727685AbfHVHCH (ORCPT ); Thu, 22 Aug 2019 03:02:07 -0400 X-UUID: 7efa0560bb424c2da1dd174810d75da5-20190822 X-UUID: 7efa0560bb424c2da1dd174810d75da5-20190822 Received: from mtkmrs01.mediatek.inc [(172.21.131.159)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0707 with TLS) with ESMTP id 1652801761; Thu, 22 Aug 2019 15:01:59 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs08n2.mediatek.inc (172.21.101.56) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 22 Aug 2019 15:01:53 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Thu, 22 Aug 2019 15:01:54 +0800 From: Sam Shih To: Rob Herring , Mark Rutland , Matthias Brugger , Thierry Reding CC: Ryder Lee , John Crispin , , , , , Sam Shih Subject: [PATCH v5 05/13] pwm: mediatek: use pwm_mediatek as common prefix Date: Thu, 22 Aug 2019 14:58:35 +0800 Message-ID: <1566457123-20791-6-git-send-email-sam.shih@mediatek.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1566457123-20791-1-git-send-email-sam.shih@mediatek.com> References: <1566457123-20791-1-git-send-email-sam.shih@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: 68AAE1149948E07F912720E7E158FDCDAB942C683F5EC002C6AEB93CD982B6802000:8 X-MTK: N Sender: linux-pwm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org Use pwm_mediatek as common prefix to match the filename. No functional change intended. Signed-off-by: Ryder Lee Signed-off-by: Sam Shih Acked-by: Uwe Kleine-König --- Changes since v5: - Follow reviewers's comments The license stuff is a separate change Change-Id: I32f421d3eb26438e25edfd6e4f6da0e85c58526c --- drivers/pwm/pwm-mediatek.c | 112 +++++++++++++++++++------------------ 1 file changed, 57 insertions(+), 55 deletions(-) diff --git a/drivers/pwm/pwm-mediatek.c b/drivers/pwm/pwm-mediatek.c index 8d1fd8163f15..0938beb1a3cb 100644 --- a/drivers/pwm/pwm-mediatek.c +++ b/drivers/pwm/pwm-mediatek.c @@ -34,15 +34,14 @@ #define PWM45THRES_FIXUP 0x34 #define PWM_CLK_DIV_MAX 7 - -struct mtk_pwm_platform_data { +struct pwm_mediatek_of_data { unsigned int fallback_npwms; bool pwm45_fixup; bool has_clks; }; /** - * struct mtk_pwm_chip - struct representing PWM chip + * struct pwm_mediatek_chip - struct representing PWM chip * @chip: linux PWM chip representation * @regs: base address of PWM chip * @clk_top: the top clock generator @@ -50,28 +49,30 @@ struct mtk_pwm_platform_data { * @clk_pwms: the clock used by each PWM channel * @clk_freq: the fix clock frequency of legacy MIPS SoC */ -struct mtk_pwm_chip { +struct pwm_mediatek_chip { struct pwm_chip chip; void __iomem *regs; struct clk *clk_top; struct clk *clk_main; struct clk **clk_pwms; unsigned int clk_freq; - const struct mtk_pwm_platform_data *soc; + const struct pwm_mediatek_of_data *soc; }; -static const unsigned int mtk_pwm_reg_offset[] = { +static const unsigned int pwm_mediatek_reg_offset[] = { 0x0010, 0x0050, 0x0090, 0x00d0, 0x0110, 0x0150, 0x0190, 0x0220 }; -static inline struct mtk_pwm_chip *to_mtk_pwm_chip(struct pwm_chip *chip) +static inline struct pwm_mediatek_chip * +to_pwm_mediatek_chip(struct pwm_chip *chip) { - return container_of(chip, struct mtk_pwm_chip, chip); + return container_of(chip, struct pwm_mediatek_chip, chip); } -static int mtk_pwm_clk_enable(struct pwm_chip *chip, struct pwm_device *pwm) +static int pwm_mediatek_clk_enable(struct pwm_chip *chip, + struct pwm_device *pwm) { - struct mtk_pwm_chip *pc = to_mtk_pwm_chip(chip); + struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip); int ret; if (!pc->soc->has_clks) @@ -99,9 +100,10 @@ static int mtk_pwm_clk_enable(struct pwm_chip *chip, struct pwm_device *pwm) return ret; } -static void mtk_pwm_clk_disable(struct pwm_chip *chip, struct pwm_device *pwm) +static void pwm_mediatek_clk_disable(struct pwm_chip *chip, + struct pwm_device *pwm) { - struct mtk_pwm_chip *pc = to_mtk_pwm_chip(chip); + struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip); if (!pc->soc->has_clks) return; @@ -111,23 +113,23 @@ static void mtk_pwm_clk_disable(struct pwm_chip *chip, struct pwm_device *pwm) clk_disable_unprepare(pc->clk_top); } -static inline u32 mtk_pwm_readl(struct mtk_pwm_chip *chip, unsigned int num, - unsigned int offset) +static inline u32 pwm_mediatek_readl(struct pwm_mediatek_chip *chip, + unsigned int num, unsigned int offset) { - return readl(chip->regs + mtk_pwm_reg_offset[num] + offset); + return readl(chip->regs + pwm_mediatek_reg_offset[num] + offset); } -static inline void mtk_pwm_writel(struct mtk_pwm_chip *chip, - unsigned int num, unsigned int offset, - u32 value) +static inline void pwm_mediatek_writel(struct pwm_mediatek_chip *chip, + unsigned int num, unsigned int offset, + u32 value) { - writel(value, chip->regs + mtk_pwm_reg_offset[num] + offset); + writel(value, chip->regs + pwm_mediatek_reg_offset[num] + offset); } -static int mtk_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, - int duty_ns, int period_ns) +static int pwm_mediatek_config(struct pwm_chip *chip, struct pwm_device *pwm, + int duty_ns, int period_ns) { - struct mtk_pwm_chip *pc = to_mtk_pwm_chip(chip); + struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip); unsigned int clk_freq; u32 clkdiv = 0, cnt_period, cnt_duty, reg_width = PWMDWIDTH, reg_thres = PWMTHRES; @@ -139,7 +141,7 @@ static int mtk_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, else clk_freq = pc->clk_freq; - ret = mtk_pwm_clk_enable(chip, pwm); + ret = pwm_mediatek_clk_enable(chip, pwm); if (ret < 0) return ret; @@ -156,7 +158,7 @@ static int mtk_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, } if (clkdiv > PWM_CLK_DIV_MAX) { - mtk_pwm_clk_disable(chip, pwm); + pwm_mediatek_clk_disable(chip, pwm); dev_err(chip->dev, "period %d not supported\n", period_ns); return -EINVAL; } @@ -171,22 +173,22 @@ static int mtk_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, } cnt_duty = DIV_ROUND_CLOSEST_ULL((u64)duty_ns * 1000, resolution); - mtk_pwm_writel(pc, pwm->hwpwm, PWMCON, BIT(15) | clkdiv); - mtk_pwm_writel(pc, pwm->hwpwm, reg_width, cnt_period); - mtk_pwm_writel(pc, pwm->hwpwm, reg_thres, cnt_duty); + pwm_mediatek_writel(pc, pwm->hwpwm, PWMCON, BIT(15) | clkdiv); + pwm_mediatek_writel(pc, pwm->hwpwm, reg_width, cnt_period); + pwm_mediatek_writel(pc, pwm->hwpwm, reg_thres, cnt_duty); - mtk_pwm_clk_disable(chip, pwm); + pwm_mediatek_clk_disable(chip, pwm); return 0; } -static int mtk_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) +static int pwm_mediatek_enable(struct pwm_chip *chip, struct pwm_device *pwm) { - struct mtk_pwm_chip *pc = to_mtk_pwm_chip(chip); + struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip); u32 value; int ret; - ret = mtk_pwm_clk_enable(chip, pwm); + ret = pwm_mediatek_clk_enable(chip, pwm); if (ret < 0) return ret; @@ -197,29 +199,29 @@ static int mtk_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) return 0; } -static void mtk_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) +static void pwm_mediatek_disable(struct pwm_chip *chip, struct pwm_device *pwm) { - struct mtk_pwm_chip *pc = to_mtk_pwm_chip(chip); + struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip); u32 value; value = readl(pc->regs); value &= ~BIT(pwm->hwpwm); writel(value, pc->regs); - mtk_pwm_clk_disable(chip, pwm); + pwm_mediatek_clk_disable(chip, pwm); } -static const struct pwm_ops mtk_pwm_ops = { - .config = mtk_pwm_config, - .enable = mtk_pwm_enable, - .disable = mtk_pwm_disable, +static const struct pwm_ops pwm_mediatek_ops = { + .config = pwm_mediatek_config, + .enable = pwm_mediatek_enable, + .disable = pwm_mediatek_disable, .owner = THIS_MODULE, }; -static int mtk_pwm_probe(struct platform_device *pdev) +static int pwm_mediatek_probe(struct platform_device *pdev) { struct device_node *np = pdev->dev.of_node; - struct mtk_pwm_chip *pc; + struct pwm_mediatek_chip *pc; struct resource *res; unsigned int npwms; int ret; @@ -293,7 +295,7 @@ static int mtk_pwm_probe(struct platform_device *pdev) platform_set_drvdata(pdev, pc); pc->chip.dev = &pdev->dev; - pc->chip.ops = &mtk_pwm_ops; + pc->chip.ops = &pwm_mediatek_ops; pc->chip.base = -1; pc->chip.npwm = npwms; @@ -306,55 +308,55 @@ static int mtk_pwm_probe(struct platform_device *pdev) return 0; } -static int mtk_pwm_remove(struct platform_device *pdev) +static int pwm_mediatek_remove(struct platform_device *pdev) { - struct mtk_pwm_chip *pc = platform_get_drvdata(pdev); + struct pwm_mediatek_chip *pc = platform_get_drvdata(pdev); return pwmchip_remove(&pc->chip); } -static const struct mtk_pwm_platform_data mt2712_pwm_data = { +static const struct pwm_mediatek_of_data mt2712_pwm_data = { .fallback_npwms = 8, .pwm45_fixup = false, .has_clks = true, }; -static const struct mtk_pwm_platform_data mt7622_pwm_data = { +static const struct pwm_mediatek_of_data mt7622_pwm_data = { .fallback_npwms = 6, .pwm45_fixup = false, .has_clks = true, }; -static const struct mtk_pwm_platform_data mt7623_pwm_data = { +static const struct pwm_mediatek_of_data mt7623_pwm_data = { .fallback_npwms = 5, .pwm45_fixup = true, .has_clks = true, }; -static const struct mtk_pwm_platform_data mt7628_pwm_data = { +static const struct pwm_mediatek_of_data mt7628_pwm_data = { .fallback_npwms = 4, .pwm45_fixup = true, .has_clks = false, }; -static const struct of_device_id mtk_pwm_of_match[] = { +static const struct of_device_id pwm_mediatek_of_match[] = { { .compatible = "mediatek,mt2712-pwm", .data = &mt2712_pwm_data }, { .compatible = "mediatek,mt7622-pwm", .data = &mt7622_pwm_data }, { .compatible = "mediatek,mt7623-pwm", .data = &mt7623_pwm_data }, { .compatible = "mediatek,mt7628-pwm", .data = &mt7628_pwm_data }, { }, }; -MODULE_DEVICE_TABLE(of, mtk_pwm_of_match); +MODULE_DEVICE_TABLE(of, pwm_mediatek_of_match); -static struct platform_driver mtk_pwm_driver = { +static struct platform_driver pwm_mediatek_driver = { .driver = { - .name = "mtk-pwm", - .of_match_table = mtk_pwm_of_match, + .name = "pwm-mediatek", + .of_match_table = pwm_mediatek_of_match, }, - .probe = mtk_pwm_probe, - .remove = mtk_pwm_remove, + .probe = pwm_mediatek_probe, + .remove = pwm_mediatek_remove, }; -module_platform_driver(mtk_pwm_driver); +module_platform_driver(pwm_mediatek_driver); MODULE_AUTHOR("John Crispin "); MODULE_LICENSE("GPL"); From patchwork Thu Aug 22 06:58:36 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Sam Shih X-Patchwork-Id: 1151322 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 46Db7W5w4kz9s7T for ; Thu, 22 Aug 2019 17:02:15 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731963AbfHVHCP (ORCPT ); Thu, 22 Aug 2019 03:02:15 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:42198 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1727685AbfHVHCP (ORCPT ); Thu, 22 Aug 2019 03:02:15 -0400 X-UUID: 63670459fc034e53b9c0bd1c8069844c-20190822 X-UUID: 63670459fc034e53b9c0bd1c8069844c-20190822 Received: from mtkmrs01.mediatek.inc [(172.21.131.159)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0707 with TLS) with ESMTP id 1200625488; Thu, 22 Aug 2019 15:02:10 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs05n1.mediatek.inc (172.21.101.15) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 22 Aug 2019 15:02:09 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Thu, 22 Aug 2019 15:02:05 +0800 From: Sam Shih To: Rob Herring , Mark Rutland , Matthias Brugger , Thierry Reding CC: Ryder Lee , John Crispin , , , , , Sam Shih Subject: [PATCH v5 06/13] pwm: mediatek: update license and switch to SPDX tag Date: Thu, 22 Aug 2019 14:58:36 +0800 Message-ID: <1566457123-20791-7-git-send-email-sam.shih@mediatek.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1566457123-20791-1-git-send-email-sam.shih@mediatek.com> References: <1566457123-20791-1-git-send-email-sam.shih@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: linux-pwm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org Add SPDX identifiers to pwm-mediatek.c Update license to GNU General Public License v2.0 Signed-off-by: Ryder Lee Signed-off-by: Sam Shih Reviewed-by: Uwe Kleine-König --- Changes since v5: - Follow reviewers's comments The license stuff is a separate change Change-Id: I8f1ff6daa76727ed203db8dc608509f1cd3b1144 --- drivers/pwm/pwm-mediatek.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/drivers/pwm/pwm-mediatek.c b/drivers/pwm/pwm-mediatek.c index 0938beb1a3cb..290536a92a80 100644 --- a/drivers/pwm/pwm-mediatek.c +++ b/drivers/pwm/pwm-mediatek.c @@ -1,12 +1,10 @@ +// SPDX-License-Identifier: GPL-2.0 /* - * Mediatek Pulse Width Modulator driver + * MediaTek Pulse Width Modulator driver * * Copyright (C) 2015 John Crispin * Copyright (C) 2017 Zhi Mao * - * This file is licensed under the terms of the GNU General Public - * License version 2. This program is licensed "as is" without any - * warranty of any kind, whether express or implied. */ #include @@ -359,4 +357,4 @@ static struct platform_driver pwm_mediatek_driver = { module_platform_driver(pwm_mediatek_driver); MODULE_AUTHOR("John Crispin "); -MODULE_LICENSE("GPL"); +MODULE_LICENSE("GPL v2"); From patchwork Thu Aug 22 06:58:37 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Sam Shih X-Patchwork-Id: 1151326 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 46Db7l5kFbz9sNy for ; Thu, 22 Aug 2019 17:02:27 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731977AbfHVHCS (ORCPT ); Thu, 22 Aug 2019 03:02:18 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:21637 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1731962AbfHVHCS (ORCPT ); Thu, 22 Aug 2019 03:02:18 -0400 X-UUID: 71a229dcf7c34d7385c61a376933f824-20190822 X-UUID: 71a229dcf7c34d7385c61a376933f824-20190822 Received: from mtkmrs01.mediatek.inc [(172.21.131.159)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0707 with TLS) with ESMTP id 1808294151; Thu, 22 Aug 2019 15:02:13 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs05n2.mediatek.inc (172.21.101.140) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 22 Aug 2019 15:02:08 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Thu, 22 Aug 2019 15:02:07 +0800 From: Sam Shih To: Rob Herring , Mark Rutland , Matthias Brugger , Thierry Reding CC: Ryder Lee , John Crispin , , , , , Sam Shih Subject: [PATCH v5 07/13] dt-bindings: pwm: add a property "num-pwms" Date: Thu, 22 Aug 2019 14:58:37 +0800 Message-ID: <1566457123-20791-8-git-send-email-sam.shih@mediatek.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1566457123-20791-1-git-send-email-sam.shih@mediatek.com> References: <1566457123-20791-1-git-send-email-sam.shih@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: linux-pwm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org From: Ryder Lee This adds a property "num-pwms" in example so that we could specify the number of PWM channels via device tree. Signed-off-by: Ryder Lee Signed-off-by: Sam Shih Reviewed-by: Matthias Brugger Acked-by: Uwe Kleine-König --- Changes since v5: - Add an Acked-by tag - This file is original v4 patch 5/10 (https://patchwork.kernel.org/patch/11102577/) Change-Id: I429048afeffa96f3f14533910efe242f88776043 --- Documentation/devicetree/bindings/pwm/pwm-mediatek.txt | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/pwm/pwm-mediatek.txt b/Documentation/devicetree/bindings/pwm/pwm-mediatek.txt index 991728cb46cb..ea95b490a913 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-mediatek.txt +++ b/Documentation/devicetree/bindings/pwm/pwm-mediatek.txt @@ -14,12 +14,12 @@ Required properties: has no clocks - "top": the top clock generator - "main": clock used by the PWM core - - "pwm1-8": the eight per PWM clocks for mt2712 - - "pwm1-6": the six per PWM clocks for mt7622 - - "pwm1-5": the five per PWM clocks for mt7623 + - "pwm1-N": the PWM clocks for each channel + where N starting from 1 to the maximum number of PWM channels - pinctrl-names: Must contain a "default" entry. - pinctrl-0: One property must exist for each entry in pinctrl-names. See pinctrl/pinctrl-bindings.txt for details of the property values. + - num-pwms: the number of PWM channels. Example: pwm0: pwm@11006000 { @@ -37,4 +37,5 @@ Example: "pwm3", "pwm4", "pwm5"; pinctrl-names = "default"; pinctrl-0 = <&pwm0_pins>; + num-pwms = <5>; }; From patchwork Thu Aug 22 06:58:38 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Shih X-Patchwork-Id: 1151324 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 46Db7k0FbJz9sN4 for ; Thu, 22 Aug 2019 17:02:26 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731962AbfHVHCV (ORCPT ); Thu, 22 Aug 2019 03:02:21 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:15498 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1731985AbfHVHCV (ORCPT ); Thu, 22 Aug 2019 03:02:21 -0400 X-UUID: 19c9c25c3d5640d89a81cbb5ee09ac63-20190822 X-UUID: 19c9c25c3d5640d89a81cbb5ee09ac63-20190822 Received: from mtkcas06.mediatek.inc [(172.21.101.30)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0707 with TLS) with ESMTP id 522336204; Thu, 22 Aug 2019 15:02:15 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs08n2.mediatek.inc (172.21.101.56) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 22 Aug 2019 15:02:09 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Thu, 22 Aug 2019 15:02:10 +0800 From: Sam Shih To: Rob Herring , Mark Rutland , Matthias Brugger , Thierry Reding CC: Ryder Lee , John Crispin , , , , , Sam Shih Subject: [PATCH v5 08/13] dt-bindings: pwm: update bindings for MT7628 SoC Date: Thu, 22 Aug 2019 14:58:38 +0800 Message-ID: <1566457123-20791-9-git-send-email-sam.shih@mediatek.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1566457123-20791-1-git-send-email-sam.shih@mediatek.com> References: <1566457123-20791-1-git-send-email-sam.shih@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: 537761E6CC7A8FDED15EE22D21D068B748F25756D1A2E9A01BCF3458085770732000:8 X-MTK: N Sender: linux-pwm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org This updates bindings for MT7628 pwm controller. Signed-off-by: Sam Shih --- Documentation/devicetree/bindings/pwm/pwm-mediatek.txt | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/pwm/pwm-mediatek.txt b/Documentation/devicetree/bindings/pwm/pwm-mediatek.txt index ea95b490a913..93980e3da261 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-mediatek.txt +++ b/Documentation/devicetree/bindings/pwm/pwm-mediatek.txt @@ -21,6 +21,10 @@ Required properties: See pinctrl/pinctrl-bindings.txt for details of the property values. - num-pwms: the number of PWM channels. + + Optional properties: + - clock-frequency: fix clock frequency, this is only used in MT7628 SoC + for period calculation. This SoC has no complex clock tree. Example: pwm0: pwm@11006000 { compatible = "mediatek,mt7623-pwm"; From patchwork Thu Aug 22 06:58:39 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Shih X-Patchwork-Id: 1151327 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 46Db7w5LxLz9s7T for ; Thu, 22 Aug 2019 17:02:36 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729898AbfHVHCc (ORCPT ); Thu, 22 Aug 2019 03:02:32 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:7599 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1731985AbfHVHCc (ORCPT ); Thu, 22 Aug 2019 03:02:32 -0400 X-UUID: c212fbdb3c5a4204b1a52620139dcac3-20190822 X-UUID: c212fbdb3c5a4204b1a52620139dcac3-20190822 Received: from mtkcas08.mediatek.inc [(172.21.101.126)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0707 with TLS) with ESMTP id 452073596; Thu, 22 Aug 2019 15:02:28 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs08n2.mediatek.inc (172.21.101.56) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 22 Aug 2019 15:02:22 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Thu, 22 Aug 2019 15:02:23 +0800 From: Sam Shih To: Rob Herring , Mark Rutland , Matthias Brugger , Thierry Reding CC: Ryder Lee , John Crispin , , , , , Sam Shih Subject: [PATCH v5 09/13] arm64: dts: mt7622: add a property "num-pwms" for PWM Date: Thu, 22 Aug 2019 14:58:39 +0800 Message-ID: <1566457123-20791-10-git-send-email-sam.shih@mediatek.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1566457123-20791-1-git-send-email-sam.shih@mediatek.com> References: <1566457123-20791-1-git-send-email-sam.shih@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: 6BD5DC16D8B0361269CF5B8470E04D1506AF6155591386D93A8E813D15F8DFFA2000:8 X-MTK: N Sender: linux-pwm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org From: Ryder Lee This adds a property "num-pwms" for PWM controller. Signed-off-by: Ryder Lee Signed-off-by: Sam Shih --- arch/arm64/boot/dts/mediatek/mt7622.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/mediatek/mt7622.dtsi b/arch/arm64/boot/dts/mediatek/mt7622.dtsi index d1e13d340e26..9a043938881f 100644 --- a/arch/arm64/boot/dts/mediatek/mt7622.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt7622.dtsi @@ -439,6 +439,7 @@ <&pericfg CLK_PERI_PWM6_PD>; clock-names = "top", "main", "pwm1", "pwm2", "pwm3", "pwm4", "pwm5", "pwm6"; + num-pwms = <6>; status = "disabled"; }; From patchwork Thu Aug 22 06:58:40 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Shih X-Patchwork-Id: 1151328 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 46Db7x5cLqz9sN6 for ; Thu, 22 Aug 2019 17:02:37 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727310AbfHVHCg (ORCPT ); Thu, 22 Aug 2019 03:02:36 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:20035 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1731399AbfHVHCg (ORCPT ); Thu, 22 Aug 2019 03:02:36 -0400 X-UUID: ff48d69163be485d9db8bc6d4332d1cb-20190822 X-UUID: ff48d69163be485d9db8bc6d4332d1cb-20190822 Received: from mtkcas07.mediatek.inc [(172.21.101.84)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0707 with TLS) with ESMTP id 1497356549; Thu, 22 Aug 2019 15:02:31 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs05n2.mediatek.inc (172.21.101.140) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 22 Aug 2019 15:02:26 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Thu, 22 Aug 2019 15:02:26 +0800 From: Sam Shih To: Rob Herring , Mark Rutland , Matthias Brugger , Thierry Reding CC: Ryder Lee , John Crispin , , , , , Sam Shih Subject: [PATCH v5 10/13] arm: dts: mt7623: add a property "num-pwms" for PWM Date: Thu, 22 Aug 2019 14:58:40 +0800 Message-ID: <1566457123-20791-11-git-send-email-sam.shih@mediatek.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1566457123-20791-1-git-send-email-sam.shih@mediatek.com> References: <1566457123-20791-1-git-send-email-sam.shih@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: linux-pwm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org From: Ryder Lee This adds a property "num-pwms" for PWM controller. Signed-off-by: Ryder Lee Signed-off-by: Sam Shih --- arch/arm/boot/dts/mt7623.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/mt7623.dtsi b/arch/arm/boot/dts/mt7623.dtsi index a79f0b6c3429..208e0d19a575 100644 --- a/arch/arm/boot/dts/mt7623.dtsi +++ b/arch/arm/boot/dts/mt7623.dtsi @@ -452,6 +452,7 @@ <&pericfg CLK_PERI_PWM5>; clock-names = "top", "main", "pwm1", "pwm2", "pwm3", "pwm4", "pwm5"; + num-pwms = <5>; status = "disabled"; }; From patchwork Thu Aug 22 06:58:41 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Shih X-Patchwork-Id: 1151331 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 46Db8B0vy5z9sNk for ; Thu, 22 Aug 2019 17:02:50 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728953AbfHVHCn (ORCPT ); Thu, 22 Aug 2019 03:02:43 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:12955 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1732043AbfHVHCn (ORCPT ); Thu, 22 Aug 2019 03:02:43 -0400 X-UUID: 952f31b732034da6b369f1422a146201-20190822 X-UUID: 952f31b732034da6b369f1422a146201-20190822 Received: from mtkcas06.mediatek.inc [(172.21.101.30)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0707 with TLS) with ESMTP id 1319561969; Thu, 22 Aug 2019 15:02:36 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs08n2.mediatek.inc (172.21.101.56) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 22 Aug 2019 15:02:30 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Thu, 22 Aug 2019 15:02:30 +0800 From: Sam Shih To: Rob Herring , Mark Rutland , Matthias Brugger , Thierry Reding CC: Ryder Lee , John Crispin , , , , , Sam Shih Subject: [PATCH v5 11/13] dt-bindings: pwm: update bindings for MT7629 SoC Date: Thu, 22 Aug 2019 14:58:41 +0800 Message-ID: <1566457123-20791-12-git-send-email-sam.shih@mediatek.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1566457123-20791-1-git-send-email-sam.shih@mediatek.com> References: <1566457123-20791-1-git-send-email-sam.shih@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: 149F0F175159D459A58AAEBE9E64CEDE6AC7A11FCFB6C55AE556BE62B9660B7E2000:8 X-MTK: N Sender: linux-pwm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org From: Ryder Lee This updates bindings for MT7629 pwm controller. This patch is the same as https://patchwork.kernel.org/patch/10769381/ and it has a Reviewed-by tag in v1 Signed-off-by: Ryder Lee Signed-off-by: Sam Shih Reviewed-by: Matthias Brugger --- Changes since v1: - add a Reviewed-by tag Change-Id: Id9f0bd0b9aaa8748fcf6b0bfb2c6214d50b5ffa4 --- Documentation/devicetree/bindings/pwm/pwm-mediatek.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pwm/pwm-mediatek.txt b/Documentation/devicetree/bindings/pwm/pwm-mediatek.txt index 93980e3da261..e11cb0d93929 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-mediatek.txt +++ b/Documentation/devicetree/bindings/pwm/pwm-mediatek.txt @@ -6,6 +6,7 @@ Required properties: - "mediatek,mt7622-pwm": found on mt7622 SoC. - "mediatek,mt7623-pwm": found on mt7623 SoC. - "mediatek,mt7628-pwm": found on mt7628 SoC. + - "mediatek,mt7629-pwm", "mediatek,mt7622-pwm": found on mt7629 SoC. - reg: physical base address and length of the controller's registers. - #pwm-cells: must be 2. See pwm.txt in this directory for a description of the cell format. From patchwork Thu Aug 22 06:58:42 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Shih X-Patchwork-Id: 1151330 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 46Db872fLwz9sN4 for ; Thu, 22 Aug 2019 17:02:47 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732048AbfHVHCp (ORCPT ); Thu, 22 Aug 2019 03:02:45 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:21167 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1730048AbfHVHCo (ORCPT ); Thu, 22 Aug 2019 03:02:44 -0400 X-UUID: 8b5b994b19934c8fb6ec44cf27186598-20190822 X-UUID: 8b5b994b19934c8fb6ec44cf27186598-20190822 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0707 with TLS) with ESMTP id 1661304108; Thu, 22 Aug 2019 15:02:40 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs05n1.mediatek.inc (172.21.101.15) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 22 Aug 2019 15:02:39 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Thu, 22 Aug 2019 15:02:35 +0800 From: Sam Shih To: Rob Herring , Mark Rutland , Matthias Brugger , Thierry Reding CC: Ryder Lee , John Crispin , , , , , Sam Shih Subject: [PATCH v5 12/13] pwm: mediatek: remove a property "has-clock" Date: Thu, 22 Aug 2019 14:58:42 +0800 Message-ID: <1566457123-20791-13-git-send-email-sam.shih@mediatek.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1566457123-20791-1-git-send-email-sam.shih@mediatek.com> References: <1566457123-20791-1-git-send-email-sam.shih@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: linux-pwm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org Due to we added clock-frequency property to fix mt7628 pwm during configure from userspace. We can alos use this property to determine whether the complex clock tree exists in the SoC or not. So we can safety remove has-clock property in the driver specific data. Signed-off-by: Sam Shih --- drivers/pwm/pwm-mediatek.c | 26 ++++++++------------------ 1 file changed, 8 insertions(+), 18 deletions(-) diff --git a/drivers/pwm/pwm-mediatek.c b/drivers/pwm/pwm-mediatek.c index 290536a92a80..96f592595063 100644 --- a/drivers/pwm/pwm-mediatek.c +++ b/drivers/pwm/pwm-mediatek.c @@ -35,7 +35,6 @@ struct pwm_mediatek_of_data { unsigned int fallback_npwms; bool pwm45_fixup; - bool has_clks; }; /** @@ -73,7 +72,7 @@ static int pwm_mediatek_clk_enable(struct pwm_chip *chip, struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip); int ret; - if (!pc->soc->has_clks) + if (pc->clk_freq) return 0; ret = clk_prepare_enable(pc->clk_top); @@ -103,7 +102,7 @@ static void pwm_mediatek_clk_disable(struct pwm_chip *chip, { struct pwm_mediatek_chip *pc = to_pwm_mediatek_chip(chip); - if (!pc->soc->has_clks) + if (pc->clk_freq) return; clk_disable_unprepare(pc->clk_pwms[pwm->hwpwm]); @@ -134,10 +133,10 @@ static int pwm_mediatek_config(struct pwm_chip *chip, struct pwm_device *pwm, u64 resolution; int ret; - if (pc->soc->has_clks) - clk_freq = clk_get_rate(pc->clk_pwms[pwm->hwpwm]); - else + if (pc->clk_freq) clk_freq = pc->clk_freq; + else + clk_freq = clk_get_rate(pc->clk_pwms[pwm->hwpwm]); ret = pwm_mediatek_clk_enable(chip, pwm); if (ret < 0) @@ -222,6 +221,7 @@ static int pwm_mediatek_probe(struct platform_device *pdev) struct pwm_mediatek_chip *pc; struct resource *res; unsigned int npwms; + unsigned int clk_freq; int ret; pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL); @@ -247,7 +247,8 @@ static int pwm_mediatek_probe(struct platform_device *pdev) } } - if (pc->soc->has_clks) { + ret = of_property_read_u32(np, "clock-frequency", &clk_freq); + if (ret < 0) { int i; pc->clk_pwms = devm_kcalloc(&pdev->dev, npwms, @@ -280,13 +281,6 @@ static int pwm_mediatek_probe(struct platform_device *pdev) } } } else { - unsigned int clk_freq; - - ret = of_property_read_u32(np, "clock-frequency", &clk_freq); - if (ret < 0) { - dev_err(&pdev->dev, "failed to get clock_frequency\n"); - return ret; - } pc->clk_freq = clk_freq; } @@ -316,25 +310,21 @@ static int pwm_mediatek_remove(struct platform_device *pdev) static const struct pwm_mediatek_of_data mt2712_pwm_data = { .fallback_npwms = 8, .pwm45_fixup = false, - .has_clks = true, }; static const struct pwm_mediatek_of_data mt7622_pwm_data = { .fallback_npwms = 6, .pwm45_fixup = false, - .has_clks = true, }; static const struct pwm_mediatek_of_data mt7623_pwm_data = { .fallback_npwms = 5, .pwm45_fixup = true, - .has_clks = true, }; static const struct pwm_mediatek_of_data mt7628_pwm_data = { .fallback_npwms = 4, .pwm45_fixup = true, - .has_clks = false, }; static const struct of_device_id pwm_mediatek_of_match[] = { From patchwork Thu Aug 22 06:58:43 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Shih X-Patchwork-Id: 1151332 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pwm-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 46Db8C11btz9sNy for ; Thu, 22 Aug 2019 17:02:51 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729964AbfHVHCu (ORCPT ); Thu, 22 Aug 2019 03:02:50 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:45334 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1730048AbfHVHCu (ORCPT ); Thu, 22 Aug 2019 03:02:50 -0400 X-UUID: b4b4cd9a999845b89599d32499c65354-20190822 X-UUID: b4b4cd9a999845b89599d32499c65354-20190822 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0707 with TLS) with ESMTP id 114307298; Thu, 22 Aug 2019 15:02:44 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs08n1.mediatek.inc (172.21.101.55) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 22 Aug 2019 15:02:43 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Thu, 22 Aug 2019 15:02:39 +0800 From: Sam Shih To: Rob Herring , Mark Rutland , Matthias Brugger , Thierry Reding CC: Ryder Lee , John Crispin , , , , , Sam Shih Subject: [PATCH v5 13/13] arm: dts: mediatek: add mt7629 pwm support Date: Thu, 22 Aug 2019 14:58:43 +0800 Message-ID: <1566457123-20791-14-git-send-email-sam.shih@mediatek.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1566457123-20791-1-git-send-email-sam.shih@mediatek.com> References: <1566457123-20791-1-git-send-email-sam.shih@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: linux-pwm-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pwm@vger.kernel.org This adds pwm support for MT7629. Signed-off-by: Sam Shih --- arch/arm/boot/dts/mt7629.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm/boot/dts/mt7629.dtsi b/arch/arm/boot/dts/mt7629.dtsi index 9608bc2ccb3f..493be9a9453b 100644 --- a/arch/arm/boot/dts/mt7629.dtsi +++ b/arch/arm/boot/dts/mt7629.dtsi @@ -241,6 +241,22 @@ status = "disabled"; }; + pwm: pwm@11006000 { + compatible = "mediatek,mt7629-pwm", + "mediatek,mt7622-pwm"; + reg = <0 0x11006000 0 0x1000>; + interrupts = ; + clocks = <&topckgen CLK_TOP_PWM_SEL>, + <&pericfg CLK_PERI_PWM_PD>, + <&pericfg CLK_PERI_PWM1_PD>; + clock-names = "top", "main", "pwm1"; + assigned-clocks = <&topckgen CLK_TOP_PWM_SEL>; + assigned-clock-parents = + <&topckgen CLK_TOP_UNIVPLL2_D4>; + num-pwms = <1>; + status = "disabled"; + }; + i2c: i2c@11007000 { compatible = "mediatek,mt7629-i2c", "mediatek,mt2712-i2c";