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Wed, 21 Aug 2019 09:27:12 +0000 From: Dennis Zhang To: "gcc-patches@gcc.gnu.org" CC: nd , Richard Earnshaw , James Greenhalgh , Marcus Shawcroft Subject: [PATCH][AArch64] Add support for missing CPUs Date: Wed, 21 Aug 2019 09:27:12 +0000 Message-ID: <62179504-50d6-49b7-9917-ce3ab53338e7@arm.com> Authentication-Results-Original: spf=none (sender IP is ) smtp.mailfrom=Dennis.Zhang@arm.com; X-Microsoft-Antispam-Untrusted: BCL:0; PCL:0; RULEID:(2390118)(7020095)(4652040)(8989299)(4534185)(4627221)(201703031133081)(201702281549075)(8990200)(5600148)(711020)(4605104)(1401327)(4618075)(2017052603328)(49563074)(7193020); SRVR:VE1PR08MB4669; X-MS-Exchange-PUrlCount: 1 x-ms-exchange-transport-forked: True x-checkrecipientrouted: true x-ms-oob-tlc-oobclassifiers: OLM:7219;OLM:7219; X-Forefront-Antispam-Report-Untrusted: SFV:NSPM; SFS:(10009020)(4636009)(136003)(396003)(346002)(376002)(366004)(39860400002)(189003)(53754006)(54534003)(199004)(44832011)(4326008)(386003)(6506007)(2906002)(6436002)(81156014)(2351001)(25786009)(102836004)(2501003)(31686004)(486006)(256004)(54906003)(476003)(66476007)(5640700003)(305945005)(66066001)(5660300002)(6306002)(8936002)(7736002)(36756003)(6916009)(99936001)(66556008)(66446008)(6486002)(66616009)(64756008)(66946007)(26005)(52116002)(8676002)(6512007)(31696002)(71200400001)(2616005)(86362001)(14454004)(71190400001)(53936002)(186003)(3846002)(966005)(478600001)(316002)(99286004)(81166006)(4744005)(6116002); DIR:OUT; SFP:1101; SCL:1; SRVR:VE1PR08MB4669; H:VE1PR08MB5168.eurprd08.prod.outlook.com; FPR:; SPF:None; LANG:en; PTR:InfoNoRecords; MX:1; A:1; received-spf: None (protection.outlook.com: arm.com does not designate permitted sender hosts) X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam-Message-Info-Original: 5TKCEb7Bh1Yai3hiwhxExmlMJ6ppSxS1cYr3LDhvKvT1BBGzaHP4YfnVhJG/IBcAKylppsCG70tqR1hMYFXG3PyvQiRJ1Hbm+OfBSePI1PPYdZyRIPjmDspDilmarlrtvk4DB9kKPHYxbYpEMurVojv4OuY5Vu/8jJlMJr/BVT0wrLUcxWxIPFCePhHtahPUHeU/gHY13/xk4FAVbdH8QIGrb8ISgX3qiVeiCXkweO3i4fonVIW+7r1Y9cYeR2KuH3tip9iVfXESxk4jIQnak/aYH3LQDq23w0wo1yOgM67SB6xbm1CTrAxuIwa/0DNPgehfITa0yhqxeMFyrSG656L+YPxkTVyEZ+CvmzTl9NamAlITamWC4LoHQjodz7Ietyz8mcHqGXCVsY0Z8vsEd1pyYDGQGvgTACAsEErxQ6Y= MIME-Version: 1.0 Original-Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Dennis.Zhang@arm.com; X-MS-Exchange-Transport-CrossTenantHeadersStripped: AM5EUR03FT062.eop-EUR03.prod.protection.outlook.com X-MS-Office365-Filtering-Correlation-Id-Prvs: a6e4e532-5ed0-469c-ef26-08d72619bf25 Hi all, This patch adds '-mcpu' options for following CPUs: Cortex-A77, Cortex-A76AE, Cortex-A65, Cortex-A65AE, and Cortex-A34. Related specifications are as following: https://developer.arm.com/ip-products/processors/cortex-a Bootstraped/regtested for aarch64-none-linux-gnu. Please help to check if it's ready. Many thanks! Dennis gcc/ChangeLog: 2019-08-21 Dennis Zhang * config/aarch64/aarch64-cores.def (AARCH64_CORE): New entries for Cortex-A77, Cortex-A76AE, Cortex-A65, Cortex-A65AE, and Cortex-A34. * config/aarch64/aarch64-tune.md: Regenerated. * doc/invoke.texi: Document the new processors. diff --git a/gcc/config/aarch64/aarch64-cores.def b/gcc/config/aarch64/aarch64-cores.def index 82d91d62519..c0be109009f 100644 --- a/gcc/config/aarch64/aarch64-cores.def +++ b/gcc/config/aarch64/aarch64-cores.def @@ -46,6 +46,7 @@ /* ARMv8-A Architecture Processors. */ /* ARM ('A') cores. */ +AARCH64_CORE("cortex-a34", cortexa34, cortexa53, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC, cortexa35, 0x41, 0xd02, -1) AARCH64_CORE("cortex-a35", cortexa35, cortexa53, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC, cortexa35, 0x41, 0xd04, -1) AARCH64_CORE("cortex-a53", cortexa53, cortexa53, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC, cortexa53, 0x41, 0xd03, -1) AARCH64_CORE("cortex-a57", cortexa57, cortexa57, 8A, AARCH64_FL_FOR_ARCH8 | AARCH64_FL_CRC, cortexa57, 0x41, 0xd07, -1) @@ -100,6 +101,10 @@ AARCH64_CORE("thunderx2t99", thunderx2t99, thunderx2t99, 8_1A, AARCH64_FL_FOR AARCH64_CORE("cortex-a55", cortexa55, cortexa53, 8_2A, AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_F16 | AARCH64_FL_RCPC | AARCH64_FL_DOTPROD, cortexa53, 0x41, 0xd05, -1) AARCH64_CORE("cortex-a75", cortexa75, cortexa57, 8_2A, AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_F16 | AARCH64_FL_RCPC | AARCH64_FL_DOTPROD, cortexa73, 0x41, 0xd0a, -1) AARCH64_CORE("cortex-a76", cortexa76, cortexa57, 8_2A, AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_F16 | AARCH64_FL_RCPC | AARCH64_FL_DOTPROD, cortexa72, 0x41, 0xd0b, -1) +AARCH64_CORE("cortex-a76ae", cortexa76ae, cortexa57, 8_2A, AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_F16 | AARCH64_FL_RCPC | AARCH64_FL_DOTPROD | AARCH64_FL_SSBS, cortexa72, 0x41, 0xd0e, -1) +AARCH64_CORE("cortex-a77", cortexa77, cortexa57, 8_2A, AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_F16 | AARCH64_FL_RCPC | AARCH64_FL_DOTPROD | AARCH64_FL_SSBS, cortexa72, 0x41, 0xd0d, -1) +AARCH64_CORE("cortex-a65", cortexa65, cortexa57, 8_2A, AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_F16 | AARCH64_FL_RCPC | AARCH64_FL_DOTPROD | AARCH64_FL_SSBS, cortexa73, 0x41, 0xd06, -1) +AARCH64_CORE("cortex-a65ae", cortexa65ae, cortexa57, 8_2A, AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_F16 | AARCH64_FL_RCPC | AARCH64_FL_DOTPROD | AARCH64_FL_SSBS, cortexa73, 0x41, 0xd43, -1) AARCH64_CORE("ares", ares, cortexa57, 8_2A, AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_F16 | AARCH64_FL_RCPC | AARCH64_FL_DOTPROD | AARCH64_FL_PROFILE, neoversen1, 0x41, 0xd0c, -1) AARCH64_CORE("neoverse-n1", neoversen1, cortexa57, 8_2A, AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_F16 | AARCH64_FL_RCPC | AARCH64_FL_DOTPROD | AARCH64_FL_PROFILE, neoversen1, 0x41, 0xd0c, -1) AARCH64_CORE("neoverse-e1", neoversee1, cortexa53, 8_2A, AARCH64_FL_FOR_ARCH8_2 | AARCH64_FL_F16 | AARCH64_FL_RCPC | AARCH64_FL_DOTPROD | AARCH64_FL_SSBS, cortexa53, 0x41, 0xd4a, -1) diff --git a/gcc/config/aarch64/aarch64-tune.md b/gcc/config/aarch64/aarch64-tune.md index 2b1ec85ae31..a6a14b7fc77 100644 --- a/gcc/config/aarch64/aarch64-tune.md +++ b/gcc/config/aarch64/aarch64-tune.md @@ -1,5 +1,5 @@ ;; -*- buffer-read-only: t -*- ;; Generated automatically by gentune.sh from aarch64-cores.def (define_attr "tune" - "cortexa35,cortexa53,cortexa57,cortexa72,cortexa73,thunderx,thunderxt88p1,thunderxt88,octeontx,octeontxt81,octeontxt83,thunderxt81,thunderxt83,emag,xgene1,falkor,qdf24xx,exynosm1,phecda,thunderx2t99p1,vulcan,thunderx2t99,cortexa55,cortexa75,cortexa76,ares,neoversen1,neoversee1,tsv110,saphira,cortexa57cortexa53,cortexa72cortexa53,cortexa73cortexa35,cortexa73cortexa53,cortexa75cortexa55,cortexa76cortexa55" + "cortexa34,cortexa35,cortexa53,cortexa57,cortexa72,cortexa73,thunderx,thunderxt88p1,thunderxt88,octeontx,octeontxt81,octeontxt83,thunderxt81,thunderxt83,emag,xgene1,falkor,qdf24xx,exynosm1,phecda,thunderx2t99p1,vulcan,thunderx2t99,cortexa55,cortexa75,cortexa76,cortexa76ae,cortexa77,cortexa65,cortexa65ae,ares,neoversen1,neoversee1,tsv110,saphira,cortexa57cortexa53,cortexa72cortexa53,cortexa73cortexa35,cortexa73cortexa53,cortexa75cortexa55,cortexa76cortexa55" (const (symbol_ref "((enum attr_tune) aarch64_tune)"))) diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 29585cf15aa..3aa59b9a125 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -15809,7 +15809,9 @@ Specify the name of the target processor for which GCC should tune the performance of the code. Permissible values for this option are: @samp{generic}, @samp{cortex-a35}, @samp{cortex-a53}, @samp{cortex-a55}, @samp{cortex-a57}, @samp{cortex-a72}, @samp{cortex-a73}, @samp{cortex-a75}, -@samp{cortex-a76}, @samp{ares}, @samp{exynos-m1}, @samp{emag}, @samp{falkor}, +@samp{cortex-a76}, @samp{cortex-a76ae}, @samp{cortex-a77}, +@samp{cortex-a65}, @samp{cortex-a65ae}, @samp{cortex-a34}, +@samp{ares}, @samp{exynos-m1}, @samp{emag}, @samp{falkor}, @samp{neoverse-e1},@samp{neoverse-n1},@samp{qdf24xx}, @samp{saphira}, @samp{phecda}, @samp{xgene1}, @samp{vulcan}, @samp{octeontx}, @samp{octeontx81}, @samp{octeontx83}, @samp{thunderx}, @samp{thunderxt88},