From patchwork Tue Aug 20 18:00:31 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Michael Meissner X-Patchwork-Id: 1150318 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-507391-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=linux.ibm.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="aXOu4bXR"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 46CdrK5S7Dz9s4Y for ; Wed, 21 Aug 2019 04:00:47 +1000 (AEST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:subject:mime-version:content-type:message-id; q=dns; s= default; b=aiHOWN6Ms5T+vclQOwRU9cE1HuiBYXHFokflYVvjxz0TZmv9Co3TT oyZcycMahZvEotn/lmiqNRfR/CtHSqdG/idA8OjBxh7sulOGGpxGjjkdWA6Nsd6v 0CgaNNkzx90rtcp58V7HLY8MdOCEgX9Prba42oN4OhKyhXqF9JlLRo= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:date :from:to:subject:mime-version:content-type:message-id; s= default; bh=p6wXgvmhp1y8UBYYPhPGbl0S8e4=; b=aXOu4bXRYSCuLPju5//9 uv40mzz2s2fJUaCSa29fgFNd8FD6mOqHVwP/nWLBoh7f92rx86SjYK4cZWFFvchs JXz8sb9NWzJIVkPWpCsCZrscT+h7tGu68c1qcjT+Gd5MLrPxDjWwFxjj/qzIw2im zmG5YmJLDu0czMzpq+deHhg= Received: (qmail 87338 invoked by alias); 20 Aug 2019 18:00:41 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 87327 invoked by uid 89); 20 Aug 2019 18:00:40 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-10.6 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_LOW, SPF_PASS autolearn=ham version=3.3.1 spammy=king, King, v1timode, pre-altivec X-HELO: mx0a-001b2d01.pphosted.com Received: from mx0b-001b2d01.pphosted.com (HELO mx0a-001b2d01.pphosted.com) (148.163.158.5) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 20 Aug 2019 18:00:39 +0000 Received: from pps.filterd (m0098417.ppops.net [127.0.0.1]) by mx0a-001b2d01.pphosted.com (8.16.0.27/8.16.0.27) with SMTP id x7KHrIYG029689 for ; Tue, 20 Aug 2019 14:00:38 -0400 Received: from e32.co.us.ibm.com (e32.co.us.ibm.com [32.97.110.150]) by mx0a-001b2d01.pphosted.com with ESMTP id 2ugkj8640y-1 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=NOT) for ; Tue, 20 Aug 2019 14:00:37 -0400 Received: from localhost by e32.co.us.ibm.com with IBM ESMTP SMTP Gateway: Authorized Use Only! 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Violators will be prosecuted; (version=TLSv1/SSLv3 cipher=AES256-GCM-SHA384 bits=256/256) Tue, 20 Aug 2019 19:00:34 +0100 Received: from b03ledav002.gho.boulder.ibm.com (b03ledav002.gho.boulder.ibm.com [9.17.130.233]) by b03cxnp08026.gho.boulder.ibm.com (8.14.9/8.14.9/NCO v10.0) with ESMTP id x7KI0X4J55837042 (version=TLSv1/SSLv3 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Tue, 20 Aug 2019 18:00:33 GMT Received: from b03ledav002.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 8E847136059; Tue, 20 Aug 2019 18:00:33 +0000 (GMT) Received: from b03ledav002.gho.boulder.ibm.com (unknown [127.0.0.1]) by IMSVA (Postfix) with ESMTP id 2903113604F; Tue, 20 Aug 2019 18:00:33 +0000 (GMT) Received: from ibm-toto.the-meissners.org (unknown [9.32.77.177]) by b03ledav002.gho.boulder.ibm.com (Postfix) with ESMTPS; Tue, 20 Aug 2019 18:00:32 +0000 (GMT) Date: Tue, 20 Aug 2019 14:00:31 -0400 From: Michael Meissner To: gcc-patches@gcc.gnu.org, segher@kernel.crashing.org, dje.gcc@gmail.com, meissner@linux.ibm.com Subject: [PATCH], Fix V1TI in Altivec regs on old systems Mail-Followup-To: Michael Meissner , gcc-patches@gcc.gnu.org, segher@kernel.crashing.org, dje.gcc@gmail.com MIME-Version: 1.0 Content-Disposition: inline User-Agent: Mutt/1.5.21 (2010-09-15) x-cbid: 19082018-0004-0000-0000-0000153739A6 X-IBM-SpamModules-Scores: X-IBM-SpamModules-Versions: BY=3.00011624; HX=3.00000242; KW=3.00000007; PH=3.00000004; SC=3.00000287; SDB=6.01249620; UDB=6.00659690; IPR=6.01031169; MB=3.00028248; MTD=3.00000008; XFM=3.00000015; UTC=2019-08-20 18:00:35 X-IBM-AV-DETECTION: SAVI=unused REMOTE=unused XFE=unused x-cbparentid: 19082018-0005-0000-0000-00008CF3190B Message-Id: <20190820180031.GA23728@ibm-toto.the-meissners.org> This is a little corner case that I noticed in my rewrite of the RELOAD_REG stuff for the future machine. I was testing what registers were allowed in what registers for various systems (power5 through power9 for big endian on both 32 & 64-bit systems, and power8/power9 for little endian systems). I was using the debug flag -mdebug=reg which dumps out the reg_addr information (among other things). I noticed on power5 that the V1TImode mode is allowed in Altivec registers, even though power5 doesn't have Altivec registers. While it doesn't seem to effect anything (I couldn't create a test case that failed), it is a small nit that should be fixed. The test for TARGET_VADDUQM matches a test earlier in the function where VSX registers are checked. I have done a bootstrap on a little endian power8 and there were no regressions in the bootstrap or make check. I also verified via -mdebug=reg that V1TI mode is marked as being valid in the Altivec registers with -mcpu=power5. Can I check this into the trunk? 2019-08-20 Michael Meissner * config/rs6000/rs6000.c (rs6000_hard_regno_mode_ok_uncached): Don't allow V1TImode in Altivec registers on pre-altivec systems. Index: gcc/config/rs6000/rs6000.c =================================================================== --- gcc/config/rs6000/rs6000.c (revision 274635) +++ gcc/config/rs6000/rs6000.c (working copy) @@ -1874,7 +1874,7 @@ rs6000_hard_regno_mode_ok_uncached (int /* AltiVec only in AldyVec registers. */ if (ALTIVEC_REGNO_P (regno)) return (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode) - || mode == V1TImode); + || (TARGET_VADDUQM && mode == V1TImode)); /* We cannot put non-VSX TImode or PTImode anywhere except general register and it must be able to fit within the register set. */