From patchwork Sun Aug 18 13:42:54 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Beniamino Galvani X-Patchwork-Id: 1148962 X-Patchwork-Delegate: narmstrong@baylibre.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=lists.denx.de (client-ip=81.169.180.215; helo=lists.denx.de; envelope-from=u-boot-bounces@lists.denx.de; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="o+IWf8EM"; dkim-atps=neutral Received: from lists.denx.de (dione.denx.de [81.169.180.215]) by ozlabs.org (Postfix) with ESMTP id 46BYyk4yBTz9s7T for ; Mon, 19 Aug 2019 10:02:38 +1000 (AEST) Received: by lists.denx.de (Postfix, from userid 105) id 333BFC21E1A; Mon, 19 Aug 2019 00:02:06 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on lists.denx.de X-Spam-Level: X-Spam-Status: No, score=0.0 required=5.0 tests=FREEMAIL_FROM, RCVD_IN_MSPIKE_H2, T_DKIM_INVALID autolearn=unavailable autolearn_force=no version=3.4.0 Received: from lists.denx.de (localhost [IPv6:::1]) by lists.denx.de (Postfix) with ESMTP id E3571C21BE5; Mon, 19 Aug 2019 00:01:55 +0000 (UTC) Received: by lists.denx.de (Postfix, from userid 105) id 0CA67C21C50; Sun, 18 Aug 2019 13:43:35 +0000 (UTC) Received: from mail-wr1-f67.google.com (mail-wr1-f67.google.com [209.85.221.67]) by lists.denx.de (Postfix) with ESMTPS id 9C91DC21C3F for ; Sun, 18 Aug 2019 13:43:35 +0000 (UTC) Received: by mail-wr1-f67.google.com with SMTP id t16so5974592wra.6 for ; Sun, 18 Aug 2019 06:43:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=VWU0RLuC8O0Vy/Z6G0znkcTbiM+xIneUu42Lrw29kkA=; b=o+IWf8EMf1PqaCy9NRH9i0nZ+CFCKppDq6PvxzZa9YQyn6SdBoFz470/vAuhSXArSg ihuLlEIRoeBK6V36EDdNC6GQ3sNN9u7+XnnYW9WFihkEWjNy9BnJFr1DrNwdPX5LUckz WdVpvopF0bQe9r9GsvcJ/dq3gxTIAUuil48e3g+qoYn5fsQDLss1GsAzd31DU4XE0vj1 4KHw4fvlr78+zLVu7baTqOUzQD7L5kHrjqHbkpWUD7tArs4NkZlM6/H3ePQd4cXeOXu+ jy+0v/a5Dr//lvWX9P7PQFJTT6eBc54TzhFRPRBO9dbqWQvbEuygDtQK40lQCV/YK/c5 wG+w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=VWU0RLuC8O0Vy/Z6G0znkcTbiM+xIneUu42Lrw29kkA=; b=TAVOJa3CaJvpMNqO4cApStujI/kLXzRyL9yiGvglNS3dClNt7wmy0j0Qm6ddmR3MhR dkqIMSBY2fONVDGcB9yNSXXHGe1kGB19stpzDJtFSAPalhzDKonCbBcuM4Yv+nZ9MZyl BiABNLZzsSKsX5KuyHq6QeeRjVH9ecnXcnVa9FTS6wzNtN71aayskOFM11ElL+WxEmvj rpkH/byfjhn6zkThzgmV8ir5wkOF0FMgU2Vp60hDQ0QoBE9xDUSYokHdGfQSuHCZ+Lyx X+fTJ1ui1puYLzadigu0BiZ5h8b88yCWpjncecY1n7Cn2FdO0o9sunHeaSeIy7fYuFEX 6YUg== X-Gm-Message-State: APjAAAWOSPHUWWvABQhBE6kV5ieVkL+/Z8RnvFXt4Ucrz4hfFz1brlA3 9mLkrMY8EYQvHs0vI/DKPZV3lvnphps= X-Google-Smtp-Source: APXvYqyvqFDMaKR6QyWi2Sa4VDLR465a+bzLXX0e3/aBVt1Poe4suDdKjLAXJLbme6gZloYuR7YjJQ== X-Received: by 2002:a5d:480e:: with SMTP id l14mr21179147wrq.96.1566135814690; Sun, 18 Aug 2019 06:43:34 -0700 (PDT) Received: from sark.homenet.telecomitalia.it (host199-185-dynamic.45-213-r.retail.telecomitalia.it. [213.45.185.199]) by smtp.gmail.com with ESMTPSA id g7sm11844600wmg.8.2019.08.18.06.43.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 18 Aug 2019 06:43:34 -0700 (PDT) From: Beniamino Galvani To: u-boot@lists.denx.de, Neil Armstrong Date: Sun, 18 Aug 2019 15:42:54 +0200 Message-Id: <20190818134255.7135-2-b.galvani@gmail.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190818134255.7135-1-b.galvani@gmail.com> References: <20190818134255.7135-1-b.galvani@gmail.com> MIME-Version: 1.0 X-Mailman-Approved-At: Mon, 19 Aug 2019 00:01:53 +0000 Cc: u-boot-amlogic@groups.io, Tom Rini Subject: [U-Boot] [PATCH 1/2] phy: meson: add GXBB PHY driver X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" This adds support for the USB PHY found on Amlogic GXBB SoCs. Signed-off-by: Beniamino Galvani Reviewed-by: Neil Armstrong --- drivers/phy/Kconfig | 8 ++ drivers/phy/Makefile | 1 + drivers/phy/meson-gxbb-usb2.c | 235 ++++++++++++++++++++++++++++++++++ 3 files changed, 244 insertions(+) create mode 100644 drivers/phy/meson-gxbb-usb2.c diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig index 3942f035eb..2190f6f970 100644 --- a/drivers/phy/Kconfig +++ b/drivers/phy/Kconfig @@ -154,6 +154,14 @@ config PHY_STM32_USBPHYC between an HS USB OTG controller and an HS USB Host controller, selected by an USB switch. +config MESON_GXBB_USB_PHY + bool "Amlogic Meson GXBB USB PHY" + depends on PHY && ARCH_MESON && MESON_GXBB + imply REGMAP + help + This is the generic phy driver for the Amlogic Meson GXBB + USB2 PHY. + config MESON_GXL_USB_PHY bool "Amlogic Meson GXL USB PHYs" depends on PHY && ARCH_MESON && (MESON_GXL || MESON_GXM) diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile index 3157f1b7ee..dde3b0ecef 100644 --- a/drivers/phy/Makefile +++ b/drivers/phy/Makefile @@ -16,6 +16,7 @@ obj-$(CONFIG_STI_USB_PHY) += sti_usb_phy.o obj-$(CONFIG_PHY_RCAR_GEN2) += phy-rcar-gen2.o obj-$(CONFIG_PHY_RCAR_GEN3) += phy-rcar-gen3.o obj-$(CONFIG_PHY_STM32_USBPHYC) += phy-stm32-usbphyc.o +obj-$(CONFIG_MESON_GXBB_USB_PHY) += meson-gxbb-usb2.o obj-$(CONFIG_MESON_GXL_USB_PHY) += meson-gxl-usb2.o meson-gxl-usb3.o obj-$(CONFIG_MESON_G12A_USB_PHY) += meson-g12a-usb2.o meson-g12a-usb3-pcie.o obj-$(CONFIG_MSM8916_USB_PHY) += msm8916-usbh-phy.o diff --git a/drivers/phy/meson-gxbb-usb2.c b/drivers/phy/meson-gxbb-usb2.c new file mode 100644 index 0000000000..88c2ec69b2 --- /dev/null +++ b/drivers/phy/meson-gxbb-usb2.c @@ -0,0 +1,235 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Meson8, Meson8b and GXBB USB2 PHY driver + * + * Copyright (C) 2016 Martin Blumenstingl + * Copyright (C) 2018 BayLibre, SAS + * + * Author: Beniamino Galvani + */ + +#include +#include +#include +#include +#include +#include +#include + +#define REG_CONFIG 0x00 + #define REG_CONFIG_CLK_EN BIT(0) + #define REG_CONFIG_CLK_SEL_MASK GENMASK(3, 1) + #define REG_CONFIG_CLK_DIV_MASK GENMASK(10, 4) + #define REG_CONFIG_CLK_32k_ALTSEL BIT(15) + #define REG_CONFIG_TEST_TRIG BIT(31) + +#define REG_CTRL 0x04 + #define REG_CTRL_SOFT_PRST BIT(0) + #define REG_CTRL_SOFT_HRESET BIT(1) + #define REG_CTRL_SS_SCALEDOWN_MODE_MASK GENMASK(3, 2) + #define REG_CTRL_CLK_DET_RST BIT(4) + #define REG_CTRL_INTR_SEL BIT(5) + #define REG_CTRL_CLK_DETECTED BIT(8) + #define REG_CTRL_SOF_SENT_RCVD_TGL BIT(9) + #define REG_CTRL_SOF_TOGGLE_OUT BIT(10) + #define REG_CTRL_POWER_ON_RESET BIT(15) + #define REG_CTRL_SLEEPM BIT(16) + #define REG_CTRL_TX_BITSTUFF_ENN_H BIT(17) + #define REG_CTRL_TX_BITSTUFF_ENN BIT(18) + #define REG_CTRL_COMMON_ON BIT(19) + #define REG_CTRL_REF_CLK_SEL_MASK GENMASK(21, 20) + #define REG_CTRL_REF_CLK_SEL_SHIFT 20 + #define REG_CTRL_FSEL_MASK GENMASK(24, 22) + #define REG_CTRL_FSEL_SHIFT 22 + #define REG_CTRL_PORT_RESET BIT(25) + #define REG_CTRL_THREAD_ID_MASK GENMASK(31, 26) + +/* bits [31:26], [24:21] and [15:3] seem to be read-only */ +#define REG_ADP_BC 0x0c + #define REG_ADP_BC_VBUS_VLD_EXT_SEL BIT(0) + #define REG_ADP_BC_VBUS_VLD_EXT BIT(1) + #define REG_ADP_BC_OTG_DISABLE BIT(2) + #define REG_ADP_BC_ID_PULLUP BIT(3) + #define REG_ADP_BC_DRV_VBUS BIT(4) + #define REG_ADP_BC_ADP_PRB_EN BIT(5) + #define REG_ADP_BC_ADP_DISCHARGE BIT(6) + #define REG_ADP_BC_ADP_CHARGE BIT(7) + #define REG_ADP_BC_SESS_END BIT(8) + #define REG_ADP_BC_DEVICE_SESS_VLD BIT(9) + #define REG_ADP_BC_B_VALID BIT(10) + #define REG_ADP_BC_A_VALID BIT(11) + #define REG_ADP_BC_ID_DIG BIT(12) + #define REG_ADP_BC_VBUS_VALID BIT(13) + #define REG_ADP_BC_ADP_PROBE BIT(14) + #define REG_ADP_BC_ADP_SENSE BIT(15) + #define REG_ADP_BC_ACA_ENABLE BIT(16) + #define REG_ADP_BC_DCD_ENABLE BIT(17) + #define REG_ADP_BC_VDAT_DET_EN_B BIT(18) + #define REG_ADP_BC_VDAT_SRC_EN_B BIT(19) + #define REG_ADP_BC_CHARGE_SEL BIT(20) + #define REG_ADP_BC_CHARGE_DETECT BIT(21) + #define REG_ADP_BC_ACA_PIN_RANGE_C BIT(22) + #define REG_ADP_BC_ACA_PIN_RANGE_B BIT(23) + #define REG_ADP_BC_ACA_PIN_RANGE_A BIT(24) + #define REG_ADP_BC_ACA_PIN_GND BIT(25) + #define REG_ADP_BC_ACA_PIN_FLOAT BIT(26) + +#define RESET_COMPLETE_TIME 500 +#define ACA_ENABLE_COMPLETE_TIME 50 + +struct phy_meson_gxbb_usb2_priv { + struct regmap *regmap; + struct reset_ctl_bulk resets; +#if CONFIG_IS_ENABLED(DM_REGULATOR) + struct udevice *phy_supply; +#endif +}; + +static int phy_meson_gxbb_usb2_power_on(struct phy *phy) +{ + struct udevice *dev = phy->dev; + struct phy_meson_gxbb_usb2_priv *priv = dev_get_priv(dev); + uint val; + +#if CONFIG_IS_ENABLED(DM_REGULATOR) + if (priv->phy_supply) { + int ret = regulator_set_enable(priv->phy_supply, true); + + if (ret) + return ret; + } +#endif + + regmap_update_bits(priv->regmap, REG_CONFIG, + REG_CONFIG_CLK_32k_ALTSEL, + REG_CONFIG_CLK_32k_ALTSEL); + regmap_update_bits(priv->regmap, REG_CTRL, + REG_CTRL_REF_CLK_SEL_MASK, + 0x2 << REG_CTRL_REF_CLK_SEL_SHIFT); + regmap_update_bits(priv->regmap, REG_CTRL, + REG_CTRL_FSEL_MASK, + 0x5 << REG_CTRL_FSEL_SHIFT); + + /* reset the PHY */ + regmap_update_bits(priv->regmap, REG_CTRL, + REG_CTRL_POWER_ON_RESET, + REG_CTRL_POWER_ON_RESET); + udelay(RESET_COMPLETE_TIME); + regmap_update_bits(priv->regmap, REG_CTRL, + REG_CTRL_POWER_ON_RESET, + 0); + udelay(RESET_COMPLETE_TIME); + + regmap_update_bits(priv->regmap, REG_CTRL, + REG_CTRL_SOF_TOGGLE_OUT, + REG_CTRL_SOF_TOGGLE_OUT); + + /* Set host mode */ + regmap_update_bits(priv->regmap, REG_ADP_BC, + REG_ADP_BC_ACA_ENABLE, + REG_ADP_BC_ACA_ENABLE); + udelay(ACA_ENABLE_COMPLETE_TIME); + + regmap_read(priv->regmap, REG_ADP_BC, &val); + if (val & REG_ADP_BC_ACA_PIN_FLOAT) { + pr_err("Error powering on GXBB USB PHY\n"); + return -EINVAL; + } + + return 0; +} + +static int phy_meson_gxbb_usb2_power_off(struct phy *phy) +{ +#if CONFIG_IS_ENABLED(DM_REGULATOR) + struct udevice *dev = phy->dev; + struct phy_meson_gxbb_usb2_priv *priv = dev_get_priv(dev); + + if (priv->phy_supply) { + int ret = regulator_set_enable(priv->phy_supply, false); + + if (ret) + return ret; + } +#endif + + return 0; +} + +static struct phy_ops meson_gxbb_usb2_phy_ops = { + .power_on = phy_meson_gxbb_usb2_power_on, + .power_off = phy_meson_gxbb_usb2_power_off, +}; + +static int meson_gxbb_usb2_phy_probe(struct udevice *dev) +{ + struct phy_meson_gxbb_usb2_priv *priv = dev_get_priv(dev); + struct clk clk_usb_general, clk_usb; + int ret; + + ret = regmap_init_mem(dev_ofnode(dev), &priv->regmap); + if (ret) + return ret; + + ret = clk_get_by_name(dev, "usb_general", &clk_usb_general); + if (ret) + return ret; + + ret = clk_enable(&clk_usb_general); + if (ret && ret != -ENOSYS && ret != -ENOTSUPP) { + pr_err("Failed to enable PHY general clock\n"); + return ret; + } + + ret = clk_get_by_name(dev, "usb", &clk_usb); + if (ret) + return ret; + + ret = clk_enable(&clk_usb); + if (ret && ret != -ENOSYS && ret != -ENOTSUPP) { + pr_err("Failed to enable PHY clock\n"); + return ret; + } + +#if CONFIG_IS_ENABLED(DM_REGULATOR) + ret = device_get_supply_regulator(dev, "phy-supply", &priv->phy_supply); + if (ret && ret != -ENOENT) { + pr_err("Failed to get PHY regulator\n"); + return ret; + } +#endif + ret = reset_get_bulk(dev, &priv->resets); + if (!ret) { + ret = reset_deassert_bulk(&priv->resets); + if (ret) { + pr_err("Failed to deassert reset\n"); + return ret; + } + } + + return 0; +} + +static int meson_gxbb_usb2_phy_remove(struct udevice *dev) +{ + struct phy_meson_gxbb_usb2_priv *priv = dev_get_priv(dev); + + return reset_release_bulk(&priv->resets); +} + +static const struct udevice_id meson_gxbb_usb2_phy_ids[] = { + { .compatible = "amlogic,meson8-usb2-phy" }, + { .compatible = "amlogic,meson8b-usb2-phy" }, + { .compatible = "amlogic,meson-gxbb-usb2-phy" }, + { } +}; + +U_BOOT_DRIVER(meson_gxbb_usb2_phy) = { + .name = "meson_gxbb_usb2_phy", + .id = UCLASS_PHY, + .of_match = meson_gxbb_usb2_phy_ids, + .probe = meson_gxbb_usb2_phy_probe, + .remove = meson_gxbb_usb2_phy_remove, + .ops = &meson_gxbb_usb2_phy_ops, + .priv_auto_alloc_size = sizeof(struct phy_meson_gxbb_usb2_priv), +}; From patchwork Sun Aug 18 13:42:55 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Beniamino Galvani X-Patchwork-Id: 1148963 X-Patchwork-Delegate: narmstrong@baylibre.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; 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[213.45.185.199]) by smtp.gmail.com with ESMTPSA id g7sm11844600wmg.8.2019.08.18.06.43.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 18 Aug 2019 06:43:35 -0700 (PDT) From: Beniamino Galvani To: u-boot@lists.denx.de, Neil Armstrong Date: Sun, 18 Aug 2019 15:42:55 +0200 Message-Id: <20190818134255.7135-3-b.galvani@gmail.com> X-Mailer: git-send-email 2.21.0 In-Reply-To: <20190818134255.7135-1-b.galvani@gmail.com> References: <20190818134255.7135-1-b.galvani@gmail.com> MIME-Version: 1.0 X-Mailman-Approved-At: Mon, 19 Aug 2019 00:01:53 +0000 Cc: u-boot-amlogic@groups.io, Tom Rini Subject: [U-Boot] [PATCH 2/2] odroid-c2: enable USB host controller X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.18 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" Enable the second USB controller, which is connected to a hub with 4 ports. The first controller is for the OTG port and is currently not supported. Signed-off-by: Beniamino Galvani --- arch/arm/dts/meson-gxbb-odroidc2-u-boot.dtsi | 8 ++++++++ configs/odroid-c2_defconfig | 7 +++++++ include/configs/meson64.h | 5 +++++ 3 files changed, 20 insertions(+) diff --git a/arch/arm/dts/meson-gxbb-odroidc2-u-boot.dtsi b/arch/arm/dts/meson-gxbb-odroidc2-u-boot.dtsi index c35158d7e9..484b40504d 100644 --- a/arch/arm/dts/meson-gxbb-odroidc2-u-boot.dtsi +++ b/arch/arm/dts/meson-gxbb-odroidc2-u-boot.dtsi @@ -5,3 +5,11 @@ */ #include "meson-gx-u-boot.dtsi" + +&usb0 { + status = "disabled"; +}; + +&usb1 { + hnp-srp-disable; +}; diff --git a/configs/odroid-c2_defconfig b/configs/odroid-c2_defconfig index 8849058d33..366ea125af 100644 --- a/configs/odroid-c2_defconfig +++ b/configs/odroid-c2_defconfig @@ -16,6 +16,7 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y # CONFIG_CMD_LOADS is not set CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y # CONFIG_CMD_SETEXPR is not set CONFIG_CMD_REGULATOR=y CONFIG_OF_CONTROL=y @@ -29,13 +30,19 @@ CONFIG_MMC_MESON_GX=y CONFIG_PHY_REALTEK=y CONFIG_DM_ETH=y CONFIG_ETH_DESIGNWARE=y +CONFIG_PHY=y +CONFIG_MESON_GXBB_USB_PHY=y CONFIG_PINCTRL=y CONFIG_PINCTRL_MESON_GXBB=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y CONFIG_DM_RESET=y CONFIG_DEBUG_UART_MESON=y CONFIG_DEBUG_UART_ANNOUNCE=y CONFIG_DEBUG_UART_SKIP_INIT=y CONFIG_MESON_SERIAL=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_DWC2=y CONFIG_OF_LIBFDT_OVERLAY=y diff --git a/include/configs/meson64.h b/include/configs/meson64.h index f8d3eee292..483a8f567c 100644 --- a/include/configs/meson64.h +++ b/include/configs/meson64.h @@ -16,6 +16,11 @@ #define GICC_BASE 0xc4302000 #endif +/* USB */ +#if defined(CONFIG_MESON_GXBB) +#define CONFIG_DWC2_UTMI_WIDTH 16 +#endif + /* For splashscreen */ #ifdef CONFIG_DM_VIDEO #define CONFIG_VIDEO_BMP_RLE8