From patchwork Thu Aug 15 08:40:35 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Sandiford X-Patchwork-Id: 1147477 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-507020-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="fMlA8+wb"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 468KfR0sc6z9sN6 for ; Thu, 15 Aug 2019 18:40:46 +1000 (AEST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:mime-version:content-type; q=dns; s=default; b=VOIMAe0ZbqB1kxyg6VaZBdXrabQQoANj5wtgxyihzeyrObRvlk 4yfVAQg1lCpNqcFbukKgBv5srGQAADKlYYU1JBlI2DYxhDz9U8WY4xXEfRsxrNJ5 nItr7kz3PBx1zPfX3PnA+oeOdhdtCU+maLt3UZPsIZYISRsn5LgMnwpBo= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:mime-version:content-type; s= default; bh=KHM3unT/KXo/ygCs20Oz/x/vqDA=; b=fMlA8+wb14n2BDW2jHfi tv0Bux8lqYH0b/APqtOm2xgGHZTqZSX8BaLZ63n8yrXWJpC+ziH010sFxND4UnPM qkFMsVtwuNL5x5fY+kbPdKOCkdE+qZs7LDZ8wqtAa/Vwmf0CTKi2VZcQinwrMeRf IsmxqRnyKlwOOJN5EDOBWmo= Received: (qmail 94063 invoked by alias); 15 Aug 2019 08:40:40 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 94014 invoked by uid 89); 15 Aug 2019 08:40:40 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-8.5 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_2, GIT_PATCH_3, KAM_ASCII_DIVIDERS, SPF_PASS autolearn=ham version=3.3.1 spammy= X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.110.172) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 15 Aug 2019 08:40:38 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 51F3D28; Thu, 15 Aug 2019 01:40:37 -0700 (PDT) Received: from localhost (e121540-lin.manchester.arm.com [10.32.99.62]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id D129D3F718; Thu, 15 Aug 2019 01:40:36 -0700 (PDT) From: Richard Sandiford To: gcc-patches@gcc.gnu.org Mail-Followup-To: gcc-patches@gcc.gnu.org, Kugan Vivekanandarajah , richard.sandiford@arm.com Cc: Kugan Vivekanandarajah Subject: [committed][AArch64] Add more SVE FMLA and FMAD /z alternatives Date: Thu, 15 Aug 2019 09:40:35 +0100 Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/26.1 (gnu/linux) MIME-Version: 1.0 X-IsSubscribed: yes This patch makes the floating-point conditional FMA patterns provide the same /z alternatives as the integer patterns added by a previous patch. We can handle cases in which individual inputs are allocated to the same register as the output, so we don't need to force all registers to be different. Tested on aarch64-linux-gnu (with and without SVE) and aarch64_be-elf. Applied as r274516. Richard 2019-08-15 Richard Sandiford Kugan Vivekanandarajah gcc/ * config/aarch64/aarch64-sve.md (*cond__any): Add /z alternatives in which one of the inputs is in the same register as the output. gcc/testsuite/ * gcc.target/aarch64/sve/cond_mla_5.c: Allow FMAD as well as FMLA and FMSB as well as FMLS. Index: gcc/config/aarch64/aarch64-sve.md =================================================================== --- gcc/config/aarch64/aarch64-sve.md 2019-08-15 09:37:10.528856480 +0100 +++ gcc/config/aarch64/aarch64-sve.md 2019-08-15 09:38:53.656095524 +0100 @@ -3844,17 +3844,17 @@ (define_insn_and_rewrite "*cond_< ;; Predicated floating-point ternary operations, merging with an ;; independent value. (define_insn_and_rewrite "*cond__any" - [(set (match_operand:SVE_F 0 "register_operand" "=&w, &w, ?&w") + [(set (match_operand:SVE_F 0 "register_operand" "=&w, &w, &w, &w, &w, ?&w") (unspec:SVE_F - [(match_operand: 1 "register_operand" "Upl, Upl, Upl") + [(match_operand: 1 "register_operand" "Upl, Upl, Upl, Upl, Upl, Upl") (unspec:SVE_F [(match_operand 6) (match_operand:SI 7 "aarch64_sve_gp_strictness") - (match_operand:SVE_F 2 "register_operand" "w, w, w") - (match_operand:SVE_F 3 "register_operand" "w, w, w") - (match_operand:SVE_F 4 "register_operand" "w, w, w")] + (match_operand:SVE_F 2 "register_operand" "w, w, 0, w, w, w") + (match_operand:SVE_F 3 "register_operand" "w, w, w, 0, w, w") + (match_operand:SVE_F 4 "register_operand" "w, 0, w, w, w, w")] SVE_COND_FP_TERNARY) - (match_operand:SVE_F 5 "aarch64_simd_reg_or_zero" "Dz, 0, w")] + (match_operand:SVE_F 5 "aarch64_simd_reg_or_zero" "Dz, Dz, Dz, Dz, 0, w")] UNSPEC_SEL))] "TARGET_SVE && !rtx_equal_p (operands[2], operands[5]) @@ -3863,6 +3863,9 @@ (define_insn_and_rewrite "*cond_< && aarch64_sve_pred_dominates_p (&operands[6], operands[1])" "@ movprfx\t%0., %1/z, %4.\;\t%0., %1/m, %2., %3. + movprfx\t%0., %1/z, %0.\;\t%0., %1/m, %2., %3. + movprfx\t%0., %1/z, %0.\;\t%0., %1/m, %3., %4. + movprfx\t%0., %1/z, %0.\;\t%0., %1/m, %2., %4. movprfx\t%0., %1/m, %4.\;\t%0., %1/m, %2., %3. #" "&& 1" Index: gcc/testsuite/gcc.target/aarch64/sve/cond_mla_5.c =================================================================== --- gcc/testsuite/gcc.target/aarch64/sve/cond_mla_5.c 2019-08-15 09:22:03.047558159 +0100 +++ gcc/testsuite/gcc.target/aarch64/sve/cond_mla_5.c 2019-08-15 09:38:53.656095524 +0100 @@ -39,13 +39,13 @@ TEST_ALL (DEF_LOOP) /* { dg-final { scan-assembler-times {\t(?:mls|msb)\tz[0-9]+\.s, p[0-7]/m,} 1 } } */ /* { dg-final { scan-assembler-times {\t(?:mls|msb)\tz[0-9]+\.d, p[0-7]/m,} 1 } } */ -/* { dg-final { scan-assembler-times {\tfmla\tz[0-9]+\.h, p[0-7]/m,} 1 } } */ -/* { dg-final { scan-assembler-times {\tfmla\tz[0-9]+\.s, p[0-7]/m,} 1 } } */ -/* { dg-final { scan-assembler-times {\tfmla\tz[0-9]+\.d, p[0-7]/m,} 1 } } */ +/* { dg-final { scan-assembler-times {\t(?:fmla|fmad)\tz[0-9]+\.h, p[0-7]/m,} 1 } } */ +/* { dg-final { scan-assembler-times {\t(?:fmla|fmad)\tz[0-9]+\.s, p[0-7]/m,} 1 } } */ +/* { dg-final { scan-assembler-times {\t(?:fmla|fmad)\tz[0-9]+\.d, p[0-7]/m,} 1 } } */ -/* { dg-final { scan-assembler-times {\tfmls\tz[0-9]+\.h, p[0-7]/m,} 1 } } */ -/* { dg-final { scan-assembler-times {\tfmls\tz[0-9]+\.s, p[0-7]/m,} 1 } } */ -/* { dg-final { scan-assembler-times {\tfmls\tz[0-9]+\.d, p[0-7]/m,} 1 } } */ +/* { dg-final { scan-assembler-times {\t(?:fmls|fmsb)\tz[0-9]+\.h, p[0-7]/m,} 1 } } */ +/* { dg-final { scan-assembler-times {\t(?:fmls|fmsb)\tz[0-9]+\.s, p[0-7]/m,} 1 } } */ +/* { dg-final { scan-assembler-times {\t(?:fmls|fmsb)\tz[0-9]+\.d, p[0-7]/m,} 1 } } */ /* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.b, p[0-7]/z,} 2 } } */ /* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+\.h, p[0-7]/z,} 4 } } */