From patchwork Wed Aug 14 10:57:48 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Sandiford X-Patchwork-Id: 1146962 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-506922-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="cnzlX7wy"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 467mlM2P67z9s7T for ; Wed, 14 Aug 2019 20:58:05 +1000 (AEST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:mime-version:content-type; q=dns; s= default; b=ZzAfIe+XmMrBHIMWjZy5mmjgO0z5zLOdO7/WLsUJ3ILhMRksLh02E hG9MeEwf/DDSWI7qdeNHpf2s00RULnARY+b4INXTH9tOYn399bxWNycB+nFEIdQL a3OHaUlBGUlJdBAahuoYEjgQoZUCwegVzn7O2D+tc7+UYcTsXcngc0= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:mime-version:content-type; s= default; bh=HGrkMqb26jh55axwl9q3bfp/APU=; b=cnzlX7wyDwEHVgsae38+ /ki9L3WWGEqUJ7/nV6y/lFQksmXOL5LnUoZYjvUIsvSbPmIMV9bkawsrCT8eVAd0 b8JRRRTk89AMe7EX46dBhvDklUT0BZKZX0WW7wg+wXF1EDI6nIaDdqnXKtWVnWh4 A3+nqNZiEgo3EpURj1zljYI= Received: (qmail 130512 invoked by alias); 14 Aug 2019 10:57:57 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 130504 invoked by uid 89); 14 Aug 2019 10:57:56 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-8.4 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_2, GIT_PATCH_3, KAM_ASCII_DIVIDERS autolearn=ham version=3.3.1 spammy= X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.110.172) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 14 Aug 2019 10:57:51 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 5685328 for ; Wed, 14 Aug 2019 03:57:50 -0700 (PDT) Received: from localhost (e121540-lin.manchester.arm.com [10.32.99.62]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id D697E3F706 for ; Wed, 14 Aug 2019 03:57:49 -0700 (PDT) From: Richard Sandiford To: gcc-patches@gcc.gnu.org Mail-Followup-To: gcc-patches@gcc.gnu.org, richard.sandiford@arm.com Subject: [committed][AArch64] Add SVE conditional conversion patterns Date: Wed, 14 Aug 2019 11:57:48 +0100 Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/26.1 (gnu/linux) MIME-Version: 1.0 X-IsSubscribed: yes This patch adds patterns to match conditional conversions between integers and like-sized floats. The patterns are actually more general than that, but the other combinations can only be tested via the ACLE. Tested on aarch64-linux-gnu (with and without SVE) and aarch64_be-elf. Applied as r274478. Richard 2019-08-14 Richard Sandiford gcc/ * config/aarch64/aarch64-sve.md (*cond__nontrunc) (*cond__nonextend): New patterns. gcc/testsuite/ * gcc.target/aarch64/sve/cond_convert_1.c: New test. * gcc.target/aarch64/sve/cond_convert_1_run.c: Likewise. * gcc.target/aarch64/sve/cond_convert_2.c: Likewise. * gcc.target/aarch64/sve/cond_convert_2_run.c: Likewise. * gcc.target/aarch64/sve/cond_convert_3.c: Likewise. * gcc.target/aarch64/sve/cond_convert_3_run.c: Likewise. * gcc.target/aarch64/sve/cond_convert_4.c: Likewise. * gcc.target/aarch64/sve/cond_convert_4_run.c: Likewise. * gcc.target/aarch64/sve/cond_convert_5.c: Likewise. * gcc.target/aarch64/sve/cond_convert_5_run.c: Likewise. * gcc.target/aarch64/sve/cond_convert_6.c: Likewise. * gcc.target/aarch64/sve/cond_convert_6_run.c: Likewise. Index: gcc/config/aarch64/aarch64-sve.md =================================================================== --- gcc/config/aarch64/aarch64-sve.md 2019-08-14 11:53:04.636898923 +0100 +++ gcc/config/aarch64/aarch64-sve.md 2019-08-14 11:55:33.251813494 +0100 @@ -4071,6 +4071,39 @@ (define_insn "*aarch64_sve__trunc "fcvtz\t%0., %1/m, %2." ) +;; Predicated float-to-integer conversion with merging, either to the same +;; width or wider. +;; +;; The first alternative doesn't need the earlyclobber, but the only case +;; it would help is the uninteresting one in which operands 2 and 3 are +;; the same register (despite having different modes). Making all the +;; alternatives earlyclobber makes things more consistent for the +;; register allocator. +(define_insn_and_rewrite "*cond__nontrunc" + [(set (match_operand:SVE_HSDI 0 "register_operand" "=&w, &w, ?&w") + (unspec:SVE_HSDI + [(match_operand: 1 "register_operand" "Upl, Upl, Upl") + (unspec:SVE_HSDI + [(match_operand 4) + (match_operand:SI 5 "aarch64_sve_gp_strictness") + (match_operand:SVE_F 2 "register_operand" "w, w, w")] + SVE_COND_FCVTI) + (match_operand:SVE_HSDI 3 "aarch64_simd_reg_or_zero" "0, Dz, w")] + UNSPEC_SEL))] + "TARGET_SVE + && >= + && aarch64_sve_pred_dominates_p (&operands[4], operands[1])" + "@ + fcvtz\t%0., %1/m, %2. + movprfx\t%0., %1/z, %2.\;fcvtz\t%0., %1/m, %2. + movprfx\t%0, %3\;fcvtz\t%0., %1/m, %2." + "&& !rtx_equal_p (operands[1], operands[4])" + { + operands[4] = copy_rtx (operands[1]); + } + [(set_attr "movprfx" "*,yes,yes")] +) + ;; ------------------------------------------------------------------------- ;; ---- [INT<-FP] Packs ;; ------------------------------------------------------------------------- @@ -4155,6 +4188,39 @@ (define_insn "aarch64_sve__extend "cvtf\t%0., %1/m, %2." ) +;; Predicated integer-to-float conversion with merging, either to the same +;; width or narrower. +;; +;; The first alternative doesn't need the earlyclobber, but the only case +;; it would help is the uninteresting one in which operands 2 and 3 are +;; the same register (despite having different modes). Making all the +;; alternatives earlyclobber makes things more consistent for the +;; register allocator. +(define_insn_and_rewrite "*cond__nonextend" + [(set (match_operand:SVE_F 0 "register_operand" "=&w, &w, ?&w") + (unspec:SVE_F + [(match_operand: 1 "register_operand" "Upl, Upl, Upl") + (unspec:SVE_F + [(match_operand 4) + (match_operand:SI 5 "aarch64_sve_gp_strictness") + (match_operand:SVE_HSDI 2 "register_operand" "w, w, w")] + SVE_COND_ICVTF) + (match_operand:SVE_F 3 "aarch64_simd_reg_or_zero" "0, Dz, w")] + UNSPEC_SEL))] + "TARGET_SVE + && >= + && aarch64_sve_pred_dominates_p (&operands[4], operands[1])" + "@ + cvtf\t%0., %1/m, %2. + movprfx\t%0., %1/z, %2.\;cvtf\t%0., %1/m, %2. + movprfx\t%0, %3\;cvtf\t%0., %1/m, %2." + "&& !rtx_equal_p (operands[1], operands[4])" + { + operands[4] = copy_rtx (operands[1]); + } + [(set_attr "movprfx" "*,yes,yes")] +) + ;; ------------------------------------------------------------------------- ;; ---- [FP<-INT] Packs ;; ------------------------------------------------------------------------- Index: gcc/testsuite/gcc.target/aarch64/sve/cond_convert_1.c =================================================================== --- /dev/null 2019-07-30 08:53:31.317691683 +0100 +++ gcc/testsuite/gcc.target/aarch64/sve/cond_convert_1.c 2019-08-14 11:55:33.251813494 +0100 @@ -0,0 +1,37 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize -fno-trapping-math" } */ + +#include + +#define DEF_LOOP(FLOAT_TYPE, INT_TYPE) \ + void __attribute__ ((noipa)) \ + test_##INT_TYPE (FLOAT_TYPE *__restrict r, \ + INT_TYPE *__restrict a, \ + FLOAT_TYPE *__restrict b, \ + INT_TYPE *__restrict pred, int n) \ + { \ + for (int i = 0; i < n; ++i) \ + r[i] = pred[i] ? (FLOAT_TYPE) a[i] : b[i]; \ + } + +#define TEST_ALL(T) \ + T (_Float16, int16_t) \ + T (_Float16, uint16_t) \ + T (float, int32_t) \ + T (float, uint32_t) \ + T (double, int64_t) \ + T (double, uint64_t) + +TEST_ALL (DEF_LOOP) + +/* { dg-final { scan-assembler-times {\tscvtf\tz[0-9]+\.h, p[0-7]/m,} 1 } } */ +/* { dg-final { scan-assembler-times {\tucvtf\tz[0-9]+\.h, p[0-7]/m,} 1 } } */ +/* { dg-final { scan-assembler-times {\tscvtf\tz[0-9]+\.s, p[0-7]/m,} 1 } } */ +/* { dg-final { scan-assembler-times {\tucvtf\tz[0-9]+\.s, p[0-7]/m,} 1 } } */ +/* { dg-final { scan-assembler-times {\tscvtf\tz[0-9]+\.d, p[0-7]/m,} 1 } } */ +/* { dg-final { scan-assembler-times {\tucvtf\tz[0-9]+\.d, p[0-7]/m,} 1 } } */ + +/* { dg-final { scan-assembler-not {\tmov\tz} } } */ +/* At the moment we don't manage to avoid using MOVPRFX. */ +/* { dg-final { scan-assembler-not {\tmovprfx\t} { xfail *-*-* } } } */ +/* { dg-final { scan-assembler-not {\tsel\t} } } */ Index: gcc/testsuite/gcc.target/aarch64/sve/cond_convert_1_run.c =================================================================== --- /dev/null 2019-07-30 08:53:31.317691683 +0100 +++ gcc/testsuite/gcc.target/aarch64/sve/cond_convert_1_run.c 2019-08-14 11:55:33.251813494 +0100 @@ -0,0 +1,29 @@ +/* { dg-do run { target { aarch64_sve_hw } } } */ +/* { dg-options "-O2 -ftree-vectorize -ftrapping-math" } */ + +#include "cond_convert_1.c" + +#define N 99 + +#define TEST_LOOP(FLOAT_TYPE, INT_TYPE) \ + { \ + FLOAT_TYPE r[N], b[N]; \ + INT_TYPE a[N], pred[N]; \ + for (int i = 0; i < N; ++i) \ + { \ + a[i] = (i & 1 ? i : 3 * i) * (i % 3 == 0 ? 1 : -1); \ + b[i] = (i % 9) * (i % 7 + 1); \ + pred[i] = (i % 7 < 4); \ + asm volatile ("" ::: "memory"); \ + } \ + test_##INT_TYPE (r, a, b, pred, N); \ + for (int i = 0; i < N; ++i) \ + if (r[i] != (pred[i] ? (FLOAT_TYPE) a[i] : b[i])) \ + __builtin_abort (); \ + } + +int main () +{ + TEST_ALL (TEST_LOOP) + return 0; +} Index: gcc/testsuite/gcc.target/aarch64/sve/cond_convert_2.c =================================================================== --- /dev/null 2019-07-30 08:53:31.317691683 +0100 +++ gcc/testsuite/gcc.target/aarch64/sve/cond_convert_2.c 2019-08-14 11:55:33.251813494 +0100 @@ -0,0 +1,36 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize -fno-trapping-math" } */ + +#include + +#define DEF_LOOP(FLOAT_TYPE, INT_TYPE) \ + void __attribute__ ((noipa)) \ + test_##INT_TYPE (FLOAT_TYPE *__restrict r, \ + INT_TYPE *__restrict a, \ + INT_TYPE *__restrict pred, int n) \ + { \ + for (int i = 0; i < n; ++i) \ + r[i] = pred[i] ? (FLOAT_TYPE) a[i] : 1.0; \ + } + +#define TEST_ALL(T) \ + T (_Float16, int16_t) \ + T (_Float16, uint16_t) \ + T (float, int32_t) \ + T (float, uint32_t) \ + T (double, int64_t) \ + T (double, uint64_t) + +TEST_ALL (DEF_LOOP) + +/* { dg-final { scan-assembler-times {\tscvtf\tz[0-9]+\.h, p[0-7]/m,} 1 } } */ +/* { dg-final { scan-assembler-times {\tucvtf\tz[0-9]+\.h, p[0-7]/m,} 1 } } */ +/* { dg-final { scan-assembler-times {\tscvtf\tz[0-9]+\.s, p[0-7]/m,} 1 } } */ +/* { dg-final { scan-assembler-times {\tucvtf\tz[0-9]+\.s, p[0-7]/m,} 1 } } */ +/* { dg-final { scan-assembler-times {\tscvtf\tz[0-9]+\.d, p[0-7]/m,} 1 } } */ +/* { dg-final { scan-assembler-times {\tucvtf\tz[0-9]+\.d, p[0-7]/m,} 1 } } */ + +/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+, z[0-9]+\n} 6 } } */ + +/* { dg-final { scan-assembler-not {\tmov\tz[^\n]*z} } } */ +/* { dg-final { scan-assembler-not {\tsel\t} } } */ Index: gcc/testsuite/gcc.target/aarch64/sve/cond_convert_2_run.c =================================================================== --- /dev/null 2019-07-30 08:53:31.317691683 +0100 +++ gcc/testsuite/gcc.target/aarch64/sve/cond_convert_2_run.c 2019-08-14 11:55:33.251813494 +0100 @@ -0,0 +1,28 @@ +/* { dg-do run { target { aarch64_sve_hw } } } */ +/* { dg-options "-O2 -ftree-vectorize -ftrapping-math" } */ + +#include "cond_convert_2.c" + +#define N 99 + +#define TEST_LOOP(FLOAT_TYPE, INT_TYPE) \ + { \ + FLOAT_TYPE r[N]; \ + INT_TYPE a[N], pred[N]; \ + for (int i = 0; i < N; ++i) \ + { \ + a[i] = (i & 1 ? i : 3 * i) * (i % 3 == 0 ? 1 : -1); \ + pred[i] = (i % 7 < 4); \ + asm volatile ("" ::: "memory"); \ + } \ + test_##INT_TYPE (r, a, pred, N); \ + for (int i = 0; i < N; ++i) \ + if (r[i] != (pred[i] ? (FLOAT_TYPE) a[i] : 1.0)) \ + __builtin_abort (); \ + } + +int main () +{ + TEST_ALL (TEST_LOOP) + return 0; +} Index: gcc/testsuite/gcc.target/aarch64/sve/cond_convert_3.c =================================================================== --- /dev/null 2019-07-30 08:53:31.317691683 +0100 +++ gcc/testsuite/gcc.target/aarch64/sve/cond_convert_3.c 2019-08-14 11:55:33.251813494 +0100 @@ -0,0 +1,40 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize -fno-trapping-math" } */ + +#include + +#define DEF_LOOP(FLOAT_TYPE, INT_TYPE) \ + void __attribute__ ((noipa)) \ + test_##INT_TYPE (FLOAT_TYPE *__restrict r, \ + INT_TYPE *__restrict a, \ + INT_TYPE *__restrict pred, int n) \ + { \ + for (int i = 0; i < n; ++i) \ + r[i] = pred[i] ? (FLOAT_TYPE) a[i] : 0.0; \ + } + +#define TEST_ALL(T) \ + T (_Float16, int16_t) \ + T (_Float16, uint16_t) \ + T (float, int32_t) \ + T (float, uint32_t) \ + T (double, int64_t) \ + T (double, uint64_t) + +TEST_ALL (DEF_LOOP) + +/* { dg-final { scan-assembler-times {\tscvtf\tz[0-9]+\.h, p[0-7]/m,} 1 } } */ +/* { dg-final { scan-assembler-times {\tucvtf\tz[0-9]+\.h, p[0-7]/m,} 1 } } */ +/* { dg-final { scan-assembler-times {\tscvtf\tz[0-9]+\.s, p[0-7]/m,} 1 } } */ +/* { dg-final { scan-assembler-times {\tucvtf\tz[0-9]+\.s, p[0-7]/m,} 1 } } */ +/* { dg-final { scan-assembler-times {\tscvtf\tz[0-9]+\.d, p[0-7]/m,} 1 } } */ +/* { dg-final { scan-assembler-times {\tucvtf\tz[0-9]+\.d, p[0-7]/m,} 1 } } */ + +/* Really we should be able to use MOVPRFX /z here, but at the moment + we're relying on combine to merge a SEL and an arithmetic operation, + and the SEL doesn't allow the "false" value to be zero when the "true" + value is a register. */ +/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+, z[0-9]+\n} 6 } } */ + +/* { dg-final { scan-assembler-not {\tmov\tz[^\n]*z} } } */ +/* { dg-final { scan-assembler-not {\tsel\t} } } */ Index: gcc/testsuite/gcc.target/aarch64/sve/cond_convert_3_run.c =================================================================== --- /dev/null 2019-07-30 08:53:31.317691683 +0100 +++ gcc/testsuite/gcc.target/aarch64/sve/cond_convert_3_run.c 2019-08-14 11:55:33.251813494 +0100 @@ -0,0 +1,28 @@ +/* { dg-do run { target { aarch64_sve_hw } } } */ +/* { dg-options "-O2 -ftree-vectorize -ftrapping-math" } */ + +#include "cond_convert_3.c" + +#define N 99 + +#define TEST_LOOP(FLOAT_TYPE, INT_TYPE) \ + { \ + FLOAT_TYPE r[N]; \ + INT_TYPE a[N], pred[N]; \ + for (int i = 0; i < N; ++i) \ + { \ + a[i] = (i & 1 ? i : 3 * i) * (i % 3 == 0 ? 1 : -1); \ + pred[i] = (i % 7 < 4); \ + asm volatile ("" ::: "memory"); \ + } \ + test_##INT_TYPE (r, a, pred, N); \ + for (int i = 0; i < N; ++i) \ + if (r[i] != (pred[i] ? (FLOAT_TYPE) a[i] : 0.0)) \ + __builtin_abort (); \ + } + +int main () +{ + TEST_ALL (TEST_LOOP) + return 0; +} Index: gcc/testsuite/gcc.target/aarch64/sve/cond_convert_4.c =================================================================== --- /dev/null 2019-07-30 08:53:31.317691683 +0100 +++ gcc/testsuite/gcc.target/aarch64/sve/cond_convert_4.c 2019-08-14 11:55:33.251813494 +0100 @@ -0,0 +1,37 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize -fno-trapping-math" } */ + +#include + +#define DEF_LOOP(FLOAT_TYPE, INT_TYPE) \ + void __attribute__ ((noipa)) \ + test_##INT_TYPE (INT_TYPE *__restrict r, \ + FLOAT_TYPE *__restrict a, \ + INT_TYPE *__restrict b, \ + INT_TYPE *__restrict pred, int n) \ + { \ + for (int i = 0; i < n; ++i) \ + r[i] = pred[i] ? (INT_TYPE) a[i] : b[i]; \ + } + +#define TEST_ALL(T) \ + T (_Float16, int16_t) \ + T (_Float16, uint16_t) \ + T (float, int32_t) \ + T (float, uint32_t) \ + T (double, int64_t) \ + T (double, uint64_t) + +TEST_ALL (DEF_LOOP) + +/* { dg-final { scan-assembler-times {\tfcvtzs\tz[0-9]+\.h, p[0-7]/m,} 1 } } */ +/* { dg-final { scan-assembler-times {\tfcvtzu\tz[0-9]+\.h, p[0-7]/m,} 1 } } */ +/* { dg-final { scan-assembler-times {\tfcvtzs\tz[0-9]+\.s, p[0-7]/m,} 1 } } */ +/* { dg-final { scan-assembler-times {\tfcvtzu\tz[0-9]+\.s, p[0-7]/m,} 1 } } */ +/* { dg-final { scan-assembler-times {\tfcvtzs\tz[0-9]+\.d, p[0-7]/m,} 1 } } */ +/* { dg-final { scan-assembler-times {\tfcvtzu\tz[0-9]+\.d, p[0-7]/m,} 1 } } */ + +/* { dg-final { scan-assembler-not {\tmov\tz} } } */ +/* At the moment we don't manage to avoid using MOVPRFX. */ +/* { dg-final { scan-assembler-not {\tmovprfx\t} { xfail *-*-* } } } */ +/* { dg-final { scan-assembler-not {\tsel\t} } } */ Index: gcc/testsuite/gcc.target/aarch64/sve/cond_convert_4_run.c =================================================================== --- /dev/null 2019-07-30 08:53:31.317691683 +0100 +++ gcc/testsuite/gcc.target/aarch64/sve/cond_convert_4_run.c 2019-08-14 11:55:33.251813494 +0100 @@ -0,0 +1,29 @@ +/* { dg-do run { target { aarch64_sve_hw } } } */ +/* { dg-options "-O2 -ftree-vectorize -ftrapping-math" } */ + +#include "cond_convert_4.c" + +#define N 99 + +#define TEST_LOOP(FLOAT_TYPE, INT_TYPE) \ + { \ + INT_TYPE r[N], b[N], pred[N]; \ + FLOAT_TYPE a[N]; \ + for (int i = 0; i < N; ++i) \ + { \ + a[i] = (i & 1 ? i : 3 * i) * (i % 3 == 0 ? 1 : -1); \ + b[i] = (i % 9) * (i % 7 + 1); \ + pred[i] = (i % 7 < 4); \ + asm volatile ("" ::: "memory"); \ + } \ + test_##INT_TYPE (r, a, b, pred, N); \ + for (int i = 0; i < N; ++i) \ + if (r[i] != (pred[i] ? (INT_TYPE) a[i] : b[i])) \ + __builtin_abort (); \ + } + +int main () +{ + TEST_ALL (TEST_LOOP) + return 0; +} Index: gcc/testsuite/gcc.target/aarch64/sve/cond_convert_5.c =================================================================== --- /dev/null 2019-07-30 08:53:31.317691683 +0100 +++ gcc/testsuite/gcc.target/aarch64/sve/cond_convert_5.c 2019-08-14 11:55:33.251813494 +0100 @@ -0,0 +1,36 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize -fno-trapping-math" } */ + +#include + +#define DEF_LOOP(FLOAT_TYPE, INT_TYPE) \ + void __attribute__ ((noipa)) \ + test_##INT_TYPE (INT_TYPE *__restrict r, \ + FLOAT_TYPE *__restrict a, \ + INT_TYPE *__restrict pred, int n) \ + { \ + for (int i = 0; i < n; ++i) \ + r[i] = pred[i] ? (INT_TYPE) a[i] : 72; \ + } + +#define TEST_ALL(T) \ + T (_Float16, int16_t) \ + T (_Float16, uint16_t) \ + T (float, int32_t) \ + T (float, uint32_t) \ + T (double, int64_t) \ + T (double, uint64_t) + +TEST_ALL (DEF_LOOP) + +/* { dg-final { scan-assembler-times {\tfcvtzs\tz[0-9]+\.h, p[0-7]/m,} 1 } } */ +/* { dg-final { scan-assembler-times {\tfcvtzu\tz[0-9]+\.h, p[0-7]/m,} 1 } } */ +/* { dg-final { scan-assembler-times {\tfcvtzs\tz[0-9]+\.s, p[0-7]/m,} 1 } } */ +/* { dg-final { scan-assembler-times {\tfcvtzu\tz[0-9]+\.s, p[0-7]/m,} 1 } } */ +/* { dg-final { scan-assembler-times {\tfcvtzs\tz[0-9]+\.d, p[0-7]/m,} 1 } } */ +/* { dg-final { scan-assembler-times {\tfcvtzu\tz[0-9]+\.d, p[0-7]/m,} 1 } } */ + +/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+, z[0-9]+\n} 6 } } */ + +/* { dg-final { scan-assembler-not {\tmov\tz[^\n]*z} } } */ +/* { dg-final { scan-assembler-not {\tsel\t} } } */ Index: gcc/testsuite/gcc.target/aarch64/sve/cond_convert_5_run.c =================================================================== --- /dev/null 2019-07-30 08:53:31.317691683 +0100 +++ gcc/testsuite/gcc.target/aarch64/sve/cond_convert_5_run.c 2019-08-14 11:55:33.251813494 +0100 @@ -0,0 +1,28 @@ +/* { dg-do run { target { aarch64_sve_hw } } } */ +/* { dg-options "-O2 -ftree-vectorize -ftrapping-math" } */ + +#include "cond_convert_5.c" + +#define N 99 + +#define TEST_LOOP(FLOAT_TYPE, INT_TYPE) \ + { \ + INT_TYPE r[N], pred[N]; \ + FLOAT_TYPE a[N]; \ + for (int i = 0; i < N; ++i) \ + { \ + a[i] = (i & 1 ? i : 3 * i) * (i % 3 == 0 ? 1 : -1); \ + pred[i] = (i % 7 < 4); \ + asm volatile ("" ::: "memory"); \ + } \ + test_##INT_TYPE (r, a, pred, N); \ + for (int i = 0; i < N; ++i) \ + if (r[i] != (pred[i] ? (INT_TYPE) a[i] : 72)) \ + __builtin_abort (); \ + } + +int main () +{ + TEST_ALL (TEST_LOOP) + return 0; +} Index: gcc/testsuite/gcc.target/aarch64/sve/cond_convert_6.c =================================================================== --- /dev/null 2019-07-30 08:53:31.317691683 +0100 +++ gcc/testsuite/gcc.target/aarch64/sve/cond_convert_6.c 2019-08-14 11:55:33.251813494 +0100 @@ -0,0 +1,40 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -ftree-vectorize -fno-trapping-math" } */ + +#include + +#define DEF_LOOP(FLOAT_TYPE, INT_TYPE) \ + void __attribute__ ((noipa)) \ + test_##INT_TYPE (INT_TYPE *__restrict r, \ + FLOAT_TYPE *__restrict a, \ + INT_TYPE *__restrict pred, int n) \ + { \ + for (int i = 0; i < n; ++i) \ + r[i] = pred[i] ? (INT_TYPE) a[i] : 0; \ + } + +#define TEST_ALL(T) \ + T (_Float16, int16_t) \ + T (_Float16, uint16_t) \ + T (float, int32_t) \ + T (float, uint32_t) \ + T (double, int64_t) \ + T (double, uint64_t) + +TEST_ALL (DEF_LOOP) + +/* { dg-final { scan-assembler-times {\tfcvtzs\tz[0-9]+\.h, p[0-7]/m,} 1 } } */ +/* { dg-final { scan-assembler-times {\tfcvtzu\tz[0-9]+\.h, p[0-7]/m,} 1 } } */ +/* { dg-final { scan-assembler-times {\tfcvtzs\tz[0-9]+\.s, p[0-7]/m,} 1 } } */ +/* { dg-final { scan-assembler-times {\tfcvtzu\tz[0-9]+\.s, p[0-7]/m,} 1 } } */ +/* { dg-final { scan-assembler-times {\tfcvtzs\tz[0-9]+\.d, p[0-7]/m,} 1 } } */ +/* { dg-final { scan-assembler-times {\tfcvtzu\tz[0-9]+\.d, p[0-7]/m,} 1 } } */ + +/* Really we should be able to use MOVPRFX /z here, but at the moment + we're relying on combine to merge a SEL and an arithmetic operation, + and the SEL doesn't allow the "false" value to be zero when the "true" + value is a register. */ +/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+, z[0-9]+\n} 6 } } */ + +/* { dg-final { scan-assembler-not {\tmov\tz[^\n]*z} } } */ +/* { dg-final { scan-assembler-not {\tsel\t} } } */ Index: gcc/testsuite/gcc.target/aarch64/sve/cond_convert_6_run.c =================================================================== --- /dev/null 2019-07-30 08:53:31.317691683 +0100 +++ gcc/testsuite/gcc.target/aarch64/sve/cond_convert_6_run.c 2019-08-14 11:55:33.251813494 +0100 @@ -0,0 +1,28 @@ +/* { dg-do run { target { aarch64_sve_hw } } } */ +/* { dg-options "-O2 -ftree-vectorize -ftrapping-math" } */ + +#include "cond_convert_6.c" + +#define N 99 + +#define TEST_LOOP(FLOAT_TYPE, INT_TYPE) \ + { \ + INT_TYPE r[N], pred[N]; \ + FLOAT_TYPE a[N]; \ + for (int i = 0; i < N; ++i) \ + { \ + a[i] = (i & 1 ? i : 3 * i) * (i % 3 == 0 ? 1 : -1); \ + pred[i] = (i % 7 < 4); \ + asm volatile ("" ::: "memory"); \ + } \ + test_##INT_TYPE (r, a, pred, N); \ + for (int i = 0; i < N; ++i) \ + if (r[i] != (pred[i] ? (INT_TYPE) a[i] : 0)) \ + __builtin_abort (); \ + } + +int main () +{ + TEST_ALL (TEST_LOOP) + return 0; +}