From patchwork Wed Aug 14 10:54:02 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Sandiford X-Patchwork-Id: 1146961 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-506921-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="RMHP8U+V"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 467mfv5TJMz9sNC for ; Wed, 14 Aug 2019 20:54:15 +1000 (AEST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:mime-version:content-type; q=dns; s=default; b=idtJOS4SVgWxGwxUNgbB9UvJh6Sq3pDnNAtyjk7PETrRRjdoUF 84j7wuVnlQw7iJ/+aNfyQKN/zy88IalTh4zD9UkGTR2/hEX1KCTAxh6JhETavWD/ iM8AOaq4cOys32vMPyBLpR7sriIVdrsZLDtL3qfSTpVHuGAG7ZFWndAeg= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:cc:subject:date:message-id:mime-version:content-type; s= default; bh=MoKhNLBf6wqAbmcDYWAqkynwvvQ=; b=RMHP8U+V4MYOiABxfr7l P25Stn4YwBBy+2tRKo0DPJ0WrfVEZUZW9LOcwq9DZSM3DEp7Ya/QK5XLv0cB5s1L dwftClgoHdmWxDl2syT9wbo5GL1YCXe/gkZL1ui8NpEpHeVaiaMnGYLsPapjjE/O EX49tcuKoOyEsaogLI6zd7g= Received: (qmail 125394 invoked by alias); 14 Aug 2019 10:54:08 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 125386 invoked by uid 89); 14 Aug 2019 10:54:08 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-8.4 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_2, GIT_PATCH_3, KAM_ASCII_DIVIDERS autolearn=ham version=3.3.1 spammy= X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.110.172) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 14 Aug 2019 10:54:06 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 84E5328; Wed, 14 Aug 2019 03:54:04 -0700 (PDT) Received: from localhost (e121540-lin.manchester.arm.com [10.32.99.62]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 1043F3F706; Wed, 14 Aug 2019 03:54:03 -0700 (PDT) From: Richard Sandiford To: gcc-patches@gcc.gnu.org Mail-Followup-To: gcc-patches@gcc.gnu.org, Kugan Vivekanandarajah , richard.sandiford@arm.com Cc: Kugan Vivekanandarajah Subject: [committed][AArch64] Add SVE conditional floating-point unary patterns Date: Wed, 14 Aug 2019 11:54:02 +0100 Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/26.1 (gnu/linux) MIME-Version: 1.0 X-IsSubscribed: yes This patch adds patterns to match conditional unary operations on floating-point modes. At the moment we rely on combine to merge separate arithmetic and vcond_mask operations, and since the latter doesn't accept zero operands, we miss out on the opportunity to use the movprfx /z alternative. (This alternative is tested by the ACLE patches though.) Tested on aarch64-linux-gnu (with and without SVE) and aarch64_be-elf. Applied as r274477. Richard 2019-08-14 Richard Sandiford Kugan Vivekanandarajah gcc/ * config/aarch64/aarch64-sve.md (*cond__2): New pattern. (*cond__any): Likewise. gcc/testsuite/ * gcc.target/aarch64/sve/cond_unary_1.c: Add tests for floating-point types. * gcc.target/aarch64/sve/cond_unary_2.c: Likewise. * gcc.target/aarch64/sve/cond_unary_3.c: Likewise. * gcc.target/aarch64/sve/cond_unary_4.c: Likewise. Index: gcc/config/aarch64/aarch64-sve.md =================================================================== --- gcc/config/aarch64/aarch64-sve.md 2019-08-14 11:48:45.114792555 +0100 +++ gcc/config/aarch64/aarch64-sve.md 2019-08-14 11:51:07.537753363 +0100 @@ -1624,6 +1624,62 @@ (define_insn "*2" "\t%0., %1/m, %2." ) +;; Predicated floating-point unary arithmetic, merging with the first input. +(define_insn_and_rewrite "*cond__2" + [(set (match_operand:SVE_F 0 "register_operand" "=w, ?&w") + (unspec:SVE_F + [(match_operand: 1 "register_operand" "Upl, Upl") + (unspec:SVE_F + [(match_operand 3) + (match_operand:SI 4 "aarch64_sve_gp_strictness") + (match_operand:SVE_F 2 "register_operand" "0, w")] + SVE_COND_FP_UNARY) + (match_dup 2)] + UNSPEC_SEL))] + "TARGET_SVE && aarch64_sve_pred_dominates_p (&operands[3], operands[1])" + "@ + \t%0., %1/m, %0. + movprfx\t%0, %2\;\t%0., %1/m, %2." + "&& !rtx_equal_p (operands[1], operands[3])" + { + operands[3] = copy_rtx (operands[1]); + } + [(set_attr "movprfx" "*,yes")] +) + +;; Predicated floating-point unary arithmetic, merging with an independent +;; value. +;; +;; The earlyclobber isn't needed for the first alternative, but omitting +;; it would only help the case in which operands 2 and 3 are the same, +;; which is handled above rather than here. Marking all the alternatives +;; as earlyclobber helps to make the instruction more regular to the +;; register allocator. +(define_insn_and_rewrite "*cond__any" + [(set (match_operand:SVE_F 0 "register_operand" "=&w, ?&w, ?&w") + (unspec:SVE_F + [(match_operand: 1 "register_operand" "Upl, Upl, Upl") + (unspec:SVE_F + [(match_operand 4) + (match_operand:SI 5 "aarch64_sve_gp_strictness") + (match_operand:SVE_F 2 "register_operand" "w, w, w")] + SVE_COND_FP_UNARY) + (match_operand:SVE_F 3 "aarch64_simd_reg_or_zero" "0, Dz, w")] + UNSPEC_SEL))] + "TARGET_SVE + && !rtx_equal_p (operands[2], operands[3]) + && aarch64_sve_pred_dominates_p (&operands[4], operands[1])" + "@ + \t%0., %1/m, %2. + movprfx\t%0., %1/z, %2.\;\t%0., %1/m, %2. + movprfx\t%0, %3\;\t%0., %1/m, %2." + "&& !rtx_equal_p (operands[1], operands[4])" + { + operands[4] = copy_rtx (operands[1]); + } + [(set_attr "movprfx" "*,yes,yes")] +) + ;; ------------------------------------------------------------------------- ;; ---- [PRED] Inverse ;; ------------------------------------------------------------------------- Index: gcc/testsuite/gcc.target/aarch64/sve/cond_unary_1.c =================================================================== --- gcc/testsuite/gcc.target/aarch64/sve/cond_unary_1.c 2019-08-14 11:48:45.114792555 +0100 +++ gcc/testsuite/gcc.target/aarch64/sve/cond_unary_1.c 2019-08-14 11:51:07.537753363 +0100 @@ -15,15 +15,22 @@ #define DEF_LOOP(TYPE, OP) \ r[i] = pred[i] ? OP (a[i]) : a[i]; \ } -#define TEST_TYPE(T, TYPE) \ +#define TEST_INT_TYPE(T, TYPE) \ T (TYPE, abs) \ T (TYPE, neg) +#define TEST_FLOAT_TYPE(T, TYPE, SUFFIX) \ + T (TYPE, __builtin_fabs##SUFFIX) \ + T (TYPE, neg) + #define TEST_ALL(T) \ - TEST_TYPE (T, int8_t) \ - TEST_TYPE (T, int16_t) \ - TEST_TYPE (T, int32_t) \ - TEST_TYPE (T, int64_t) + TEST_INT_TYPE (T, int8_t) \ + TEST_INT_TYPE (T, int16_t) \ + TEST_INT_TYPE (T, int32_t) \ + TEST_INT_TYPE (T, int64_t) \ + TEST_FLOAT_TYPE (T, _Float16, f16) \ + TEST_FLOAT_TYPE (T, float, f) \ + TEST_FLOAT_TYPE (T, double, ) TEST_ALL (DEF_LOOP) @@ -37,6 +44,14 @@ TEST_ALL (DEF_LOOP) /* { dg-final { scan-assembler-times {\tneg\tz[0-9]+\.s, p[0-7]/m,} 1 } } */ /* { dg-final { scan-assembler-times {\tneg\tz[0-9]+\.d, p[0-7]/m,} 1 } } */ +/* { dg-final { scan-assembler-times {\tfabs\tz[0-9]+\.h, p[0-7]/m,} 1 } } */ +/* { dg-final { scan-assembler-times {\tfabs\tz[0-9]+\.s, p[0-7]/m,} 1 } } */ +/* { dg-final { scan-assembler-times {\tfabs\tz[0-9]+\.d, p[0-7]/m,} 1 } } */ + +/* { dg-final { scan-assembler-times {\tfneg\tz[0-9]+\.h, p[0-7]/m,} 1 } } */ +/* { dg-final { scan-assembler-times {\tfneg\tz[0-9]+\.s, p[0-7]/m,} 1 } } */ +/* { dg-final { scan-assembler-times {\tfneg\tz[0-9]+\.d, p[0-7]/m,} 1 } } */ + /* { dg-final { scan-assembler-not {\tmov\tz} } } */ /* { dg-final { scan-assembler-not {\tmovprfx\t} } } */ /* XFAILed because the ?: gets canonicalized so that the operation is in Index: gcc/testsuite/gcc.target/aarch64/sve/cond_unary_2.c =================================================================== --- gcc/testsuite/gcc.target/aarch64/sve/cond_unary_2.c 2019-08-14 11:48:45.118792524 +0100 +++ gcc/testsuite/gcc.target/aarch64/sve/cond_unary_2.c 2019-08-14 11:51:07.537753363 +0100 @@ -16,15 +16,22 @@ #define DEF_LOOP(TYPE, OP) \ r[i] = pred[i] ? OP (a[i]) : b[i]; \ } -#define TEST_TYPE(T, TYPE) \ +#define TEST_INT_TYPE(T, TYPE) \ T (TYPE, abs) \ T (TYPE, neg) +#define TEST_FLOAT_TYPE(T, TYPE, SUFFIX) \ + T (TYPE, __builtin_fabs##SUFFIX) \ + T (TYPE, neg) + #define TEST_ALL(T) \ - TEST_TYPE (T, int8_t) \ - TEST_TYPE (T, int16_t) \ - TEST_TYPE (T, int32_t) \ - TEST_TYPE (T, int64_t) + TEST_INT_TYPE (T, int8_t) \ + TEST_INT_TYPE (T, int16_t) \ + TEST_INT_TYPE (T, int32_t) \ + TEST_INT_TYPE (T, int64_t) \ + TEST_FLOAT_TYPE (T, _Float16, f16) \ + TEST_FLOAT_TYPE (T, float, f) \ + TEST_FLOAT_TYPE (T, double, ) TEST_ALL (DEF_LOOP) @@ -38,6 +45,17 @@ TEST_ALL (DEF_LOOP) /* { dg-final { scan-assembler-times {\tneg\tz[0-9]+\.s, p[0-7]/m,} 1 } } */ /* { dg-final { scan-assembler-times {\tneg\tz[0-9]+\.d, p[0-7]/m,} 1 } } */ +/* { dg-final { scan-assembler-times {\tfabs\tz[0-9]+\.h, p[0-7]/m,} 1 } } */ +/* { dg-final { scan-assembler-times {\tfabs\tz[0-9]+\.s, p[0-7]/m,} 1 } } */ +/* { dg-final { scan-assembler-times {\tfabs\tz[0-9]+\.d, p[0-7]/m,} 1 } } */ + +/* { dg-final { scan-assembler-times {\tfneg\tz[0-9]+\.h, p[0-7]/m,} 1 } } */ +/* { dg-final { scan-assembler-times {\tfneg\tz[0-9]+\.s, p[0-7]/m,} 1 } } */ +/* { dg-final { scan-assembler-times {\tfneg\tz[0-9]+\.d, p[0-7]/m,} 1 } } */ + /* { dg-final { scan-assembler-not {\tmov\tz} } } */ -/* { dg-final { scan-assembler-not {\tmovprfx\t} } } */ +/* At the moment we don't manage to avoid using MOVPRFX for the + floating-point functions. */ +/* { dg-final { scan-assembler-not {\tmovprfx\t} { xfail *-*-* } } } */ +/* { dg-final { scan-assembler-times {\tmovprfx\t} 6 } } */ /* { dg-final { scan-assembler-not {\tsel\t} } } */ Index: gcc/testsuite/gcc.target/aarch64/sve/cond_unary_3.c =================================================================== --- gcc/testsuite/gcc.target/aarch64/sve/cond_unary_3.c 2019-08-14 11:48:45.118792524 +0100 +++ gcc/testsuite/gcc.target/aarch64/sve/cond_unary_3.c 2019-08-14 11:51:07.537753363 +0100 @@ -15,15 +15,22 @@ #define DEF_LOOP(TYPE, OP) \ r[i] = pred[i] ? OP (a[i]) : 5; \ } -#define TEST_TYPE(T, TYPE) \ +#define TEST_INT_TYPE(T, TYPE) \ T (TYPE, abs) \ T (TYPE, neg) +#define TEST_FLOAT_TYPE(T, TYPE, SUFFIX) \ + T (TYPE, __builtin_fabs##SUFFIX) \ + T (TYPE, neg) + #define TEST_ALL(T) \ - TEST_TYPE (T, int8_t) \ - TEST_TYPE (T, int16_t) \ - TEST_TYPE (T, int32_t) \ - TEST_TYPE (T, int64_t) + TEST_INT_TYPE (T, int8_t) \ + TEST_INT_TYPE (T, int16_t) \ + TEST_INT_TYPE (T, int32_t) \ + TEST_INT_TYPE (T, int64_t) \ + TEST_FLOAT_TYPE (T, _Float16, f16) \ + TEST_FLOAT_TYPE (T, float, f) \ + TEST_FLOAT_TYPE (T, double, ) TEST_ALL (DEF_LOOP) @@ -37,7 +44,15 @@ TEST_ALL (DEF_LOOP) /* { dg-final { scan-assembler-times {\tneg\tz[0-9]+\.s, p[0-7]/m,} 1 } } */ /* { dg-final { scan-assembler-times {\tneg\tz[0-9]+\.d, p[0-7]/m,} 1 } } */ -/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+, z[0-9]+\n} 8 } } */ +/* { dg-final { scan-assembler-times {\tfabs\tz[0-9]+\.h, p[0-7]/m,} 1 } } */ +/* { dg-final { scan-assembler-times {\tfabs\tz[0-9]+\.s, p[0-7]/m,} 1 } } */ +/* { dg-final { scan-assembler-times {\tfabs\tz[0-9]+\.d, p[0-7]/m,} 1 } } */ + +/* { dg-final { scan-assembler-times {\tfneg\tz[0-9]+\.h, p[0-7]/m,} 1 } } */ +/* { dg-final { scan-assembler-times {\tfneg\tz[0-9]+\.s, p[0-7]/m,} 1 } } */ +/* { dg-final { scan-assembler-times {\tfneg\tz[0-9]+\.d, p[0-7]/m,} 1 } } */ + +/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+, z[0-9]+\n} 14 } } */ /* { dg-final { scan-assembler-not {\tmov\tz[^\n]*z} } } */ /* { dg-final { scan-assembler-not {\tsel\t} } } */ Index: gcc/testsuite/gcc.target/aarch64/sve/cond_unary_4.c =================================================================== --- gcc/testsuite/gcc.target/aarch64/sve/cond_unary_4.c 2019-08-14 11:48:45.118792524 +0100 +++ gcc/testsuite/gcc.target/aarch64/sve/cond_unary_4.c 2019-08-14 11:51:07.537753363 +0100 @@ -15,15 +15,22 @@ #define DEF_LOOP(TYPE, OP) \ r[i] = pred[i] ? OP (a[i]) : 0; \ } -#define TEST_TYPE(T, TYPE) \ +#define TEST_INT_TYPE(T, TYPE) \ T (TYPE, abs) \ T (TYPE, neg) +#define TEST_FLOAT_TYPE(T, TYPE, SUFFIX) \ + T (TYPE, __builtin_fabs##SUFFIX) \ + T (TYPE, neg) + #define TEST_ALL(T) \ - TEST_TYPE (T, int8_t) \ - TEST_TYPE (T, int16_t) \ - TEST_TYPE (T, int32_t) \ - TEST_TYPE (T, int64_t) + TEST_INT_TYPE (T, int8_t) \ + TEST_INT_TYPE (T, int16_t) \ + TEST_INT_TYPE (T, int32_t) \ + TEST_INT_TYPE (T, int64_t) \ + TEST_FLOAT_TYPE (T, _Float16, f16) \ + TEST_FLOAT_TYPE (T, float, f) \ + TEST_FLOAT_TYPE (T, double, ) TEST_ALL (DEF_LOOP) @@ -37,11 +44,19 @@ TEST_ALL (DEF_LOOP) /* { dg-final { scan-assembler-times {\tneg\tz[0-9]+\.s, p[0-7]/m,} 1 } } */ /* { dg-final { scan-assembler-times {\tneg\tz[0-9]+\.d, p[0-7]/m,} 1 } } */ +/* { dg-final { scan-assembler-times {\tfabs\tz[0-9]+\.h, p[0-7]/m,} 1 } } */ +/* { dg-final { scan-assembler-times {\tfabs\tz[0-9]+\.s, p[0-7]/m,} 1 } } */ +/* { dg-final { scan-assembler-times {\tfabs\tz[0-9]+\.d, p[0-7]/m,} 1 } } */ + +/* { dg-final { scan-assembler-times {\tfneg\tz[0-9]+\.h, p[0-7]/m,} 1 } } */ +/* { dg-final { scan-assembler-times {\tfneg\tz[0-9]+\.s, p[0-7]/m,} 1 } } */ +/* { dg-final { scan-assembler-times {\tfneg\tz[0-9]+\.d, p[0-7]/m,} 1 } } */ + /* Really we should be able to use MOVPRFX /z here, but at the moment we're relying on combine to merge a SEL and an arithmetic operation, and the SEL doesn't allow the "false" value to be zero when the "true" value is a register. */ -/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+, z[0-9]+\n} 8 } } */ +/* { dg-final { scan-assembler-times {\tmovprfx\tz[0-9]+, z[0-9]+\n} 14 } } */ /* { dg-final { scan-assembler-not {\tmov\tz[^\n]*z} } } */ /* { dg-final { scan-assembler-not {\tsel\t} } } */