From patchwork Wed Aug 14 10:43:34 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Shih X-Patchwork-Id: 1146941 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 467mSC0bB6z9sN1 for ; Wed, 14 Aug 2019 20:44:59 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726721AbfHNKo6 (ORCPT ); Wed, 14 Aug 2019 06:44:58 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:5802 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726551AbfHNKo6 (ORCPT ); Wed, 14 Aug 2019 06:44:58 -0400 X-UUID: 20eb46e758b0455b9f25295df721bdbd-20190814 X-UUID: 20eb46e758b0455b9f25295df721bdbd-20190814 Received: from mtkcas07.mediatek.inc [(172.21.101.84)] by mailgw01.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0707 with TLS) with ESMTP id 867862673; Wed, 14 Aug 2019 18:44:47 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs05n1.mediatek.inc (172.21.101.15) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Wed, 14 Aug 2019 18:44:50 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Wed, 14 Aug 2019 18:44:50 +0800 From: Sam Shih To: Rob Herring , Mark Rutland , Matthias Brugger , Thierry Reding CC: Ryder Lee , John Crispin , , , , , Sam Shih Subject: [PATCH v2 4/10] dt-bindings: pwm: add a property "num-pwms" Date: Wed, 14 Aug 2019 18:43:34 +0800 Message-ID: <4107497fa8564032cac49e70680a9aa7bbb312eb.1548313019.git.ryder.lee@mediatek.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <621e49c01b943edb6ddac9182f34719eb0727f01.1548313019.git.ryder.lee@mediatek.com> References: <621e49c01b943edb6ddac9182f34719eb0727f01.1548313019.git.ryder.lee@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Ryder Lee This adds a property "num-pwms" in example so that we could specify the number of PWM channels via device tree. Signed-off-by: Ryder Lee Signed-off-by: Sam Shih Reviewed-by: Matthias Brugger --- Changes since v2: - use num-pwms instead of mediatek,num-pwms. - modify the description of clocks to make it simple. Changes since v1: - add a Reviewed-by tag. --- Documentation/devicetree/bindings/pwm/pwm-mediatek.txt | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/pwm/pwm-mediatek.txt b/Documentation/devicetree/bindings/pwm/pwm-mediatek.txt index 991728c..ea95b49 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-mediatek.txt +++ b/Documentation/devicetree/bindings/pwm/pwm-mediatek.txt @@ -14,12 +14,12 @@ Required properties: has no clocks - "top": the top clock generator - "main": clock used by the PWM core - - "pwm1-8": the eight per PWM clocks for mt2712 - - "pwm1-6": the six per PWM clocks for mt7622 - - "pwm1-5": the five per PWM clocks for mt7623 + - "pwm1-N": the PWM clocks for each channel + where N starting from 1 to the maximum number of PWM channels - pinctrl-names: Must contain a "default" entry. - pinctrl-0: One property must exist for each entry in pinctrl-names. See pinctrl/pinctrl-bindings.txt for details of the property values. + - num-pwms: the number of PWM channels. Example: pwm0: pwm@11006000 { @@ -37,4 +37,5 @@ Example: "pwm3", "pwm4", "pwm5"; pinctrl-names = "default"; pinctrl-0 = <&pwm0_pins>; + num-pwms = <5>; }; From patchwork Wed Aug 14 10:43:37 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Shih X-Patchwork-Id: 1146942 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 467mSP71RLz9sNp for ; Wed, 14 Aug 2019 20:45:09 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726126AbfHNKpF (ORCPT ); Wed, 14 Aug 2019 06:45:05 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:45070 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726551AbfHNKpE (ORCPT ); Wed, 14 Aug 2019 06:45:04 -0400 X-UUID: 82b81f65d0234156ae6ce57c1a2a9544-20190814 X-UUID: 82b81f65d0234156ae6ce57c1a2a9544-20190814 Received: from mtkexhb02.mediatek.inc [(172.21.101.103)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0707 with TLS) with ESMTP id 1209167984; Wed, 14 Aug 2019 18:44:56 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs05n1.mediatek.inc (172.21.101.15) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Wed, 14 Aug 2019 18:44:57 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Wed, 14 Aug 2019 18:44:57 +0800 From: Sam Shih To: Rob Herring , Mark Rutland , Matthias Brugger , Thierry Reding CC: Ryder Lee , John Crispin , , , , , Sam Shih Subject: [PATCH v2 7/10] dt-bindings: pwm: update bindings for MT7629 SoC Date: Wed, 14 Aug 2019 18:43:37 +0800 Message-ID: <0ae03abe4ff77c67c137d71185c89b1a88293365.1548313019.git.ryder.lee@mediatek.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <621e49c01b943edb6ddac9182f34719eb0727f01.1548313019.git.ryder.lee@mediatek.com> References: <621e49c01b943edb6ddac9182f34719eb0727f01.1548313019.git.ryder.lee@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Ryder Lee This updates bindings for MT7629 pwm controller. Signed-off-by: Ryder Lee Signed-off-by: Sam Shih Reviewed-by: Matthias Brugger --- Documentation/devicetree/bindings/pwm/pwm-mediatek.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/pwm/pwm-mediatek.txt b/Documentation/devicetree/bindings/pwm/pwm-mediatek.txt index ea95b49..c7bd563 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-mediatek.txt +++ b/Documentation/devicetree/bindings/pwm/pwm-mediatek.txt @@ -6,6 +6,7 @@ Required properties: - "mediatek,mt7622-pwm": found on mt7622 SoC. - "mediatek,mt7623-pwm": found on mt7623 SoC. - "mediatek,mt7628-pwm": found on mt7628 SoC. + - "mediatek,mt7629-pwm", "mediatek,mt7622-pwm": found on mt7629 SoC. - reg: physical base address and length of the controller's registers. - #pwm-cells: must be 2. See pwm.txt in this directory for a description of the cell format. From patchwork Wed Aug 14 10:43:39 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sam Shih X-Patchwork-Id: 1146949 Return-Path: X-Original-To: incoming-dt@patchwork.ozlabs.org Delivered-To: patchwork-incoming-dt@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=devicetree-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 467mSj6zQFz9sNy for ; Wed, 14 Aug 2019 20:45:25 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726931AbfHNKpM (ORCPT ); Wed, 14 Aug 2019 06:45:12 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:29419 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726551AbfHNKpL (ORCPT ); Wed, 14 Aug 2019 06:45:11 -0400 X-UUID: da896fad1a3f48d6ab0961ca83e2064c-20190814 X-UUID: da896fad1a3f48d6ab0961ca83e2064c-20190814 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0707 with TLS) with ESMTP id 52192520; Wed, 14 Aug 2019 18:45:05 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs05n1.mediatek.inc (172.21.101.15) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Wed, 14 Aug 2019 18:45:07 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Wed, 14 Aug 2019 18:45:07 +0800 From: Sam Shih To: Rob Herring , Mark Rutland , Matthias Brugger , Thierry Reding CC: Ryder Lee , John Crispin , , , , , sam shih Subject: [PATCH v2 9/10] dt-bindings: pwm: update bindings for MT7628 SoC Date: Wed, 14 Aug 2019 18:43:39 +0800 Message-ID: <1565779497-23621-2-git-send-email-sam.shih@mediatek.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <621e49c01b943edb6ddac9182f34719eb0727f01.1548313019.git.ryder.lee@mediatek.com> References: <621e49c01b943edb6ddac9182f34719eb0727f01.1548313019.git.ryder.lee@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: devicetree-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: sam shih This updates bindings for MT7628 pwm controller. Signed-off-by: Sam Shih --- .../devicetree/bindings/pwm/pwm-mediatek.txt | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/Documentation/devicetree/bindings/pwm/pwm-mediatek.txt b/Documentation/devicetree/bindings/pwm/pwm-mediatek.txt index c7bd5633d1eb..9d2d893a07ff 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-mediatek.txt +++ b/Documentation/devicetree/bindings/pwm/pwm-mediatek.txt @@ -21,6 +21,8 @@ Required properties: - pinctrl-0: One property must exist for each entry in pinctrl-names. See pinctrl/pinctrl-bindings.txt for details of the property values. - num-pwms: the number of PWM channels. + - clock-frequency: fix clock frequency, this is an optional property, only use in MT7628 SoC + for period calculation. This SoC has no complex clock tree. Example: pwm0: pwm@11006000 { @@ -40,3 +42,13 @@ Example: pinctrl-0 = <&pwm0_pins>; num-pwms = <5>; }; +MT7628 Example: + pwm: pwm@5000 { + compatible = "mediatek,mt7628-pwm"; + reg = <0x5000 0x1000>; + #pwm-cells = <2>; + pinctrl-names = "default"; + pinctrl-0 = <&pwm0_pins>, <&pwm1_pins>; + num-pwms = <4>; + clock-frequency = <100000>; + };