From patchwork Wed Aug 14 08:41:09 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Richard Sandiford X-Patchwork-Id: 1146847 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-506882-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=arm.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="E1P1V7uL"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 467jjc451xz9sDB for ; Wed, 14 Aug 2019 18:41:24 +1000 (AEST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:mime-version:content-type; q=dns; s= default; b=hRcBl1ZpjLdzVKX5bvXaVYy2+DRtl8AMtyYaUbZHFuFNFKyjupNBl NhFCkEpVdX4p3SvsJub0NyUGzEpu/3DJvKBkK1P3dBTxHOPrNBoyTs64PDGEQXdh z8yKLB3yiVfE6KJ9l/+h+qkYVSecoLuF3niwC39/iZMA29cCmUF5Co= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender:from :to:subject:date:message-id:mime-version:content-type; s= default; bh=6WUFnVH7jAPPMWOIJsNQfUDVDNs=; b=E1P1V7uLsUMrNbXkvIuV d9zvltOnWH+VVLLF17btvigi0vk5kV+0PNdXJp4IWOBdHSKt8Cp7tdTh8EcxycXW XyeV8Jhk5S1KyNVQ2UlOtJBgDyqOp1p9J0vtBm9bMXu4HDsoR2tBRJ32ClY7ZEMZ tcDpSW3Qiw5quc5BjgudLJ0= Received: (qmail 75184 invoked by alias); 14 Aug 2019 08:41:14 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 75061 invoked by uid 89); 14 Aug 2019 08:41:14 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-8.4 required=5.0 tests=AWL, BAYES_00, GIT_PATCH_2, GIT_PATCH_3, KAM_ASCII_DIVIDERS, SPF_PASS autolearn=ham version=3.3.1 spammy= X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.110.172) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 14 Aug 2019 08:41:12 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id E1069337 for ; Wed, 14 Aug 2019 01:41:10 -0700 (PDT) Received: from localhost (e121540-lin.manchester.arm.com [10.32.99.62]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 889D53F694 for ; Wed, 14 Aug 2019 01:41:10 -0700 (PDT) From: Richard Sandiford To: gcc-patches@gcc.gnu.org Mail-Followup-To: gcc-patches@gcc.gnu.org, richard.sandiford@arm.com Subject: [committed][AArch64] Rearrange SVE conversion patterns Date: Wed, 14 Aug 2019 09:41:09 +0100 Message-ID: User-Agent: Gnus/5.13 (Gnus v5.13) Emacs/26.1 (gnu/linux) MIME-Version: 1.0 X-IsSubscribed: yes The SVE int<->float conversion patterns need to handle various combinations of modes, making sure that the predicate mode is based on the widest element size. We did this using separate patterns for conversions involving: - HF (converting to/from [HSD]I, predicated based on the int operand) - SF (converting to/from [SD]I, predicated based on the int operand) - DF (converting to/from [SD]I, predicated based on the float operand) This worked, and meant that there were no redundant patterns. However, the ACLE needs various new predicated patterns too, and having three versions of each one seemed excessive. This patch instead splits the patterns into two groups rather than three. For conversions to integers: - truncating (predicated based on the source type, DF->SI only) - non-truncating (predicated based on the destination type) For conversions from integers: - extending (predicated based on the destination type, SI->DF only) - non-extending (predicated based on the source type) This means that we still don't create pattern names for the invalid combinations DF<->HI and SF<->HI. The downside is that we need to use C conditions to exclude the SI<->DF case from the non-truncating/ non-extending patterns. We therefore have two pattern names for SI<->DF, but genconditions ensures that the invalid one always has the value CODE_FOR_nothing. Tested on aarch64-linux-gnu (with and without SVE) and aarch64_be-elf. Applied as r274424. Richard 2019-08-14 Richard Sandiford gcc/ * config/aarch64/iterators.md (VNx4SI_ONLY, VNx2DF_ONLY): New mode iterators. (SVE_BHSI, SVE_SDI): Tweak comment. (SVE_HSDI): Likewise. Fix definition. (SVE_SDF): New mode iterator. (elem_bits): New mode attribute. (SVE_COND_FCVT): New int iterator. * config/aarch64/aarch64-sve.md (*v16hsf2) (*vnx4sf2) (*vnx2df2): Merge into... (*aarch64_sve__nontrunc) (*aarch64_sve__trunc): ...these new patterns. (*vnx8hf2) (*vnx4sf2) (aarch64_sve_vnx2df2): Merge into... (*aarch64_sve__nonextend) (aarch64_sve__extend): ...these new patterns. (vec_unpack_float__vnx4si): Update accordingly. (*trunc2): Replace with... (*aarch64_sve__trunc): ...this new pattern. (aarch64_sve_extend2): Replace with... (aarch64_sve__nontrunc): ...this new pattern. (vec_unpacks__): Update accordingly. Index: gcc/config/aarch64/iterators.md =================================================================== --- gcc/config/aarch64/iterators.md 2019-08-14 09:34:05.509786440 +0100 +++ gcc/config/aarch64/iterators.md 2019-08-14 09:38:47.027705882 +0100 @@ -278,6 +278,10 @@ (define_mode_iterator VMUL_CHANGE_NLANES (define_mode_iterator SVE_ALL [VNx16QI VNx8HI VNx4SI VNx2DI VNx8HF VNx4SF VNx2DF]) +;; Iterators for single modes, for "@" patterns. +(define_mode_iterator VNx4SI_ONLY [VNx4SI]) +(define_mode_iterator VNx2DF_ONLY [VNx2DF]) + ;; All SVE vector structure modes. (define_mode_iterator SVE_STRUCT [VNx32QI VNx16HI VNx8SI VNx4DI VNx16HF VNx8SF VNx4DF @@ -292,15 +296,21 @@ (define_mode_iterator SVE_BH [VNx16QI VN ;; All SVE vector modes that have 8-bit, 16-bit or 32-bit elements. (define_mode_iterator SVE_BHS [VNx16QI VNx8HI VNx4SI VNx8HF VNx4SF]) -;; All SVE integer vector modes that have 8-bit, 16-bit or 32-bit elements. +;; SVE integer vector modes that have 8-bit, 16-bit or 32-bit elements. (define_mode_iterator SVE_BHSI [VNx16QI VNx8HI VNx4SI]) -;; All SVE integer vector modes that have 16-bit, 32-bit or 64-bit elements. -(define_mode_iterator SVE_HSDI [VNx16QI VNx8HI VNx4SI]) +;; SVE integer vector modes that have 16-bit, 32-bit or 64-bit elements. +(define_mode_iterator SVE_HSDI [VNx8HI VNx4SI VNx2DI]) -;; All SVE floating-point vector modes that have 16-bit or 32-bit elements. +;; SVE floating-point vector modes that have 16-bit or 32-bit elements. (define_mode_iterator SVE_HSF [VNx8HF VNx4SF]) +;; SVE integer vector modes that have 32-bit or 64-bit elements. +(define_mode_iterator SVE_SDI [VNx4SI VNx2DI]) + +;; SVE floating-point vector modes that have 32-bit or 64-bit elements. +(define_mode_iterator SVE_SDF [VNx4SF VNx2DF]) + ;; All SVE vector modes that have 16-bit, 32-bit or 64-bit elements. (define_mode_iterator SVE_HSD [VNx8HI VNx4SI VNx2DI VNx8HF VNx4SF VNx2DF]) @@ -313,9 +323,6 @@ (define_mode_iterator SVE_S [VNx4SI VNx4 ;; All SVE vector modes that have 64-bit elements. (define_mode_iterator SVE_D [VNx2DI VNx2DF]) -;; All SVE integer vector modes that have 32-bit or 64-bit elements. -(define_mode_iterator SVE_SDI [VNx4SI VNx2DI]) - ;; All SVE integer vector modes. (define_mode_iterator SVE_I [VNx16QI VNx8HI VNx4SI VNx2DI]) @@ -629,6 +636,11 @@ (define_mode_attr sizen [(QI "8") (HI "1 (define_mode_attr sizem1 [(QI "#7") (HI "#15") (SI "#31") (DI "#63") (HF "#15") (SF "#31") (DF "#63")]) +;; The number of bits in a vector element, or controlled by a predicate +;; element. +(define_mode_attr elem_bits [(VNx8HI "16") (VNx4SI "32") (VNx2DI "64") + (VNx8HF "16") (VNx4SF "32") (VNx2DF "64")]) + ;; Attribute to describe constants acceptable in logical operations (define_mode_attr lconst [(SI "K") (DI "L")]) @@ -1647,6 +1659,7 @@ (define_int_iterator SVE_COND_FP_UNARY [ UNSPEC_COND_FRINTZ UNSPEC_COND_FSQRT]) +(define_int_iterator SVE_COND_FCVT [UNSPEC_COND_FCVT]) (define_int_iterator SVE_COND_FCVTI [UNSPEC_COND_FCVTZS UNSPEC_COND_FCVTZU]) (define_int_iterator SVE_COND_ICVTF [UNSPEC_COND_SCVTF UNSPEC_COND_UCVTF]) Index: gcc/config/aarch64/aarch64-sve.md =================================================================== --- gcc/config/aarch64/aarch64-sve.md 2019-08-14 09:34:05.505786467 +0100 +++ gcc/config/aarch64/aarch64-sve.md 2019-08-14 09:38:47.027705882 +0100 @@ -3656,40 +3656,28 @@ (define_expand "v16hsf2" +;; Predicated float-to-integer conversion, either to the same width or wider. +(define_insn "*aarch64_sve__nontrunc" [(set (match_operand:SVE_HSDI 0 "register_operand" "=w") (unspec:SVE_HSDI - [(match_operand: 1 "register_operand" "Upl") + [(match_operand: 1 "register_operand" "Upl") (match_operand:SI 3 "aarch64_sve_gp_strictness") - (match_operand:VNx8HF 2 "register_operand" "w")] + (match_operand:SVE_F 2 "register_operand" "w")] SVE_COND_FCVTI))] - "TARGET_SVE" - "fcvtz\t%0., %1/m, %2.h" -) - -;; Conversion of SF to DI or SI, predicated with a PTRUE. -(define_insn "*vnx4sf2" - [(set (match_operand:SVE_SDI 0 "register_operand" "=w") - (unspec:SVE_SDI - [(match_operand: 1 "register_operand" "Upl") - (match_operand:SI 3 "aarch64_sve_gp_strictness") - (match_operand:VNx4SF 2 "register_operand" "w")] - SVE_COND_FCVTI))] - "TARGET_SVE" - "fcvtz\t%0., %1/m, %2.s" + "TARGET_SVE && >= " + "fcvtz\t%0., %1/m, %2." ) -;; Conversion of DF to DI or SI, predicated with a PTRUE. -(define_insn "*vnx2df2" - [(set (match_operand:SVE_SDI 0 "register_operand" "=w") - (unspec:SVE_SDI +;; Predicated narrowing float-to-integer conversion. +(define_insn "*aarch64_sve__trunc" + [(set (match_operand:VNx4SI_ONLY 0 "register_operand" "=w") + (unspec:VNx4SI_ONLY [(match_operand:VNx2BI 1 "register_operand" "Upl") (match_operand:SI 3 "aarch64_sve_gp_strictness") - (match_operand:VNx2DF 2 "register_operand" "w")] + (match_operand:VNx2DF_ONLY 2 "register_operand" "w")] SVE_COND_FCVTI))] "TARGET_SVE" - "fcvtz\t%0., %1/m, %2.d" + "fcvtz\t%0., %1/m, %2." ) ;; ------------------------------------------------------------------------- @@ -3751,41 +3739,29 @@ (define_expand "vnx8hf2" - [(set (match_operand:VNx8HF 0 "register_operand" "=w") - (unspec:VNx8HF - [(match_operand: 1 "register_operand" "Upl") +;; Predicated integer-to-float conversion, either to the same width or +;; narrower. +(define_insn "*aarch64_sve__nonextend" + [(set (match_operand:SVE_F 0 "register_operand" "=w") + (unspec:SVE_F + [(match_operand: 1 "register_operand" "Upl") (match_operand:SI 3 "aarch64_sve_gp_strictness") (match_operand:SVE_HSDI 2 "register_operand" "w")] SVE_COND_ICVTF))] - "TARGET_SVE" - "cvtf\t%0.h, %1/m, %2." + "TARGET_SVE && >= " + "cvtf\t%0., %1/m, %2." ) -;; Conversion of DI or SI to the same number of SFs, predicated with a PTRUE. -(define_insn "*vnx4sf2" - [(set (match_operand:VNx4SF 0 "register_operand" "=w") - (unspec:VNx4SF - [(match_operand: 1 "register_operand" "Upl") - (match_operand:SI 3 "aarch64_sve_gp_strictness") - (match_operand:SVE_SDI 2 "register_operand" "w")] - SVE_COND_ICVTF))] - "TARGET_SVE" - "cvtf\t%0.s, %1/m, %2." -) - -;; Conversion of DI or SI to DF, predicated with a PTRUE. -(define_insn "aarch64_sve_vnx2df2" - [(set (match_operand:VNx2DF 0 "register_operand" "=w") - (unspec:VNx2DF +;; Predicated widening integer-to-float conversion. +(define_insn "aarch64_sve__extend" + [(set (match_operand:VNx2DF_ONLY 0 "register_operand" "=w") + (unspec:VNx2DF_ONLY [(match_operand:VNx2BI 1 "register_operand" "Upl") (match_operand:SI 3 "aarch64_sve_gp_strictness") - (match_operand:SVE_SDI 2 "register_operand" "w")] + (match_operand:VNx4SI_ONLY 2 "register_operand" "w")] SVE_COND_ICVTF))] "TARGET_SVE" - "cvtf\t%0.d, %1/m, %2." + "cvtf\t%0., %1/m, %2." ) ;; ------------------------------------------------------------------------- @@ -3821,7 +3797,7 @@ (define_expand "vec_unpack_flo (temp, operands[1], operands[1])); rtx ptrue = aarch64_ptrue_reg (VNx2BImode); rtx strictness = gen_int_mode (SVE_RELAXED_GP, SImode); - emit_insn (gen_aarch64_sve_vnx4sivnx2df2 + emit_insn (gen_aarch64_sve__extendvnx4sivnx2df (operands[0], ptrue, temp, strictness)); DONE; } @@ -3859,17 +3835,16 @@ (define_expand "vec_pack_trunc_" } ) -;; Conversion of DFs to the same number of SFs, or SFs to the same number -;; of HFs. -(define_insn "*trunc2" +;; Predicated float-to-float truncation. +(define_insn "*aarch64_sve__trunc" [(set (match_operand:SVE_HSF 0 "register_operand" "=w") (unspec:SVE_HSF - [(match_operand: 1 "register_operand" "Upl") + [(match_operand: 1 "register_operand" "Upl") (match_operand:SI 3 "aarch64_sve_gp_strictness") - (match_operand: 2 "register_operand" "w")] - UNSPEC_COND_FCVT))] - "TARGET_SVE" - "fcvt\t%0., %1/m, %2." + (match_operand:SVE_SDF 2 "register_operand" "w")] + SVE_COND_FCVT))] + "TARGET_SVE && > " + "fcvt\t%0., %1/m, %2." ) ;; ------------------------------------------------------------------------- @@ -3899,23 +3874,22 @@ (define_expand "vec_unpacks__ (temp, operands[1], operands[1])); rtx ptrue = aarch64_ptrue_reg (mode); rtx strictness = gen_int_mode (SVE_RELAXED_GP, SImode); - emit_insn (gen_aarch64_sve_extend2 + emit_insn (gen_aarch64_sve_fcvt_nontrunc (operands[0], ptrue, temp, strictness)); DONE; } ) -;; Conversion of SFs to the same number of DFs, or HFs to the same number -;; of SFs. -(define_insn "aarch64_sve_extend2" - [(set (match_operand: 0 "register_operand" "=w") - (unspec: - [(match_operand: 1 "register_operand" "Upl") +;; Predicated float-to-float extension. +(define_insn "aarch64_sve__nontrunc" + [(set (match_operand:SVE_SDF 0 "register_operand" "=w") + (unspec:SVE_SDF + [(match_operand: 1 "register_operand" "Upl") (match_operand:SI 3 "aarch64_sve_gp_strictness") (match_operand:SVE_HSF 2 "register_operand" "w")] - UNSPEC_COND_FCVT))] - "TARGET_SVE" - "fcvt\t%0., %1/m, %2." + SVE_COND_FCVT))] + "TARGET_SVE && > " + "fcvt\t%0., %1/m, %2." ) ;; -------------------------------------------------------------------------