From patchwork Tue Aug 13 18:20:56 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Uros Bizjak X-Patchwork-Id: 1146533 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=pass (mailfrom) smtp.mailfrom=gcc.gnu.org (client-ip=209.132.180.131; helo=sourceware.org; envelope-from=gcc-patches-return-506843-incoming=patchwork.ozlabs.org@gcc.gnu.org; receiver=) Authentication-Results: ozlabs.org; dmarc=fail (p=none dis=none) header.from=gmail.com Authentication-Results: ozlabs.org; dkim=pass (1024-bit key; unprotected) header.d=gcc.gnu.org header.i=@gcc.gnu.org header.b="PywwC7gM"; dkim=fail reason="signature verification failed" (2048-bit key; unprotected) header.d=gmail.com header.i=@gmail.com header.b="aTpCwx/j"; dkim-atps=neutral Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ozlabs.org (Postfix) with ESMTPS id 467LdF29RMz9sN6 for ; Wed, 14 Aug 2019 04:21:19 +1000 (AEST) DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:from:date:message-id:subject:to:content-type; q= dns; s=default; b=lEsBlQWBEbethbWvFPRsY2iJlQkdOTSDkQQCpeUYU3+IIe xP+ziDI3nfsCvIXE6eTTE9AZG5RqFHPjcAWkhaANjAjKT5HvmWYF/vncJWDVRpAR aTS4d3g3Qsk0hYZZ6RmKZYDDPkvfKUX737T/azXwfiQxWShgGCZg49zk6Matw= DKIM-Signature: v=1; a=rsa-sha1; c=relaxed; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:from:date:message-id:subject:to:content-type; s= default; bh=XB95noxxWBGnyImapA1zzVMCKOU=; b=PywwC7gMs504z8lQwlte heRN7lW/Q2WEZvkxPI3fIiS6hdppRC4Q/MsBTA7BvkAObfpR62Etp4HYRmnYdJRJ Sh2a8foB+sDSwdBlD0b7CYDWdPqavqdaMuQ0Gm8eU85ByqDqvCBi/ewPvHyeJeCU WMlnv1gTsOpwoK3boi8rOm8= Received: (qmail 19115 invoked by alias); 13 Aug 2019 18:21:11 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Received: (qmail 19107 invoked by uid 89); 13 Aug 2019 18:21:10 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-15.1 required=5.0 tests=AWL, BAYES_00, FREEMAIL_FROM, GIT_PATCH_0, GIT_PATCH_1, GIT_PATCH_2, GIT_PATCH_3, RCVD_IN_DNSWL_NONE, SPF_PASS autolearn=ham version=3.3.1 spammy=yyv X-HELO: mail-ot1-f51.google.com Received: from mail-ot1-f51.google.com (HELO mail-ot1-f51.google.com) (209.85.210.51) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 13 Aug 2019 18:21:09 +0000 Received: by mail-ot1-f51.google.com with SMTP id e12so31938439otp.10 for ; Tue, 13 Aug 2019 11:21:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=mime-version:from:date:message-id:subject:to; bh=qSzbNuKRsWVwbkAEa0s4dM86appo5wI8r5hlzkbjNLs=; b=aTpCwx/jhGgNBfYl91WQQcy5Wj+gd0+GRv9nxIieq+1tude+ObzkDFm01FYNSJxT1z pHC+VMVeXRJLpRZ2AIVYN+c5LrP0qBxhDe2us0wP6h1kP41GMM3orQXAVQEoJPPq5PbF fMFTqFKbUMYOx/A1vJLO17mitdb3hWhTmgOoPTu/Qh9stTDJhk9kk9VrSFiQNwyE2hpH TjmfFH/4zxX13ucIjVLuqboy7Lw3rFF3acUb0dP2zQ+nH6JkMfXfXp6ZE2KqsR2ohkpy gcxj2x7PMeVpXZ8BqDcqoE/6BHahXR0cKrrPqBXvN9gtLpg3ywSKR575YnfisdNpSbT7 YfOg== MIME-Version: 1.0 From: Uros Bizjak Date: Tue, 13 Aug 2019 20:20:56 +0200 Message-ID: Subject: [PATCH, i386]: Add missing *mmx_pextrb and *mmx_pextr{b, w}_zext patterns To: "gcc-patches@gcc.gnu.org" We can implement these for TARGET_MMX_WITH_SSE (and TARGET_SSE4_1 in case of.pextrb). 2019-08-13 Uroš Bizjak * config/i386/i386.md (ix86_expand_vector_extract) : Use vec_extr path for TARGET_MMX_WITH_SSE && TARGET_SSE4_1. : Ditto. * config/i386/mmx.md (*mmx_pextrw_zext): Rename from mmx_pextrw. Use SWI48 mode iterator. Use %k to output operand 0. (*mmx_pextrw): New insn pattern. (*mmx_pextrb): Ditto. (*mmx_pextrb_zext): Ditto. Bootstrapped and regression tested on x86_64-linux-gnu {,-m32}. Committed to mainline SVN. Uros. diff --git a/gcc/config/i386/i386-expand.c b/gcc/config/i386/i386-expand.c index 718de73395c4..176347cd4e6d 100644 --- a/gcc/config/i386/i386-expand.c +++ b/gcc/config/i386/i386-expand.c @@ -14617,6 +14617,11 @@ ix86_expand_vector_extract (bool mmx_ok, rtx target, rtx vec, int elt) switch (mode) { case E_V2SImode: + use_vec_extr = TARGET_MMX_WITH_SSE && TARGET_SSE4_1; + if (use_vec_extr) + break; + /* FALLTHRU */ + case E_V2SFmode: if (!mmx_ok) break; @@ -14866,7 +14871,10 @@ ix86_expand_vector_extract (bool mmx_ok, rtx target, rtx vec, int elt) return; case E_V8QImode: + use_vec_extr = TARGET_MMX_WITH_SSE && TARGET_SSE4_1; /* ??? Could extract the appropriate HImode element and shift. */ + break; + default: break; } diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md index 5ae27c85fe5c..33eb15fae207 100644 --- a/gcc/config/i386/mmx.md +++ b/gcc/config/i386/mmx.md @@ -1510,23 +1510,73 @@ (set_attr "prefix" "orig,vex") (set_attr "mode" "TI")]) -(define_insn "mmx_pextrw" - [(set (match_operand:SI 0 "register_operand" "=r,r") - (zero_extend:SI +(define_insn "*mmx_pextrw" + [(set (match_operand:HI 0 "register_sse4nonimm_operand" "=r,r,m") + (vec_select:HI + (match_operand:V4HI 1 "register_operand" "y,Yv,Yv") + (parallel [(match_operand:SI 2 "const_0_to_3_operand" "n,n,n")])))] + "(TARGET_MMX || TARGET_MMX_WITH_SSE) + && (TARGET_SSE || TARGET_3DNOW_A)" + "@ + pextrw\t{%2, %1, %k0|%k0, %1, %2} + %vpextrw\t{%2, %1, %k0|%k0, %1, %2} + %vpextrw\t{%2, %1, %0|%0, %1, %2}" + [(set_attr "isa" "*,sse2,sse4") + (set_attr "mmx_isa" "native,*,*") + (set_attr "type" "mmxcvt,sselog1,sselog1") + (set_attr "length_immediate" "1") + (set_attr "prefix" "orig,maybe_vex,maybe_vex") + (set_attr "mode" "DI,TI,TI")]) + +(define_insn "*mmx_pextrw_zext" + [(set (match_operand:SWI48 0 "register_operand" "=r,r") + (zero_extend:SWI48 (vec_select:HI (match_operand:V4HI 1 "register_operand" "y,Yv") (parallel [(match_operand:SI 2 "const_0_to_3_operand" "n,n")]))))] "(TARGET_MMX || TARGET_MMX_WITH_SSE) && (TARGET_SSE || TARGET_3DNOW_A)" "@ - pextrw\t{%2, %1, %0|%0, %1, %2} - %vpextrw\t{%2, %1, %0|%0, %1, %2}" + pextrw\t{%2, %1, %k0|%k0, %1, %2} + %vpextrw\t{%2, %1, %k0|%k0, %1, %2}" [(set_attr "isa" "*,sse2") (set_attr "mmx_isa" "native,*") (set_attr "type" "mmxcvt,sselog1") (set_attr "length_immediate" "1") + (set_attr "prefix" "orig,maybe_vex") (set_attr "mode" "DI,TI")]) +(define_insn "*mmx_pextrb" + [(set (match_operand:QI 0 "nonimmediate_operand" "=r,m") + (vec_select:QI + (match_operand:V8QI 1 "register_operand" "Yv,Yv") + (parallel [(match_operand:SI 2 "const_0_to_7_operand" "n,n")])))] + "TARGET_MMX_WITH_SSE && TARGET_SSE4_1" + "@ + %vpextrb\t{%2, %1, %k0|%k0, %1, %2} + %vpextrb\t{%2, %1, %0|%0, %1, %2}" + [(set_attr "type" "sselog1") + (set_attr "prefix_data16" "1") + (set_attr "prefix_extra" "1") + (set_attr "length_immediate" "1") + (set_attr "prefix" "maybe_vex") + (set_attr "mode" "TI")]) + +(define_insn "*mmx_pextrb_zext" + [(set (match_operand:SWI248 0 "register_operand" "=r") + (zero_extend:SWI248 + (vec_select:QI + (match_operand:V8QI 1 "register_operand" "Yv") + (parallel [(match_operand:SI 2 "const_0_to_7_operand" "n")]))))] + "TARGET_MMX_WITH_SSE && TARGET_SSE4_1" + "%vpextrb\t{%2, %1, %k0|%k0, %1, %2}" + [(set_attr "type" "sselog1") + (set_attr "prefix_data16" "1") + (set_attr "prefix_extra" "1") + (set_attr "length_immediate" "1") + (set_attr "prefix" "maybe_vex") + (set_attr "mode" "TI")]) + (define_expand "mmx_pshufw" [(match_operand:V4HI 0 "register_operand") (match_operand:V4HI 1 "register_mmxmem_operand")