From patchwork Tue Aug 13 10:37:58 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Andr=C3=A9_Draszik?= X-Patchwork-Id: 1146194 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=andred.net Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 4678Lk3SjDz9sN6 for ; Tue, 13 Aug 2019 20:38:06 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727150AbfHMKiF (ORCPT ); Tue, 13 Aug 2019 06:38:05 -0400 Received: from mail-wm1-f65.google.com ([209.85.128.65]:33482 "EHLO mail-wm1-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726086AbfHMKiF (ORCPT ); Tue, 13 Aug 2019 06:38:05 -0400 Received: by mail-wm1-f65.google.com with SMTP id p77so772204wme.0; Tue, 13 Aug 2019 03:38:03 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=IRI9xzFxMKHfeehDsl2GFQBy7QLiUvO6l2kHk0UQE0g=; b=aCI51qO34X/uPszR7lNNZE1/e1jxWIwIBk8l9oePyQwmSP0bFzbVeCDYVtMpEqNWr7 QdMZRXwK1Oveq4ovY3DMACXY3Hzznyx3JNqpQJE+GHlaEGQ4Lo+l3A31Ru66W6ACXEUh NfsgAzBW43voti8rf6Zr7Zfj6jhG0petXi7SO0OQ6u9WOeKDBDB5rl9DBGb1KQCPGyYN 8II2YfhXnNEwdmofyxEiyhIEtNJHteNFx2aVymiK64VilodcocPKIZTKrZp7FygzGQKR I17VuYM/66iXMfyeLqZDO2Iu9MxBe1DCL+nBMwzRFU7kDgi2H1fb4+eMjP9ThcnmSKo9 4WKw== X-Gm-Message-State: APjAAAVfqwwrJpQgFlZCWKstHwC+QCd1clanezcc2Lr/WNWax93i5yuZ icjtCMks1VPag2GMiEh/APZor7rI9LzsoQ== X-Google-Smtp-Source: APXvYqykijlq6kdHHcALNJ7kMDqWm4cQ80tA6EmpKRsiGVizuQU+0b4coATfODqCKbQAlhZg4Rcazw== X-Received: by 2002:a1c:f409:: with SMTP id z9mr2408158wma.176.1565692682962; Tue, 13 Aug 2019 03:38:02 -0700 (PDT) Received: from 1aq-andre.garage.tyco.com ([77.107.218.170]) by smtp.gmail.com with ESMTPSA id f70sm1484635wme.22.2019.08.13.03.38.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Aug 2019 03:38:02 -0700 (PDT) From: =?utf-8?q?Andr=C3=A9_Draszik?= To: linux-kernel@vger.kernel.org Cc: =?utf-8?q?Andr=C3=A9_Draszik?= , Richard Zhu , Lucas Stach , Lorenzo Pieralisi , Bjorn Helgaas , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH 1/2] PCIe: imx6: imx7d: add support for internal phy refclk source Date: Tue, 13 Aug 2019 11:37:58 +0100 Message-Id: <20190813103759.38358-1-git@andred.net> X-Mailer: git-send-email 2.23.0.rc1 MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org The i.MX7D variant of the IP can use either an external crystal oscillator input or an internal clock input as a reference clock input for the PCIe PHY. Add support for an optional property 'fsl,pcie-phy-refclk-internal' If present then the internal clock input is used as PCIe PHY reference clock source. The previous default of using an external ocsillator input (if the property doesn't exist), doesn't change. Signed-off-by: André Draszik Cc: Richard Zhu Cc: Lucas Stach Cc: Lorenzo Pieralisi Cc: Bjorn Helgaas Cc: Shawn Guo Cc: Sascha Hauer Cc: Pengutronix Kernel Team Cc: Fabio Estevam Cc: NXP Linux Team Cc: linux-pci@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org --- drivers/pci/controller/dwc/pci-imx6.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index 9b5cb5b70389..bb3700c9157c 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -63,6 +63,7 @@ struct imx6_pcie { struct dw_pcie *pci; int reset_gpio; bool gpio_active_high; + bool phy_refclk_internal; struct clk *pcie_bus; struct clk *pcie_phy; struct clk *pcie_inbound_axi; @@ -635,7 +636,10 @@ static void imx6_pcie_init_phy(struct imx6_pcie *imx6_pcie) break; case IMX7D: regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, - IMX7D_GPR12_PCIE_PHY_REFCLK_SEL, 0); + IMX7D_GPR12_PCIE_PHY_REFCLK_SEL, + imx6_pcie->phy_refclk_internal + ? IMX7D_GPR12_PCIE_PHY_REFCLK_SEL + : 0); break; case IMX6SX: regmap_update_bits(imx6_pcie->iomuxc_gpr, IOMUXC_GPR12, @@ -1171,6 +1175,9 @@ static int imx6_pcie_probe(struct platform_device *pdev) if (ret) imx6_pcie->link_gen = 1; + imx6_pcie->phy_refclk_internal = + of_property_read_bool(node, "fsl,pcie-phy-refclk-internal"); + imx6_pcie->vpcie = devm_regulator_get_optional(&pdev->dev, "vpcie"); if (IS_ERR(imx6_pcie->vpcie)) { if (PTR_ERR(imx6_pcie->vpcie) == -EPROBE_DEFER) From patchwork Tue Aug 13 10:37:59 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Andr=C3=A9_Draszik?= X-Patchwork-Id: 1146195 X-Patchwork-Delegate: lorenzo.pieralisi@arm.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Authentication-Results: ozlabs.org; spf=none (mailfrom) smtp.mailfrom=vger.kernel.org (client-ip=209.132.180.67; helo=vger.kernel.org; envelope-from=linux-pci-owner@vger.kernel.org; receiver=) Authentication-Results: ozlabs.org; dmarc=none (p=none dis=none) header.from=andred.net Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 4678Ln2T1dz9sN6 for ; Tue, 13 Aug 2019 20:38:09 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726086AbfHMKiI (ORCPT ); Tue, 13 Aug 2019 06:38:08 -0400 Received: from mail-wr1-f66.google.com ([209.85.221.66]:33290 "EHLO mail-wr1-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727221AbfHMKiH (ORCPT ); Tue, 13 Aug 2019 06:38:07 -0400 Received: by mail-wr1-f66.google.com with SMTP id n9so107389633wru.0; Tue, 13 Aug 2019 03:38:05 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=7fA4ImgTXDy54WkrrWpZEbCCgZQJp3nUMqu6kivAEHE=; b=FO/qnFt/sp+xk1BO5CqMw5J+EBN6WhpvDsaH/h/m97kzOLovP8o3zbMeR3Q+lQ0O3v 5tYOH31Nv0sjwLJx+M1zz3SA76u6UtpKXPfQpRiU59ZASLelyufcH8aQDoq7bJa5qjJz BnuMb4V2qzu/DHgRRcWc4x2Ibkm98qe9U1IC8TP7Ohr7aZcvPA3VqzAEUMdv+MI8CINx gxw2kVQW0MvOj80ljfymDjp1lY39xAHBi7QlMCCtpDoNsZGNqDZUOzfGJWuPfibiRj2k R0HZEptCID9CBG2x66CtNGLXLcAy9YgYN/dHGLinDt8DyClLmTZRLdakmXpDgKzzdQye 0vfQ== X-Gm-Message-State: APjAAAV1zfihnhkTQrKE2hlG+WRY2iALHvWeofk+kPmr8j4vjqkwRSVz vVc62GSW0z1EwDSXWWWZmrIAVNaQ+qVbpw== X-Google-Smtp-Source: APXvYqwJhQAcPo3ERBZnabP8qqSJfaIMlg+cCQT9+ITjd2tPgcv7HbOe4c56c7ufaMOznaURXCPzuw== X-Received: by 2002:a5d:610d:: with SMTP id v13mr36286575wrt.249.1565692684135; Tue, 13 Aug 2019 03:38:04 -0700 (PDT) Received: from 1aq-andre.garage.tyco.com ([77.107.218.170]) by smtp.gmail.com with ESMTPSA id f70sm1484635wme.22.2019.08.13.03.38.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 13 Aug 2019 03:38:03 -0700 (PDT) From: =?utf-8?q?Andr=C3=A9_Draszik?= To: linux-kernel@vger.kernel.org Cc: =?utf-8?q?Andr=C3=A9_Draszik?= , Richard Zhu , Lucas Stach , Bjorn Helgaas , Rob Herring , Mark Rutland , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , NXP Linux Team , linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org Subject: [PATCH 2/2] dt-bindings: imx6q-pcie: add "fsl, pcie-phy-refclk-internal" for i.MX7D Date: Tue, 13 Aug 2019 11:37:59 +0100 Message-Id: <20190813103759.38358-2-git@andred.net> X-Mailer: git-send-email 2.23.0.rc1 In-Reply-To: <20190813103759.38358-1-git@andred.net> References: <20190813103759.38358-1-git@andred.net> MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org The i.MX7D variant of the IP can use either an external crystal oscillator input or an internal clock input as a reference clock input for the PCIe PHY. Document the optional property 'fsl,pcie-phy-refclk-internal' Signed-off-by: André Draszik Cc: Richard Zhu Cc: Lucas Stach Cc: Bjorn Helgaas Cc: Rob Herring Cc: Mark Rutland Cc: Shawn Guo Cc: Sascha Hauer Cc: Pengutronix Kernel Team Cc: Fabio Estevam Cc: NXP Linux Team Cc: linux-pci@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: devicetree@vger.kernel.org Cc: linux-kernel@vger.kernel.org --- Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt index a7f5f5afa0e6..985d7083df9f 100644 --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie.txt @@ -56,6 +56,11 @@ Additional required properties for imx7d-pcie and imx8mq-pcie: - "turnoff" - fsl,imx7d-pcie-phy: A phandle to an fsl,imx7d-pcie-phy node. +Additional optional properties for imx7d-pcie: +- fsl,pcie-phy-refclk-internal: If present then an internal PLL input is used + as PCIe PHY reference clock source. By default an external ocsillator input + is used. + Additional required properties for imx8mq-pcie: - clock-names: Must include the following additional entries: - "pcie_aux"